WO2004061935A1 - Method for forming bump, semiconductor devcie and its manufacturing method, substrate treatment device, and semiconductor manufacturing apparatus - Google Patents

Method for forming bump, semiconductor devcie and its manufacturing method, substrate treatment device, and semiconductor manufacturing apparatus Download PDF

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Publication number
WO2004061935A1
WO2004061935A1 PCT/JP2003/005092 JP0305092W WO2004061935A1 WO 2004061935 A1 WO2004061935 A1 WO 2004061935A1 JP 0305092 W JP0305092 W JP 0305092W WO 2004061935 A1 WO2004061935 A1 WO 2004061935A1
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WO
WIPO (PCT)
Prior art keywords
bump
bumps
semiconductor
substrate
forming
Prior art date
Application number
PCT/JP2003/005092
Other languages
French (fr)
Japanese (ja)
Inventor
Masataka Mizukoshi
Yoshikatsu Ishizuki
Kanae Nakagawa
Keishiro Okamoto
Kazuo Teshirogi
Taiji Sakai
Original Assignee
Fujitsu Limited
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Limited filed Critical Fujitsu Limited
Priority to JP2004564465A priority Critical patent/JP4279786B2/en
Publication of WO2004061935A1 publication Critical patent/WO2004061935A1/en
Priority to US11/083,926 priority patent/US20050161814A1/en
Priority to US12/413,898 priority patent/US8962470B2/en
Priority to US14/600,590 priority patent/US20150132865A1/en

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    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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Definitions

  • the present invention relates to a method for forming fine bumps for making electrical connection with the outside on a surface of a substrate, a semiconductor device and a method for manufacturing the same, a substrate processing apparatus, and a semiconductor manufacturing apparatus.
  • Au bumps and the like have been used for fine metal terminals for making electrical connection to the outside on the surface of a semiconductor substrate.
  • the Au bumps are formed by plating and have a large surface roughness.
  • CMP chemical mechanical polishing
  • the metal and resin to be processed are formed relatively flat in advance, a flat polishing pad is pressed, and the surface is finely chemically and mechanically flattened using a slurry (chemical polishing material). It is to be processed.
  • the hard resin or metal surface provided in advance becomes a stop layer, and the CMP is completed.
  • the CMP method does not depend on TTV (Total Thickness Variation), which is defined by the thickness variation of the semiconductor substrate and the difference between the maximum thickness and the minimum thickness of the semiconductor substrate.
  • TTV Total Thickness Variation
  • Conventional bonding of Au bumps with large surface roughness requires a mounting method that applies a load to the bumps with a load, heat, or ultrasonic waves until the roughness is eliminated.
  • This method is based on the surface to be cut, and does not depend on the TTV of the semiconductor substrate.
  • Au bumps are used for fine connections, but the bump surfaces are so rough that it is difficult to join them.
  • a metal such as Au and a resin are simultaneously planarized using CMP, a depression called dishing appears due to a difference in polishing rate between the metal and the resin. Due to this dishing, it is necessary to apply a large load such as a load, heat, or ultrasonic wave to the bump in order to obtain a reliable bump bonding.
  • the present invention has been made in view of the above-mentioned problems, and has been proposed in place of CMP to flatten the surface of fine bumps formed on a substrate at low cost and at high speed, and to reduce inconveniences such as dishing between bumps.
  • An object of the present invention is to provide a bump forming method, a highly reliable semiconductor device, a method of manufacturing the same, and a semiconductor manufacturing device that can be easily and reliably performed without causing the generation. Disclosure of the invention
  • the method of forming a bump according to the present invention is a method of forming a bump for making an electrical connection with the outside on a surface of a substrate, the method comprising: forming an insulating film between the plurality of bumps and the pump on the surface of the substrate.
  • the semiconductor device of the present invention includes a pair of semiconductor substrates each having a plurality of bumps formed on a surface thereof for making an electrical connection with the outside.
  • a method of manufacturing a semiconductor device includes the steps of: forming a bump on each surface of a pair of semiconductor substrates so as to be embedded in an insulating film; A step of performing a planarization process so that the surface of the insulating film is continuously flat; a step of removing the insulating film; and a step of removing the semiconductor substrates from each other by flattening the surfaces of the bumps. And connecting and integrating them.
  • a method for forming a bump according to the present invention is a method for forming a bump for making an electrical connection to the outside on a surface of a substrate, comprising: forming a plurality of bumps on the surface of the substrate; And a step of performing a flattening process so that the surfaces of the plurality of bumps are continuously flattened by a cutting process.
  • a step of forming a plurality of the bumps on each surface of the pair of semiconductor chips, and a cutting process using a byte the surfaces of the plurality of bumps are continuously flattened.
  • the semiconductor device of the present invention includes a pair of semiconductor chips each having a plurality of bumps formed on a surface for electrical connection with the outside, and a surface of each of the bumps is formed on each of the semiconductor chips.
  • the semiconductor chips are continuously and uniformly flattened on the upper surface, and the semiconductor chips are formed by connecting the flattened surfaces of the bumps so as to face each other and integrated.
  • the bump forming method of the present invention is a bump for making an electrical connection to the outside on the surface of a semiconductor substrate, and a method for forming a stud bump using a wire bonding method.
  • the semiconductor device of the present invention is a bump for making an electrical connection with the outside, and has a semiconductor chip having a plurality of stud bumps formed on the surface using a wire bonding method. The upper surfaces of the bumps are continuously and uniformly flattened on the semiconductor chip.
  • the method of manufacturing a semiconductor device includes a step of forming a plurality of bumps on a surface of a semiconductor substrate and a cutting process using a byte so that the surfaces of the plurality of bumps are continuously flat.
  • the method of manufacturing a semiconductor device according to the present invention includes a step of forming a plurality of protrusions using an electric wire at a connection point on a surface of a semiconductor substrate; and a step of cutting the plurality of protrusions using a byte.
  • the semiconductor device of the present invention has a semiconductor chip having a plurality of bumps formed on a surface for electrical connection with the outside, and the surface of each bump is continuously formed on the semiconductor chip.
  • the bumps of the semiconductor chip and one ends of the lead terminals are connected and integrated, and are uniformly flattened.
  • the semiconductor device of the present invention includes a plurality of bumps for making an electrical connection with the outside, A semiconductor chip having a plurality of stud bumps formed on a surface thereof using a wire bonding method, and a surface of each of the stud bumps is continuously and uniformly planarized on the semiconductor chip; The stud bump of the semiconductor chip and one end of a lead terminal are connected and integrated.
  • the surface of the plurality of electrodes is continuously formed by introducing a semiconductor chip having a plurality of electrodes formed on its surface into an inert atmosphere, and performing cutting using a byte.
  • a semiconductor manufacturing apparatus includes a cutting means having a byte, a joining means for joining a pair of introduced substrates, and an inert gas for maintaining an environment of the cutting means and the joining means in an inert atmosphere. Atmosphere means, wherein the cutting means performs cutting using at least one of the pair of substrates having a plurality of electrodes formed on a surface thereof in the inert atmosphere using the byte.
  • the bonding unit cleans the flattened surfaces of the plurality of electrodes in the inert atmosphere.
  • the pair of bases have a function of being connected and integrated by the plurality of electrodes.
  • the substrate processing apparatus of the present invention is a substrate processing apparatus for forming a bump for making an electrical connection with the outside on a surface of a substrate, the substrate processing apparatus having a flat support surface, and A substrate support base for adsorbing to the support surface and forcibly supporting and fixing the one surface as a flat reference surface; and a byte for cutting the other surface of the substrate, and a plurality of bumps on the surface and between the bumps
  • a substrate on which an insulating film is formed is supported and fixed to the substrate support table, and cutting using the bytes is performed so that the surfaces of the bumps and the surface of the insulating film are continuously flat.
  • a flattening process is performed.
  • FIGS. 2A and 2B are schematic cross-sectional views illustrating a method of forming a bump according to the first embodiment in the order of steps.
  • 3A and 3B show the results of flattening by cutting.
  • FIG. 4A and 4B are schematic cross-sectional views showing specific examples of flattening by cutting.
  • FIG. 5 is a schematic cross-sectional view showing a specific example of flattening by cutting.
  • FIG. 6 is a block diagram showing a configuration of the cutting apparatus.
  • FIG. 7 is a schematic configuration diagram of a cutting device.
  • FIG. 8 is a flowchart of the cutting process.
  • 9A to 9C are schematic plan views illustrating a method for manufacturing a semiconductor device according to the second embodiment in the order of steps.
  • 10A to 10F are schematic cross-sectional views illustrating a method of forming a bump according to the second embodiment in the order of steps.
  • 11A and 11B are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to the third embodiment in the order of steps.
  • 12A to 12C are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to Modification 1 of the third embodiment in the order of steps.
  • FIGS. 13A to 13C are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to Modification 2 of the third embodiment in the order of steps.
  • FIG. 14A to 14F are schematic sectional views showing the method for manufacturing the semiconductor device according to the fourth embodiment in the order of steps.
  • FIGS. 15A to 15D are diagrams showing a cutting end point detection method according to the fourth embodiment.
  • FIG. 16 is a schematic sectional view illustrating the method for manufacturing the semiconductor device according to the fifth embodiment.
  • FIG. 17 is a schematic sectional view illustrating the method for manufacturing the semiconductor device according to the fifth embodiment.
  • FIG. 18 is a schematic diagram showing a semiconductor manufacturing apparatus according to the sixth embodiment.
  • the inventor of the present invention has conceived of applying cutting using a byte as a technique for simultaneously and simultaneously flattening the surface of a large number of fine bumps formed on a substrate at low cost and at high speed, instead of the CMP method. .
  • this cutting process even when a bump is buried in an insulating film on a semiconductor substrate, the bumps are simultaneously formed on the substrate without depending on the polishing rate of a metal and an insulator as in the CMP method. In this way, the metal and the insulator can be continuously cut, and both can be uniformly flattened without causing dishing or the like.
  • Metals such as copper, aluminum and nickel and insulating materials such as polyimide are materials that can be easily cut with a byte.
  • the former is a ductile metal and the latter is a resin having a rigidity of, for example, 200 GPa or more.
  • the back surface back surface
  • the TTV of a silicon substrate is in the range of 1 m to 5 m, and in the LSI process, a TTV of about 5 m does not affect photolithography and is usually not considered. .
  • the present inventor when cutting is used for flattening a semiconductor substrate, it is first necessary to control the TTV of the substrate to a target cutting accuracy or less.
  • the present inventor when using the above-mentioned cutting for flattening the bump surface, as a specific method for ensuring the flattening, grinds the back surface with reference to the substrate surface.
  • the TTV of semiconductor substrates at a level lower than the target cutting accuracy.
  • the TTV should be reduced and the thickness variation of individual semiconductor substrates should be kept below the cutting accuracy.
  • the TTV can be made even smaller, the thickness of individual semiconductor substrates can be detected during cutting. The amount of cutting can be controlled by detecting the thickness of each individual semiconductor substrate.
  • the bumps are formed by wire bonding, that is, by bonding a pole-shaped mass formed by melting the tip of the bonding wire onto the electrode pad and tearing the wire.
  • Bumps (hereinafter referred to as stud bumps).
  • a pin-shaped protrusion is formed due to tearing of the bonding wire, and therefore, it is necessary to flatten such protrusions.
  • the above-mentioned flattening method by cutting is also applied to stud bumps. In this case, when the wire is torn (pre-cut), the height of each protrusion is different, and the wire is flattened in alignment with the lowest bump.
  • the height of the protruding portion from the electrode pad at the time of precut is specified to be at least twice the wire diameter, and the diameter of the cut surface is the same as the wire diameter for all stud bumps as the end point of the cutting process. It will be the time when it becomes equal or higher.
  • the height of the stud bump after cutting and flattening can be made 1.5 times or more as compared with the case where the wire diameter is not specified, and the stress on the semiconductor element can be alleviated. Device life can be extended.
  • both the flattening process and the bonding process should be performed in a cleaning atmosphere, specifically, an inert atmosphere. L thought to do it inside. This can be dealt with by adding a cleaning step using Ar plasma or the like immediately before the bonding step, but has the disadvantage of increasing the number of steps.
  • the present invention it is possible to relatively easily maintain a flattened state that is very close to an ideal state without increasing the number of steps, and it is possible to reliably connect bumps.
  • the inventor focuses on the state of the semiconductor chip as another aspect of the present invention.
  • the TTV of the semiconductor substrate becomes a problem as described above.
  • the TTV in the chip area is cut due to its small size.
  • the inventor of the present invention has conceived of first cutting each semiconductor chip from the semiconductor substrate and then flattening the surface of the fine bumps by cutting using the above-mentioned bumps in the state of the semiconductor chip. Then, the semiconductor chips are electrically connected and joined with the bumps facing each other. As a result, the step of controlling the TTV can be omitted, and the bump bonding can be easily performed. Further, in the present invention, the above-mentioned cutting technology is applied to a semiconductor device by a so-called TAB bonding method.
  • a strip-shaped copper foil lead that has been subjected to a gold surface treatment is directly aligned with the gold-plated bump, and heated to 300 ° C or more, and one bump is formed. It requires 30 g or more of pressure bonding.
  • the stud bump method it is necessary to press the semiconductor chip on which the stud bump is formed in advance against a glass plate or a metal plate and heat it so as to flatten the tip of the stud bump.
  • the end surface of the plating has metallic and organic contaminants peculiar to irregularities and surfaces. In addition, variations in die height within the chip occur at the level of several microns.
  • TAB bonding to these terminations requires high temperatures and high loads. At high temperatures during bonding, fine pitch lead connections tend to be misaligned due to the large difference in thermal expansion between copper and silicon. On the other hand, stud bumps require a higher temperature and a higher load because the height varies widely and the shape is not constant, and it is also difficult to connect fine pitches.
  • the surfaces of the metal bumps and the stud bumps are flattened by cutting using a byte cutting technique to purify the surface, thereby reducing the temperature and the load at the time of TAB bonding and leading to a fine pitch lead. Connection can be performed without displacement.
  • a silicon semiconductor substrate is exemplified as a substrate, and a method of forming a bump provided for making electrical connection with the outside on the semiconductor substrate, a semiconductor device using this method, and a method of manufacturing the same are disclosed. .
  • FIG. 1A to 1D, 2A, and 2B are schematic cross-sectional views showing a method of forming a bump according to the present embodiment in order.
  • a silicon semiconductor substrate 1 is prepared.
  • an LSI semiconductor device (not shown) is formed.
  • the LSI half The respective steps of the semiconductor substrate 1 on which the conductor elements and the like are formed will be described below.
  • the silicon semiconductor substrate is usually not uniform in thickness as shown in FIG. Therefore, the back surface 1b of the semiconductor substrate 1 is flattened as a pre-process for performing a cutting process using a byte described later on the front surface 1a.
  • a substrate support table (not shown) having a flat support surface is prepared, and the semiconductor substrate 1 is fixed to the substrate support table by suctioning the surface 1a by suction, for example, by vacuum suction. .
  • the front surface 1a is forcibly flattened by adsorption to the support surface, whereby the front surface 1a becomes a reference surface for flattening the back surface 1b.
  • the rear surface lb is machined, in this case, mechanically ground, and the convex portion 1c of the rear surface 1b is ground and removed to be flattened.
  • the thickness of the semiconductor substrate 1 is constant, specifically, the TTV (difference between the maximum thickness and the minimum thickness of the substrate) is equal to or less than a predetermined value. TTV will be controlled to 1 / im or less.
  • the semiconductor substrate 1 is removed from the substrate support, and a photosensitive resin, for example, a photoresist is applied on the surface 1a of the semiconductor substrate 1, and the photoresist is subjected to photolithography.
  • a resist mask 12 having a predetermined bump pattern 12a is formed.
  • a metal for example, a copper film is formed by, for example, an evaporation method, and a plating electrode (not shown) is formed.
  • gold (Au) is deposited so as to bury each bump pattern 12a of the resist mask 12 by a plating method, and an Au projection 2 is formed.
  • the projections may be formed using Cu, Ag, Ni, Sn, or an alloy thereof in addition to Au.
  • the surface 1 a of the semiconductor substrate 1 is subjected to cutting using a byte to be flattened.
  • the back surface 1b is sucked to the support surface 11a of the substrate support 11 by, for example, vacuum suction, and the semiconductor substrate 1 is fixed to the substrate support 11.
  • the thickness of the semiconductor substrate 1 is kept constant by flattening the back surface 1b as shown in FIG. 1B, and the back surface 1b is also forced to undulate due to adsorption to the support surface 11a.
  • the back surface 1b becomes a reference surface for flattening the front surface 1a.
  • each Au projection 2 and the surface layer of the photoresist 12 on the surface 1a are machined, in this case, cut using a byte 10 made of diamond or the like, and each Au projection 2 and the resist mask are cut.
  • a flattening process is performed so that the surface of 12 is continuously flat. Thereby, the upper surface of the Au projection 2 is flattened to a mirror surface.
  • the results of the flattening by this cutting are shown in the micrographs and schematic diagrams of FIGS. 3A and 3B.
  • the surface of the Au projection was uneven, as shown in Fig. 3A. After cutting, however, the surface of the Au projection was highly accurate, as shown in Fig. 3B. It can be seen that it has been flattened. Subsequently, as shown in FIG. 2B, the resist mask 12 is removed by ashing or the like. At this time, on the surface 1 a of the semiconductor substrate 1, bumps 3 having a uniform height, each Au projection 2 being cut and the upper surface 3 a being flattened in a flat manner are formed. Using this semiconductor substrate 1, for example, it is chipped and then electrically connected to another semiconductor substrate 4 by a bump 3. In this embodiment, one semiconductor substrate has been described.
  • each process of this embodiment on a plurality of semiconductor substrates constituting a lot so that the thickness of each semiconductor substrate is made uniform. It is suitable.
  • the semiconductor substrate 1 is parallelized with reference to 3005092, the position of the surface 1a is detected, and the amount of shaving is calculated from the detected surface 1a for control.
  • FIG. 4A when detecting the position of the surface 1a, a plurality of locations around the surface 1a of the semiconductor substrate 1, for example, three locations shown in FIG.
  • the resist mask 12 it is preferable to irradiate the resist mask 12 with a laser beam 13 and scatter it by heating to expose a part of the surface 1a.
  • the semiconductor substrate 1 when detecting the position of the front surface 1a, the semiconductor substrate 1 is suction-fixed to the substrate support base 11 having the opening 11b, and the semiconductor substrate 1 is fixed through the opening 1
  • the back surface 1b may be irradiated with an infrared laser beam, and the reflected light from the front surface 1a may be measured by, for example, an infrared laser measuring device 14.
  • FIG. 6 is a block diagram showing the configuration of the cutting apparatus
  • FIG. 7 is a similar schematic configuration diagram.
  • the cutting apparatus includes a storage unit 101 for storing the semiconductor substrate, a hand unit 102 for transporting the semiconductor substrate 1 to each processing unit, a sensing unit 103 for positioning the semiconductor substrate 1, and a cutting unit.
  • a chuck table 104 for chucking the semiconductor substrate 1 at the time, a cutting unit 105 for flattening and cutting the semiconductor substrate 1, a cleaning unit 106 for cleaning after cutting, and a control unit 1 for controlling these. 07.
  • the chuck table section 104 constitutes a substrate support (chuck table) 11 on which the semiconductor substrate 1 is mounted and fixed as described above, and the cutting section 105 is a hard cutting tool made of diamond or the like. It has 10 bytes. Next, the flow of the cutting process will be described with reference to FIGS.
  • the transfer hand of the hand unit 102 takes out the semiconductor substrate 1 from the storage cassette 111 of the storage unit 101 in which the semiconductor substrate 1 is stored.
  • the storage unit 101 has an elevator mechanism, which moves up and down to a level at which the semiconductor substrate 1 is taken out of the transfer hand.
  • the transfer hand vacuum sucks the semiconductor substrate and transfers it to the sensing unit 103.
  • the transfer hand is a 3-axis and Z-axis scalar type pot and can be easily handled to each processing unit.
  • the mechanism of the mouth pot is not limited to this, and the XY axis perpendicular type may be used.
  • the semiconductor substrate 1 is rotated by 360 ° using the rotary table 112, the outer periphery of the semiconductor substrate 1 is imaged by the CCD camera 111, and the result is calculated by the control unit 107.
  • the processing is performed by the section to calculate one center position of the semiconductor substrate 1.
  • the transfer hand corrects the position based on the result, and transfers the semiconductor substrate 1 to the check table 104, and the check table 11 is fixed by vacuum.
  • the chuck table 11 serves as a reference surface for processing. Therefore, in order to maintain the planar accuracy at the time of fixing and at the time of processing, it is preferable that the chuck surface is made of a material having a plurality of holes and chucks the entire surface of the semiconductor substrate 1.
  • the material is metal, ceramic, resin, etc.
  • An optical sensor unit which is a light emitting unit 114, is arranged opposite to the chucked semiconductor substrate 1, and the dimensions of the semiconductor substrate 1 are measured and calculated together with a camera unit, which is a light receiving unit 115. Is fed to the X-axis drive unit of the cutting unit 105, and the movement amount for cutting is commanded.
  • the cut surface is a wiring forming surface, specifically, as shown in FIG. 4, it is preferable to irradiate a laser beam to heat and scatter the resist mask to expose the surface. Then, as shown in FIG. 5, the position is measured using a transmission sensor using infrared laser light.
  • the table on which the byte 10 for actually performing cutting is mounted moves in the X direction, and cutting is started.
  • the byte 10 used here is made of diamond or the like.
  • the cutting to the set dimension is completed.
  • the transfer hand takes out the semiconductor substrate 1 from the chuck table 11 and transfers it to the cleaning unit.
  • the cleaning unit 105 the semiconductor substrate 1 is vacuum-fixed and rotated, and the surface residual foreign matter after processing is washed away with the washing water. Then air blow While rotating at high speed, dry while washing away the washing water.
  • the transport hand takes out the semiconductor substrate 1 again, and finally stores it in the storage cassette 111 of the storage section 101.
  • the back surface is cut with reference to the bumps and the surface on which the insulating film is formed between the bumps, and then the front surface of each bump and the surface of the insulating film are cut with reference to the back surface. Complete the planarization process.
  • FIGS. 9A to 9C are schematic plan views illustrating the method for manufacturing the semiconductor device according to the present embodiment in the order of steps.
  • the semiconductor device 1 on which the LSI element and the like are mounted and which has the bumps 3 whose upper surfaces 3a are flattened by cutting using a byte is shown in FIG.
  • Each semiconductor chip 21 is cut out as shown in FIG.
  • FIG. 9B a semiconductor substrate 22 having bumps 3 whose upper surface is flattened by cutting using a byte is prepared, and each semiconductor chip is placed on the semiconductor substrate 22.
  • 2 1 is electrically connected between the flattened upper surfaces 3 a of the bumps 3.
  • the semiconductor substrate 22 and the semiconductor chip 21a are arranged so that the upper surfaces 3a face each other, and are connected by being press-bonded at room temperature to 350, here, about 170C. Since each upper surface 3a is flattened with high precision, the semiconductor substrate 2 2. and the semiconductor chip 21 can be easily connected without requiring high temperature and high pressure as in the conventional case. . Then, as shown in FIG. 9C, the semiconductor substrate 22 to which the semiconductor chip 21 is connected The semiconductor chip 23 is mounted on the substrate 24 through processes such as wire bonding (connection using the wire 25) and the like, and the semiconductor device is completed.
  • the surface of the fine bumps 3 formed on the semiconductor substrate 1 is flattened at low cost and at high speed without inconvenience such as dishing.
  • the connection of the bumps 3 can be performed easily and reliably.
  • the bumps 3 can be connected to each other without requiring conditions such as high temperature and high pressure, and a highly reliable semiconductor device can be manufactured with high yield.
  • Au is exemplified as the bump material.
  • Ni nickel
  • FIGS. 10A to 10F are schematic cross-sectional views showing a method for forming a bump according to the present embodiment in the order of steps.
  • the semiconductor substrate 1 is ground back through the same steps as in FIGS. 1A and 1B of the first embodiment, and the TTL is controlled to a predetermined value or less, specifically, 1 im or less.
  • an electrode 31 made of an aluminum-based metal is patterned on the surface of the semiconductor substrate 1, and then nickel is applied to the electrode 31 by an electroless plating method.
  • Nickel phosphorus, nickel-phosphorus-boron, nickel-boron, etc. are formed by a general-purpose electroless plating method by forming a phosphorus plating film 32 to a thickness of about 5 / zm to 10 / zm. It is formed using.
  • a nickel-phosphorous alloy is formed in a hypophosphorous acid bath (sodium hypophosphite or calcium hypophosphite), and a nickel-boron alloy is formed in a sodium borohydride bath or a weak acid bath using dimethylaminoporan.
  • a neutral bath it is formed in a neutral bath, and the nickel-phosphorus-boron alloy is formed in a neutral bath.
  • a phosphorus-enriched layer 33 which is a mechanically fragile layer, is formed on the surface of the nickel-phosphorus plating film 32, regardless of which alloy system is selected.
  • the interface strength between the plating and the solder bumps is reduced due to the phosphorus concentration layer.
  • the thickness of the phosphorus-enriched layer is about 20 nm to 40 nm, and the thickness increases as the phosphorus content in the plating bath increases.
  • this phosphorus concentration layer is generated irrespective of the underlying material (glass substrate, iron substrate, aluminum substrate) and regardless of the thickness of the plating. Further, for example, even if a nickel-based electroless plating described in Patent Document 6 is subjected to an annealing treatment at a temperature equal to or higher than the solder melting point, a phosphorus-enriched layer is always generated on the surface layer.
  • a liquid resist is coated as a protective film 34 so as to cover the surface of the substrate, thereby forming a layer for alleviating a physical impact by a cutting process described later.
  • the protective film 34 is formed by spin coating or the like to a thickness of about 10 m to 15 and curing.
  • the back surface is sucked to the support surface of the substrate support by, for example, vacuum suction, and the semiconductor substrate 1 is fixed to the substrate support. At this time, the thickness of the semiconductor substrate 1 is kept constant by the flattening process of FIG.
  • the b is forcibly absorbed into the support surface 11a, so that there is no waviness or the like, whereby the back surface 1b becomes a reference surface for flattening the front surface 1a.
  • the surface layer of each nickel phosphor coating film 32 and the protective film 34 on the surface 1a is machined, and in this case, cut using a cutting tool made of diamond or the like,
  • the phosphorus concentration layer 33 of the nickel phosphorus plating film 32 is removed, and a flattening process is performed so that the surfaces of the nickel phosphorus plating film 32 and the protective film 34 are continuously flat.
  • the amount of cutting is 1 ⁇ , which can reliably remove the phosphorus enriched layer 3 3! ⁇ 2 m.
  • a gold plating film 35 is formed on the nickel plating film 32 by an electroless plating method.
  • the thickness of the gold plating film 35 is preferably about 30 nm to 50 nm.
  • the protective film 34 is removed by ashing or the like.
  • bumps 36 are formed on the surface 1 a of the semiconductor substrate 1 with a uniform height, and the upper surface is uniformly flattened by the cutting process, and the gold plating film 35 is formed. Is performed.
  • a solder bump 37 is formed on the bump 36 as shown in FIG. 10F.
  • the solder bumps 37 are formed by screen printing, a solder pole method, melting, or the like. As a material of the solder, it is desirable to use a solder containing no lead, such as tin-silver or tin-zinc. Thereafter, the semiconductor substrate 1 is divided by full-cut dicing, and semiconductor chips are cut out to complete a semiconductor device as in the first embodiment. As described above, according to the present embodiment, in place of CMP, the surface of the nickel bump 36 formed on the semiconductor substrate 1 is flattened at low cost and at high speed without inconvenience such as dicing. This makes it possible to connect the bumps 36 with each other without requiring conditions such as high temperature and high pressure, and to produce a highly reliable semiconductor device with high yield. Can be manufactured.
  • the bump 36 having a flat upper surface can be removed.
  • the solder bumps 37 can be reliably formed.
  • FIG. 11A and 11B are schematic cross-sectional views showing the method for manufacturing the semiconductor device according to the present embodiment in the order of steps.
  • a plurality of bumps having different heights are mounted without mounting the back surface of the first embodiment, without mounting the LSI element.
  • individual semiconductor chips 41 are cut out from the semiconductor substrate on which the Au bumps 42 are formed.
  • the surface layer of the semiconductor chip 41 is machined, in this case, cut using a byte made of diamond or the like as in the first embodiment, so that the surface of each Au bump 42 is continuously flat.
  • a flattening process is performed. Thereby, the height of each Au bump 42 is made uniform, and the upper surface is flattened to a mirror surface.
  • a pair of semiconductor chips 41 are opposed to each other, and the flat upper surfaces of the Au bumps 42 are electrically connected to each other.
  • a pair of semiconductor chips 41 are arranged so as to face each other at the same upper surface, and are bonded by pressure bonding at room temperature to 350 ° C., here at about 170 °. Since each upper surface is flattened with high precision, the pair of semiconductor chips 41 can be easily connected without requiring high temperature and high pressure as in the conventional case.
  • the surface of the fine Au bump 42 formed on the semiconductor chip 41 is flattened inexpensively at high speed without inconvenience such as dishing.
  • the Au bumps 42 on the pair of semiconductor chips 41 can be easily and reliably connected. This makes it possible to connect the eight pumps 42 without requiring conditions such as high temperature and high pressure, and to manufacture a highly reliable semiconductor device with high yield.
  • the step of controlling the TTV can be omitted, which contributes to a reduction in the number of steps.
  • FIG. 12A to 12C are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to Modification 1 in the order of steps.
  • a plurality of bumps having different heights are mounted on the LSI device and the like without grinding the back surface of the first embodiment.
  • individual semiconductor chips 41 are cut out from the semiconductor substrate on which the Au bumps 42 are formed.
  • a resin layer 43 made of an insulating material is formed on the surface of the semiconductor chip 41 so as to bury the Au bumps 42.
  • the individual semiconductor chips 41 may be cut out. Subsequently, as shown in FIG.
  • the surface layer of the semiconductor chip 41 is machined.
  • cutting is performed using a byte made of diamond or the like, and each Au bump is cut.
  • a flattening process is performed so that the surface of 42 and the surface of the resin layer 43 are continuously flat.
  • the height of each Au bump 42 is made uniform, and The surface is flattened to a mirror surface.
  • the pair of semiconductor chips 41 are opposed to each other, and the Au bumps 42 and the flattened upper surfaces of the resin layer 43 are electrically connected to each other.
  • a pair of semiconductor chips 41 are arranged so that the upper surfaces thereof are opposed to each other, and are crimped at room temperature to 350 ° C., here about 170 ° C., and connected. Since both upper surfaces are flattened with high precision, the pair of semiconductor chips 41 can be easily connected without requiring high temperature, high pressure, or the like as in the related art. Further, the resin film 43 ensures the bonding of the pair of semiconductor chips 41 and also serves as an underfill for protecting the electrodes 42 and the like. As described above, according to the first modification, instead of CMP, the surface of the fine Au bump 42 formed on the semiconductor chip 41 can be inexpensively operated at high speed without inconvenience such as dishing.
  • the flattening makes it possible to easily and reliably connect the Au bumps 42 on the pair of semiconductor chips 41.
  • the Au bumps 42 can be connected to each other without requiring conditions such as high temperature and high pressure, and a highly reliable semiconductor device can be manufactured with high yield.
  • the step of controlling the TTV can be omitted, which contributes to a reduction in the number of steps.
  • FIG. 13A to 13C are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to Modification 2 in the order of steps.
  • a plurality of bumps having different heights are mounted without the back surface grinding of the first embodiment and the LSI elements and the like are mounted.
  • individual semiconductor chips 41 are cut out from the semiconductor substrate on which the Au bumps 42 are formed.
  • the surface layer of the semiconductor chip 41 is machined.
  • cutting is performed using a byte made of diamond or the like, and the surface of each Au bump 42 is continuously flat.
  • the flattening process is performed so that Thereby, the height of each Au bump 42 is made uniform, and the upper surface is flattened to a mirror surface.
  • the pair of the semiconductor chips 41 subjected to the flattening treatment is formed into a pair of semiconductor chips 41, and Au bumps 42 are formed on the surface of one of the semiconductor chips 41.
  • a resin layer 44 containing conductive fine particles 45 in an insulating resin is formed to a thickness completely embedded.
  • the pair of semiconductor chips 41 are opposed to each other, and the flattened upper surfaces of the Au bumps 42 are electrically connected to each other.
  • a pair of semiconductor chips 41 are arranged so that their upper surfaces face each other, and they are pressure-bonded at room temperature to 350 ° C., here about 170 ° C.
  • the Au bumps 42 facing each other by thermocompression bonding contact each other via the conductive fine particles 45 and are electrically connected. Since each of the upper surfaces is flattened with high precision, the pair of semiconductor chips 41 can be easily connected without requiring high temperature, high pressure, or the like as in the related art.
  • the resin of the resin layer 44 ensures the adhesion and electrical connection between the pair of semiconductor chips 41, and also contributes as an underfill for protecting the electrodes 42 and the like.
  • the surface of the fine Au bump 42 formed on the semiconductor chip 41 can be inexpensively operated at high speed without inconvenience such as dishing.
  • the flattening makes it possible to easily and reliably connect the Au bumps 42 on the pair of semiconductor chips 41. This makes it possible to connect the eight bumps 42 without requiring conditions such as high temperature and high pressure, and to manufacture highly reliable semiconductor devices with high yield.
  • the step of controlling the TTV can be omitted, which contributes to a reduction in the number of steps.
  • the present embodiment discloses the case where the stud bump is formed using the wire bonding method.
  • FIGS. 14A to 14F are schematic cross-sectional views showing the method for manufacturing the semiconductor device according to the present embodiment in the order of steps.
  • the back surface of a semiconductor substrate 51 on which an LSI semiconductor element and an electrode pad are formed in an element forming portion is ground, and a semiconductor is formed.
  • the thickness of the substrate 51 is kept constant, specifically, the TTV (difference between the maximum thickness and the minimum thickness of the substrate) is controlled to 1 or less.
  • a metal film for example, an A1 film is formed on the semiconductor substrate 51 by a sputtering method or the like, and this is patterned.
  • the electrode pad 52 may be formed at a portion that becomes an electrical connection portion. Then, as shown in Fig. 14C, a pole-shaped lump formed by melting the tip of a 20 / m diameter Au bonding wire, for example, by a wire bonding method using Au as the metal was used as an electrode. After crimping on the pad 52, the wire is torn off (precut) to form an Au projection 53 on the electrode pad 52. At this time, the height of each Au projection 53 from the electrode pad 52 is specified to be at least twice the diameter of the bonding wire, in this case about 60 m. In this case, the height of the Au projections 53 actually varies, and may be about 50 m to 60 / m. Subsequently, as shown in FIG.
  • cutting is performed using a byte 10 made of diamond or the like, and a flattening process is performed so that the upper surface of each Au projection 53 is continuously flat.
  • the bumps 54 are formed.
  • the cutting position is, for example, about 50 m from the electrode pad 52.
  • the cutting conditions are as follows: cutting speed 10 mZ s, Feed is set to about 20 m, and drive in 2 m each from the first cutting position.
  • FIG. 14E the upper surface of the Au projection 53 is flattened into a mirror-like shape, and the stud bump 54 is formed.
  • This flattening method by cutting requires less slurry than CMP, and the cost of the cutting tool is low because it can be worn and polished repeatedly, even if it is worn.
  • the semiconductor substrate chucked on the chuck table is rotated at high speed, and then the byte is moved at a predetermined speed to cut an arbitrary cutting amount at a time, so it can be completed in 1 to 2 minutes per semiconductor substrate This is a very high-throughput method.
  • the cutting conditions are set to the appropriate value. By setting the cutting conditions, the bump of the bump using an Au bonding wire can be prevented. A flat surface without breakage is possible. However, if the hardness is less than 30 HV, the projection may be inclined during cutting, so that the hardness of the wire is preferably 3 OHv or more.
  • the end point of the cutting process is a point in time when the diameter of the cut surface of all stud bumps becomes equal to or larger than the wire diameter.
  • the height of stud bumps varies greatly after precutting, and it is difficult to confirm that the diameter of the cut surface of all stud bumps is equal to or larger than the wire diameter.
  • a detection device including a laser oscillator 61 and a detector 62 is used, and an upper surface of the cut bump 54 is used.
  • a method is employed in which the laser beam is steered and the laser reflected from the upper surface is detected by the detector 62. Then, as shown in FIG. 15B, the processing is repeated until the detected laser intensity reaches a predetermined intensity at all the Au projections 53. It is desirable that this detector be installed behind the cutting tool in the traveling direction, and proceed in synchronization with the cutting tool. Since the upper surface (cut surface) of the stud bump 54 is almost mirror surface, the laser beam and the like are totally reflected.
  • each semiconductor chip 55 is cut out from the semiconductor substrate 51, and the semiconductor chip 55 and the circuit board 56 are connected by, for example, a flip chip method.
  • a stud pump 54 having a flattened upper surface of the semiconductor chip 55 and an electrode 57 formed on the surface of the circuit board 56 are brought into contact with each other, and pressurized and heated. Join them together.
  • the flattening 57 is flattened by the above-mentioned cutting process and then the flip chip is connected.
  • the surface of the fine stud bump 54 formed on the semiconductor substrate 51 can be inexpensively and quickly flattened without causing inconvenience such as dishing.
  • the connection of the stud bumps 54 can be easily and reliably performed. As a result, the bumps can be connected without requiring conditions such as high temperature and high pressure, and a highly reliable semiconductor device can be manufactured with high yield.
  • the height of the stud bumps 54 after cutting and flattening can be 1.5 times or more as compared with the case where the wire diameter is not specified, so that stress on the semiconductor element can be reduced. Device life can be extended. Furthermore, since the flat surface in cutting is equal to or larger than the wire diameter, it is possible to obtain a bonding strength twice or more even with the same wire diameter. If the same bonding strength as the conventional one is sufficient, the wire diameter can be reduced, so that the bump pitch can be reduced and the cost of the bonding wire can be reduced.
  • FIGS. 16 and 17 are schematic sectional views showing the method for manufacturing the semiconductor device according to the present embodiment.
  • the electrode 7 of the semiconductor substrate 1 on which an LSI semiconductor element or the like is formed A bump 3 having a uniform height, each Au projection 2 being cut, and an upper surface 3a being flattened on the upper surface 1 is formed on an underlying metal film 72.
  • an insulating protective film 73 is formed around the bumps 3 of the semiconductor substrate 1.
  • the probe is brought into contact with the upper surface of the bump 3 to inspect the electrical characteristics of the semiconductor element and the like of the semiconductor substrate 1.
  • an Au film 76 is formed by a copper foil 75 subjected to a surface treatment of Au, and a portion located at one end corresponds to a connection portion, and a resin layer 7 at the other end.
  • the semiconductor chip 21 is placed and fixed on the bonding stage 80, and the Au film 7 at the connection site of the TAB lead 74 is placed on the upper surface of the flattened and cleaned bump 3 of the semiconductor chip 21. 6 are brought into contact with each other and pressurized while being heated by a heater 78 to join them together.
  • the heating temperature may be a relatively low temperature of about 200 ° C., and the bonding load can be reduced to about 20 g, which is about 2/3 of the conventional value.
  • the semiconductor chip 21 is removed from the bonding stage 80, and the sealing resin 7 is covered so as to cover the surface of the semiconductor chip 21 including the connection portion between the bump 3 and the TAB lead 74. 9 is formed to complete the semiconductor device.
  • the metal bump may be formed by a wire bonding method.
  • the surface of the fine bump 3 formed on the semiconductor substrate 1 is flattened at low cost and at high speed without inconvenience such as dishing. Connection 3 can be easily and reliably performed. This eliminates the need for conditions such as high temperature and high pressure between bumps and lead terminals Reliable connection is possible, and highly reliable TAB bonding type semiconductor devices can be manufactured with high yield.
  • FIG. 18 is a schematic diagram illustrating the semiconductor manufacturing apparatus according to the present embodiment.
  • the semiconductor manufacturing apparatus includes a chip introducing section 81 for introducing a semiconductor chip having bumps formed on the surface thereof, and a circuit board introducing section 82 for introducing a circuit board having electrodes formed on the surface thereof.
  • a cutting section 83 for performing a step of flattening the bump surface of the semiconductor chip by cutting using the above-mentioned bytes, and a step of joining the semiconductor chip and the circuit board with the flattened bumps and electrodes.
  • an unloading unit 85 for unloading the bonded and integrated semiconductor device.
  • the cutting unit 83 and the bonding unit 84 are connected to an inert atmosphere. It is configured to have a cleaning holding section 86 encompassed by the above.
  • the cutting portion 83 not only the semiconductor chip but also the electrode surface of the circuit board may be similarly flattened by cutting.
  • Cleaning holder 8 6, the flattening step and the bonding step together cleaning atmosphere, in particular including an inert atmosphere, for example in the gas phase which does not contain oxygen, such as A r and N 2, or an oxygen 1 It has the function of keeping the atmosphere below atm. This makes it possible to maintain a flattened state, which is very close to the ideal, relatively easily, without adding a cleaning step using Ar plasma or the like immediately before the bonding step. Is possible.
  • the flip chip mounting is exemplified.
  • the present invention is not limited to this, and the bonding between the semiconductor chip and the semiconductor chip, the bonding between the semiconductor chips, and the like are not limited to this. It is also suitable for use in TJP2003 / 005092. Industrial applicability
  • the surface of fine bumps formed on a substrate is flattened at low cost and at high speed, and bumps are easily and reliably connected without causing inconvenience such as dicing. It becomes possible.

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Abstract

The rear (1b) of a semiconductor substrate (1) is fixed to the support face (11a) of a substrate support base (11) by vacuum clamping. The thickness of the semiconductor substrate (1) is uniform by planarizing the rear (1b), and the rear (1b) is forcedly free of waviness caused by the vacuum clamping to the support face (11a), so that the rear (1b) functions as the reference face of the planarization of the front (1a). In this state, Au projections (2) on the front (1a) and the surface layer of a resist mask (12) is cut with a single point tool (10) to planarize the surface of Au projections (2) and that of the resist mask (12) so as to be flat continuously. Thus, instead of CMP, the surface of a fine bump formed on a substrate is planarized at low cost low costly and speedily.

Description

明 細 書 バンプの形成方法、 半導体装置及びその製造方法、 並びに基板処理装置及び半 導体製造装置 技術分野  Technical Field Bump forming method, semiconductor device and manufacturing method thereof, substrate processing apparatus and semiconductor manufacturing apparatus
本発明は、 基板の表面に外部と電気的接続を行うための微細なバンプを形成す る方法、 半導体装置及びその製造方法、 並びに基板処理装置及び半導体製造装置 に関する。 背景技術  The present invention relates to a method for forming fine bumps for making electrical connection with the outside on a surface of a substrate, a semiconductor device and a method for manufacturing the same, a substrate processing apparatus, and a semiconductor manufacturing apparatus. Background art
従来、 半導体基板の表面で外部と電気的接続を行うため微細な金属端子には、 金 （Au) バンプ等が用いられている。 この A uバンプはメツキで形成されてお り、 表面の粗さが大きい。 このような金属端子を平坦化するためには、 化学機械 研磨 （Chemical Mechanical Polishing： CMP) 法が用いられている。 この方法 は、 被加工面となる金属及び樹脂を予め比較的平坦に形成し、 平坦な研磨パッド を押し当て、 スラリー （化学的研磨材） を用いて化学的 ·機械的に表面を精緻に 平坦加工するものである。予め設けられた硬い樹脂や金属面がストップ層となり、 CMPは完了する。 CMP法は、 半導体基板の厚みのばらつきや半導体基板の最 大厚みと最小厚みとの差で定義される T TV (Total Thickness Variation) には依 存しない方法である。 また、 従来の表面の粗さが大きい A uバンプ等の接合には、 その粗さが無くな るまで、 荷重、 熱、 あるいは超音波等によりバンプへ負荷を与える実装方法が必 要である。  Conventionally, gold (Au) bumps and the like have been used for fine metal terminals for making electrical connection to the outside on the surface of a semiconductor substrate. The Au bumps are formed by plating and have a large surface roughness. In order to flatten such metal terminals, a chemical mechanical polishing (CMP) method is used. In this method, the metal and resin to be processed are formed relatively flat in advance, a flat polishing pad is pressed, and the surface is finely chemically and mechanically flattened using a slurry (chemical polishing material). It is to be processed. The hard resin or metal surface provided in advance becomes a stop layer, and the CMP is completed. The CMP method does not depend on TTV (Total Thickness Variation), which is defined by the thickness variation of the semiconductor substrate and the difference between the maximum thickness and the minimum thickness of the semiconductor substrate. Conventional bonding of Au bumps with large surface roughness requires a mounting method that applies a load to the bumps with a load, heat, or ultrasonic waves until the roughness is eliminated.
CMP以外でも、 例えば切削工具を用いた平坦化方法がいくつか案出されてい る （例えば、 特開平 7 - 3 2 6 6 1 4号公報、 特開平 8 - 1 1 04 9号公報、 特 開平 9— 8 2 6 1 6号公報、特開 2 0 0 0— 1 7 3 9 54号公報参照）。 しかしな がら、 いずれも L S I上における部分領域の S O G膜の平坦化を対象としたもの であり、 C M Pと同様、 被切削面を基準として切削する方法であって半導体基板 の T T Vには依存しない。 また、 バンプを切削して表面を露出させる方法 （特開 平 1 0— 3 4 5 2 0 1号公報参照） もあるが、 これは L S I上に形成されたバン プ部分の平坦化を対象としており、被切削面を基準として切削する方法であって、 半導体基板の T T Vには依存しない。 上述のように、 微細な接続には A uバンプが用いられているが、 バンプ表面の 粗さが大きいことで、 それらのバンプ同士を接合するのは困難である。 また、 A uなどの金属と樹脂を同時に C M Pを用いて平坦化する場合、 金属と樹脂の研磨 速度の違いに起因してディッシングと呼ばれる窪みが現れる。 このディッシング により、 確実なバンプ接合を得るために、 荷重、 熱、 あるいは超音波等の大きな 負荷をバンプに与えることを要する。 本発明は、 上記の課題に鑑みてなされたものであり、 C M Pに替わり、 基板上 に形成された微細なバンプの表面を安価に高速で平坦化し、バンプ同士の接続を、 ディッシング等の不都合を発生させることなく容易且つ確実に行うことを可能と するバンプの形成方法及び高信頼性の半導体装置、 その製造方法並びに半導体製 造装置を提供することを目的とする。 発明の開示 Other than CMP, for example, several flattening methods using a cutting tool have been devised (for example, Japanese Patent Application Laid-Open Nos. Hei 7-32614, Hei 8-11049, and Tokuhei Heihei). No. 9-82626, Japanese Patent Application Laid-Open No. 2000-174954). But However, all of them are directed to flattening the SOG film in a partial region on the LSI, and, like CMP, are based on the surface to be cut and do not depend on the TTV of the semiconductor substrate. There is also a method in which the surface is exposed by cutting the bump (see Japanese Patent Application Laid-Open No. H10-345201). This method is intended for flattening the bump formed on the LSI. This method is based on the surface to be cut, and does not depend on the TTV of the semiconductor substrate. As described above, Au bumps are used for fine connections, but the bump surfaces are so rough that it is difficult to join them. When a metal such as Au and a resin are simultaneously planarized using CMP, a depression called dishing appears due to a difference in polishing rate between the metal and the resin. Due to this dishing, it is necessary to apply a large load such as a load, heat, or ultrasonic wave to the bump in order to obtain a reliable bump bonding. The present invention has been made in view of the above-mentioned problems, and has been proposed in place of CMP to flatten the surface of fine bumps formed on a substrate at low cost and at high speed, and to reduce inconveniences such as dishing between bumps. An object of the present invention is to provide a bump forming method, a highly reliable semiconductor device, a method of manufacturing the same, and a semiconductor manufacturing device that can be easily and reliably performed without causing the generation. Disclosure of the invention
本発明のバンプの形成方法は、 基板の表面に外部と電気的接続を行うためのバ ンプを形成する方法であって、 前記基板の表面に、 複数の前記バンプ及び前記パ ンプ間に絶縁膜を形成する工程と、 バイ トを用いた切削加工により、 前記各バン プの表面及び前記絶縁膜の表面が連続して平坦となるように平坦化処理する工程 と、 前記絶縁膜を除去する工程とを含む。 本発明の半導体装置は、 それぞれ、 外部と電気的接続を行うための複数のバン プが表面に形成されてなる一対の半導体基板を有しており、 前記各バンプの表面 が前記各半導体基板上で連続して均一に平坦化されており、前記各半導体基板は、 前記各バンプの平坦化された前記表面同士を対向させて接続し、 一体化してなる ものである。 本発明の半導体装置の製造方法は、 一対の半導体基板の各表面に、 絶縁膜内に 埋め込まれるように各バンプを形成する工程と、バイ トを用いた切削加工により、 前記各バンプの表面及び前記絶縁膜の表面が連続して平坦となるように平坦化処 理する工程と、 前記絶縁膜を除去する工程と、 前記各半導体基板を、 前記各バン プの平坦化された前記表面同士を対向させて接続し、 一体化する工程とを含む。 本発明のバンプの形成方法は、 基板の表面に外部と電気的接続を行うためのバ ンプを形成する方法であって、 前記基板の表面に、 複数の前記バンプを形成する 工程と、 バイ トを用いた切削加工により、 前記複数のバンプの表面が連続して平 坦となるように平坦化処理する工程とを含む。 本発明の半導体装置の製造方法は、 一対の半導体チップの各表面に、 それぞれ 複数の前記バンプを形成する工程と、 バイ トを用いた切削加工により、 前記複数 のバンプの表面が連続して平坦となるように平坦化処理する工程と、 前記複数の バンプの表面が平坦化された前記一対の半導体チップを、 前記各バンプ同士が対 向するように接続して一体化する工程とを含む。 本発明の半導体装置は、 それぞれ、 外部と電気的接続を行うための複数のバン プが表面に形成されてなる一対の半導体チップを有しており、 前記各バンプの表 面が前記各半導体チップ上で連続して均一に平坦化されており、 前記各半導体チ ップは、 前記各バンプの平坦化された前記表面同士を対向させて接続し、 一体化 してなるものである。 本発明のバンプの形成方法は、 半導体基板の表面に外部と電気的接続を行うた めのバンプであり、 ワイヤボンディング法を用いたスタツ ドバンプを形成する方 法であって、 前記半導体基板の表面の電気的接続箇所にボンディングワイヤを用 いて複数の突起部を形成する工程と、 バイ トを用いた切削加工により、 前記複数 の突起部の上面が連続して平坦となるように平坦化処理し、 前記スタツドバンプ を形成する工程とを含む。 本発明の半導体装置は、 外部と電気的接続を行うためのバンプであり、 ワイヤ ボンディング法を用いた複数のスタツ ドバンプが表面に形成されてなる半導体チ ップを有しており、 前記各スタツドバンプの上面が前記半導体チップ上で連続し て均一に平坦化されてなるものである。 ' 本発明の半導体装置の製造方法は、 半導体基板の表面に複数のバンプを形成す る工程と、 バイ トを用いた切削加工により、 前記複数のバンプの表面が連続して 平坦となるように平 a化処理する工程と、 前記複数のバンプの表面が平坦化され た前記半導体基板から、 各半導体チップを切り出す工程と、 前記半導体チップの 前記バンプとリ一ド端子の一端部とを接続する工程とを含む。 本発明の半導体装置の製造方法は、 半導体基板の表面の電気的接続箇所にワイ ャボンディング法を用いた複数の突起部を形成する工程と、 バイ トを用いた切削 加工により、前記複数の突起部の上面が連続して平坦となるように平坦化処理し、 スタツドバンプを形成する工程と、 複数のスタツ ドバンプの形成された前記半導 体基板から、 各半導体チップを切り出す工程と、 前記半導体チップの前記スタツ ドバンプとリード端子の一端部とを接続する工程とを含む。 本発明の半導体装置は、 外部と電気的接続を行うための複数のバンプが表面に 形成されてなる半導体チップを有しており、 前記各バンプの表面が前記半導体チ ップ上で連続して均一に平坦化されており、 前記半導体チップの前記バンプとリ ―ド端子の一端部とが接続され、 一体化してなるものである。 本発明の半導体装置は、 外部と電気的接続を行うための複数のバンプであり、 ワイヤボンディング法を用いた複数のスタッドバンプが表面に形成されてなる半 導体チップを有しており、 前記各ス夕ッドバンプの表面が前記半導体チップ上で 連続して均一に'平坦化されており、 前記半導体チップの前記スタッドバンプとリ 一ド端子の一端部とが接続され、 一体化してなるものである。 本発明の半導体装置の製造方法は、 表面に複数の電極が形成された半導体チッ プを不活性雰囲気内に導入し、 バイ トを用いた切削加工により、 前記複数の電極 の表面が連続して平坦となるように平坦化処理する工程と、 平坦化された前記複 数の電極の表面が前記不活性雰囲気内で清浄に保たれた状態で、 前記半導体チッ プの前記複数の電極と回路基板とを接続し、 一体化する工程とを含む。 本発明の半導体製造装置は、 バイ トを有する切削加工手段と、 導入された一対 の基体を接合させる接合手段と、 前記切削加工手段及び前記接合手段の環境を不 活性雰囲気の状態に保つ不活性雰囲気手段とを含み、 前記切削加工手段は、 前記 不活性雰囲気内において、 表面に複数の電極が形成された前記一対の基体の少な くとも一方に対して、 前記バイ トを用いた切削加工により、 前記複数の電極の表 面が連続して平坦となるように平坦化処理する機能を有し、 前記接合手段は、 平 坦化された前記複数の電極の表面が前記不活性雰囲気内で清浄に保たれた状態で, 前記一対の基体を前記複数の電極で接続し、 一体化する機能を有する。 本発明の基板処理装置は、 基板の表面に外部と電気的接続を行うためのバンプ を形成する際の基板処理装置であって、 平坦な支持面を有しており、 基板をその 一面で前記支持面に吸着させ、 前記一面を強制的に平坦な基準面として支持固定 する基板支持台と、 前記基板の他面を切削加工するバイ トとを含み、 表面に複数 の前記バンプ及び前記バンプ間に絶縁膜が形成されてなる基板を前記基板支持台 に支持固定し、 前記バイ 卜を用いた切削加工により、 前記各バンプの表面及び前 記絶縁膜の表面が連続して平坦となるように平坦化処理する。 図面の簡単な説明 図 1 A〜図 I Dは、 第 1の実施形態によるバンプの形成方法を工程順に示す概 略断面図である。 The method of forming a bump according to the present invention is a method of forming a bump for making an electrical connection with the outside on a surface of a substrate, the method comprising: forming an insulating film between the plurality of bumps and the pump on the surface of the substrate. A step of forming, a step of performing a flattening process by cutting using a byte so that the surface of each of the bumps and the surface of the insulating film are continuously flattened, and a step of removing the insulating film And The semiconductor device of the present invention includes a pair of semiconductor substrates each having a plurality of bumps formed on a surface thereof for making an electrical connection with the outside. Are continuously and uniformly flattened on the respective semiconductor substrates, and the respective semiconductor substrates are formed by connecting the flattened surfaces of the respective bumps so as to face each other and integrating them. A method of manufacturing a semiconductor device according to the present invention includes the steps of: forming a bump on each surface of a pair of semiconductor substrates so as to be embedded in an insulating film; A step of performing a planarization process so that the surface of the insulating film is continuously flat; a step of removing the insulating film; and a step of removing the semiconductor substrates from each other by flattening the surfaces of the bumps. And connecting and integrating them. A method for forming a bump according to the present invention is a method for forming a bump for making an electrical connection to the outside on a surface of a substrate, comprising: forming a plurality of bumps on the surface of the substrate; And a step of performing a flattening process so that the surfaces of the plurality of bumps are continuously flattened by a cutting process. In the method for manufacturing a semiconductor device according to the present invention, a step of forming a plurality of the bumps on each surface of the pair of semiconductor chips, and a cutting process using a byte, the surfaces of the plurality of bumps are continuously flattened. And a step of connecting and unifying the pair of semiconductor chips having the surfaces of the plurality of bumps planarized so that the bumps face each other. The semiconductor device of the present invention includes a pair of semiconductor chips each having a plurality of bumps formed on a surface for electrical connection with the outside, and a surface of each of the bumps is formed on each of the semiconductor chips. The semiconductor chips are continuously and uniformly flattened on the upper surface, and the semiconductor chips are formed by connecting the flattened surfaces of the bumps so as to face each other and integrated. The bump forming method of the present invention is a bump for making an electrical connection to the outside on the surface of a semiconductor substrate, and a method for forming a stud bump using a wire bonding method. Forming a plurality of protrusions using a bonding wire at an electrical connection point on the surface of the semiconductor substrate; and cutting using a byte, the upper surfaces of the plurality of protrusions are continuously formed. And forming the stud bumps. The semiconductor device of the present invention is a bump for making an electrical connection with the outside, and has a semiconductor chip having a plurality of stud bumps formed on the surface using a wire bonding method. The upper surfaces of the bumps are continuously and uniformly flattened on the semiconductor chip. '' The method of manufacturing a semiconductor device according to the present invention includes a step of forming a plurality of bumps on a surface of a semiconductor substrate and a cutting process using a byte so that the surfaces of the plurality of bumps are continuously flat. A step of performing a planarization process, a step of cutting out each semiconductor chip from the semiconductor substrate having the surfaces of the plurality of bumps planarized, and connecting the bump of the semiconductor chip and one end of a lead terminal. And a step. The method of manufacturing a semiconductor device according to the present invention includes a step of forming a plurality of protrusions using an electric wire at a connection point on a surface of a semiconductor substrate; and a step of cutting the plurality of protrusions using a byte. Forming a stud bump so that the upper surface of the semiconductor chip is continuously flat, forming each semiconductor chip from the semiconductor substrate having a plurality of stud bumps formed thereon, Connecting the stud bump to one end of the lead terminal. The semiconductor device of the present invention has a semiconductor chip having a plurality of bumps formed on a surface for electrical connection with the outside, and the surface of each bump is continuously formed on the semiconductor chip. The bumps of the semiconductor chip and one ends of the lead terminals are connected and integrated, and are uniformly flattened. The semiconductor device of the present invention includes a plurality of bumps for making an electrical connection with the outside, A semiconductor chip having a plurality of stud bumps formed on a surface thereof using a wire bonding method, and a surface of each of the stud bumps is continuously and uniformly planarized on the semiconductor chip; The stud bump of the semiconductor chip and one end of a lead terminal are connected and integrated. In the method for manufacturing a semiconductor device according to the present invention, the surface of the plurality of electrodes is continuously formed by introducing a semiconductor chip having a plurality of electrodes formed on its surface into an inert atmosphere, and performing cutting using a byte. A step of performing a flattening process so as to be flat, and the plurality of electrodes of the semiconductor chip and the circuit board in a state where the surfaces of the flattened electrodes are kept clean in the inert atmosphere. And integrating them with each other. A semiconductor manufacturing apparatus according to the present invention includes a cutting means having a byte, a joining means for joining a pair of introduced substrates, and an inert gas for maintaining an environment of the cutting means and the joining means in an inert atmosphere. Atmosphere means, wherein the cutting means performs cutting using at least one of the pair of substrates having a plurality of electrodes formed on a surface thereof in the inert atmosphere using the byte. And a function of performing a flattening process so that the surfaces of the plurality of electrodes are continuously flat. The bonding unit cleans the flattened surfaces of the plurality of electrodes in the inert atmosphere. In this state, the pair of bases have a function of being connected and integrated by the plurality of electrodes. The substrate processing apparatus of the present invention is a substrate processing apparatus for forming a bump for making an electrical connection with the outside on a surface of a substrate, the substrate processing apparatus having a flat support surface, and A substrate support base for adsorbing to the support surface and forcibly supporting and fixing the one surface as a flat reference surface; and a byte for cutting the other surface of the substrate, and a plurality of bumps on the surface and between the bumps A substrate on which an insulating film is formed is supported and fixed to the substrate support table, and cutting using the bytes is performed so that the surfaces of the bumps and the surface of the insulating film are continuously flat. A flattening process is performed. BRIEF DESCRIPTION OF THE FIGURES 1A to 1D are schematic cross-sectional views showing a method of forming a bump according to the first embodiment in the order of steps.
図 2 A， 図 2 Bは、 第 1の実施形態によるバンプの形成方法を工程順に示す概 略断面図である。  2A and 2B are schematic cross-sectional views illustrating a method of forming a bump according to the first embodiment in the order of steps.
図 3 A， 図 3 Bは、 切削加工による平坦化の結果を示す図である。  3A and 3B show the results of flattening by cutting.
図 4A, 図 4 Bは、 切削加工による平坦化の具体例を示す概略断面図である。 図 5は、 切削加工による平坦化の具体例を示す概略断面図である。  4A and 4B are schematic cross-sectional views showing specific examples of flattening by cutting. FIG. 5 is a schematic cross-sectional view showing a specific example of flattening by cutting.
図 6は、 切削加工装置の構成を表したブロック図である。  FIG. 6 is a block diagram showing a configuration of the cutting apparatus.
図 7は、 切削加工装置の概略構成図である。  FIG. 7 is a schematic configuration diagram of a cutting device.
図 8は、 切削加工工程のフロー図である。  FIG. 8 is a flowchart of the cutting process.
図 9 A〜図 9 Cは、 第 2の実施形態による半導体装置の製造方法を工程順に示 す概略平面図である。  9A to 9C are schematic plan views illustrating a method for manufacturing a semiconductor device according to the second embodiment in the order of steps.
図 1 0 A〜図 1 0 Fは、 第 2の実施形態によるバンプの形成方法を工程順に示 す概略断面図である。  10A to 10F are schematic cross-sectional views illustrating a method of forming a bump according to the second embodiment in the order of steps.
図 1 1 A， 図 1 1 Bは、 第 3の実施形態による半導体装置の製造方法を工程順 に示す概略断面図である。  11A and 11B are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to the third embodiment in the order of steps.
図 1 2 A〜図 1 2 Cは、 第 3の実施形態の変形例 1による半導体装置の製造方 法を工程順に示す概略断面図である。  12A to 12C are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to Modification 1 of the third embodiment in the order of steps.
図 1 3 A〜図 1 3 Cは、 第 3の実施形態の変形例 2による半導体装置の製造方 法を工程順に示す概略断面図である。  13A to 13C are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to Modification 2 of the third embodiment in the order of steps.
図 1 4 A〜図 1 4 Fは、 第 4の実施形態による半導体装置の製造方法を工程順 に示す概略断面図である。  14A to 14F are schematic sectional views showing the method for manufacturing the semiconductor device according to the fourth embodiment in the order of steps.
図 1 5 A〜図 1 5 Dは、第 4の実施形態による切削終点検出方法を示す図であ る。  FIGS. 15A to 15D are diagrams showing a cutting end point detection method according to the fourth embodiment.
図 1 6は、 第 5の実施形態半導体装置の製造方法を示す概略断面図である。 図 1 7は、 第 5の実施形態半導体装置の製造方法を示す概略断面図である。 図 1 8は、 第 6の実施形態による半導体製造装置を示す模式図である。 発明を実施するための最良の形態 一本発明の基本骨子一 FIG. 16 is a schematic sectional view illustrating the method for manufacturing the semiconductor device according to the fifth embodiment. FIG. 17 is a schematic sectional view illustrating the method for manufacturing the semiconductor device according to the fifth embodiment. FIG. 18 is a schematic diagram showing a semiconductor manufacturing apparatus according to the sixth embodiment. BEST MODE FOR CARRYING OUT THE INVENTION One basic principle of the present invention
初めに、 本発明の基本骨子について説明する。  First, the basic gist of the present invention will be described.
本発明者は、 C M P法に替わり、 基板上に形成された多数の微細バンプの表面 を安価に高速で一斉に平坦化する手法として、 バイ トを用いた切削加工を適用す ることに想到した。 この切削加工によれば、 半導体基板上で絶縁膜内にバンプが 埋め込み形成されているような場合でも、 C M P法のように金属と絶縁物の研磨 速度等に依存することなく、 基板上で一斉に金属と絶縁物を連続して切削し、 デ ィッシング等を発生せしめることなく全体的に両者を均一に平坦化することがで きる。 銅、 アルミニウム、 ニッケル等の金属やポリイミ ド等の絶縁材料は、 容易 にバイ トで切削可能な材料である。 本発明では、 バンプの金属材料及び絶縁材料 としては、 前者が延性金属であり、 後者が例えば 2 0 0 G P a以上の剛性率を有 する樹脂等であれば、 好適である。 この場合、 上述の切削加工をバンプ表面の平坦化に利用するためには、 切削を 基板の背面 （裏面） 基準で行うことが好適である。 一般的に、 シリコン基板の T T Vは、 1 m ~ 5 mの範囲内にあり、 L S Iのプロセスでは 5 m程度の T T Vはフォトリソグラフィ一に影響を与えることはなく、 通常では考慮の対象外 となる。 しかしながら、 切削加工の場合では T T Vの値に大きく影響される。 切 削による平坦精度は T T Vの値以下にはならない。 従って、 切削加工を半導体基 板の平坦化に用いる場合には、 基板の T T Vを目標の切削精度以下に制御するこ とが先ず必要になる。 本発明者は、 上記の事情を勘案し、 上述の切削加工をバンプ表面の平坦化に利 用するに際して、 当該平坦化を確実に行う具体的手法として、 基板表面を基準に その裏面を研削し、 半導体基板の T T Vを目的とする切削精度以下に小さく抑え ることに想到した。 この場合、 T T Vを小さくして且つ個々の半導体基板の厚み ばらつきも切削精度以下に抑えることが理想的である。 しかしながら、 T T Vさ え小さくできれば、個々の半導体基板の厚みについては切削時に検出可能である。 切削量は、 この個々の半導体基板の厚みを検出することにより制御可能である。 バンプとしては、 メツキ法により形成されるものの他、 ワイヤボンディング 法、即ちボンディ ングワイヤの先端を溶融して形成したポール状の塊を電極パ ッ ド上に圧着し、当該ワイヤを引きちぎることにより形成されたバンプ（以下、 スタッ ドバンプと称する。） がある。 スタツ ドバンプを形成する場合、 ボンディ ングワイヤの引きちぎりにより、 ピン状の突起が形成されるため、 かかる突起を平坦化する必要がある。 本発明 では、 上述の切削加工による平坦化法をスタッ ドバンプにも適用する。 この場 合、 ワイヤの引きちぎり （プレカッ ト） 時には各突起部の高さが異なり、 最も 低いバンプに揃えて平坦化することになるが、スタツ ドバンプの高さは高いほ どデバイスへの応力を緩和し、 デバイス寿命を延ばすことが可能であるため、 各突起部の高さを規定することが必要である。 本発明では、 プレカツ 卜時の突 起部の電極パッ ドからの高さをワイヤ径の 2倍以上に規定し、切削加工の終点 として、 全てのスタッ ドバンプについて、 切削面の径がワイヤ径と同等以上に なった時点とする。 これにより、 切削平坦化後におけるスタッ ドバンプの高さ を、 ワイヤ径を規定しない場合に比べて 1 . 5倍以上とすることができ、 半導 体素子への応力を緩和することが可能となり、 デバイス寿命を延ばすことが可能 となる。 そして、 上述のように T T Vを制御し、 切削加工により微細なバンプの表面を 平坦化した後、 半導体基板 （ゥェ一 Λ ) から半導体部品となる個々の半導体チッ プを切り出す。しかる後、平坦化された表面を有する半導体基板と半導体チップ、 又は半導体チップ同士を、 バンプを対向させて電気的に接続して接合する。 この とき、 対向するバンプの上面が共に高精度に平坦化されているため、 従来のよう に高温 · 高圧等を要することなく容易に接合される。 ここで、 本発明者は更に、 対向するバンプ同士の接合を確実に実現するための 具体的条件 ·状態を模索した。 上述の接合時にもバンプを切削加工直後の平坦化 状態に保つことが理想的である；とに鑑み、 切削加工直後の平坦化状態を可及的 に保持するため、 平坦化工 §と接合工程を共に清浄化雰囲気、 具体的には不活性 雰囲 L気内で行うことに想到した。 この点、 接合工程の直前に A rプラズマ等を用 いた清浄化工程を付加することで対処することもできるが、 工程数の増加を招く という欠点がある。 本発明では、 工程数の増加を招くことなく比較的容易に理想 に極めて近い平坦化状態を維持することができ、 バンプの確実な接合が可能とな る。 本発明者は、 本発明の他の態様として、 この半導体チップの状態に着目する。 即ち、 ゥェ一ハレベルでは、 上述のように当該半導体基板の T T Vが問題となる が、 半導体チップなどの個片化されたものについては、 そのサイズが小さいため にチップエリア内における T T Vは、 切削時には殆ど無視できる程度の影響しか 受けない。 そこで本発明者は、 先ず半導体基板から各半導体チップを切り出した後、 この 半導体チップの状態で上述のバンプを用いた切削加工により微細なバンプの表面 を平坦化することに想到した。 そして、 半導体チップ同士を、 バンプを対向させ て電気的に接続して接合する。 これにより、 T T Vを制御する工程を省略できる とともに、 容易にバンプ接合を行うことが可能となる。 また本発明では、 上述した切削加工技術を、 いわゆる T A Bボンディング法に よる半導体装置にも適用する。 The inventor of the present invention has conceived of applying cutting using a byte as a technique for simultaneously and simultaneously flattening the surface of a large number of fine bumps formed on a substrate at low cost and at high speed, instead of the CMP method. . According to this cutting process, even when a bump is buried in an insulating film on a semiconductor substrate, the bumps are simultaneously formed on the substrate without depending on the polishing rate of a metal and an insulator as in the CMP method. In this way, the metal and the insulator can be continuously cut, and both can be uniformly flattened without causing dishing or the like. Metals such as copper, aluminum and nickel and insulating materials such as polyimide are materials that can be easily cut with a byte. In the present invention, as the metal material and the insulating material of the bump, it is preferable that the former is a ductile metal and the latter is a resin having a rigidity of, for example, 200 GPa or more. In this case, in order to use the above-mentioned cutting for flattening the bump surface, it is preferable to perform cutting with reference to the back surface (back surface) of the substrate. Generally, the TTV of a silicon substrate is in the range of 1 m to 5 m, and in the LSI process, a TTV of about 5 m does not affect photolithography and is usually not considered. . However, in the case of cutting, it is greatly affected by the value of TTV. The flatness accuracy by cutting does not fall below the value of TTV. Therefore, when cutting is used for flattening a semiconductor substrate, it is first necessary to control the TTV of the substrate to a target cutting accuracy or less. In view of the above circumstances, the present inventor, when using the above-mentioned cutting for flattening the bump surface, as a specific method for ensuring the flattening, grinds the back surface with reference to the substrate surface. However, we came up with the idea of keeping the TTV of semiconductor substrates at a level lower than the target cutting accuracy. In this case, ideally, the TTV should be reduced and the thickness variation of individual semiconductor substrates should be kept below the cutting accuracy. However, if the TTV can be made even smaller, the thickness of individual semiconductor substrates can be detected during cutting. The amount of cutting can be controlled by detecting the thickness of each individual semiconductor substrate. In addition to the bumps formed by the plating method, the bumps are formed by wire bonding, that is, by bonding a pole-shaped mass formed by melting the tip of the bonding wire onto the electrode pad and tearing the wire. Bumps (hereinafter referred to as stud bumps). When forming a stud bump, a pin-shaped protrusion is formed due to tearing of the bonding wire, and therefore, it is necessary to flatten such protrusions. In the present invention, the above-mentioned flattening method by cutting is also applied to stud bumps. In this case, when the wire is torn (pre-cut), the height of each protrusion is different, and the wire is flattened in alignment with the lowest bump. However, the higher the height of the stud bump, the more stress on the device It is necessary to specify the height of each protrusion because it can be relaxed and the device life can be extended. In the present invention, the height of the protruding portion from the electrode pad at the time of precut is specified to be at least twice the wire diameter, and the diameter of the cut surface is the same as the wire diameter for all stud bumps as the end point of the cutting process. It will be the time when it becomes equal or higher. As a result, the height of the stud bump after cutting and flattening can be made 1.5 times or more as compared with the case where the wire diameter is not specified, and the stress on the semiconductor element can be alleviated. Device life can be extended. After controlling the TTV as described above and flattening the surfaces of the fine bumps by cutting, individual semiconductor chips to be semiconductor components are cut out from the semiconductor substrate (ゥ ゥ). Thereafter, the semiconductor substrate having the flattened surface and the semiconductor chip or the semiconductor chips are electrically connected to each other with the bumps facing each other and joined. At this time, since the upper surfaces of the opposing bumps are both flattened with high precision, they can be easily joined without requiring a high temperature and a high pressure as in the conventional case. Here, the present inventor further searched for specific conditions and conditions for reliably realizing the joining of the opposing bumps. Flattening of bumps immediately after cutting even during the above-mentioned bonding In view of this, ideally, in order to maintain the flattened state immediately after cutting as much as possible, both the flattening process and the bonding process should be performed in a cleaning atmosphere, specifically, an inert atmosphere. L thought to do it inside. This can be dealt with by adding a cleaning step using Ar plasma or the like immediately before the bonding step, but has the disadvantage of increasing the number of steps. According to the present invention, it is possible to relatively easily maintain a flattened state that is very close to an ideal state without increasing the number of steps, and it is possible to reliably connect bumps. The inventor focuses on the state of the semiconductor chip as another aspect of the present invention. In other words, at the wafer level, the TTV of the semiconductor substrate becomes a problem as described above. However, as for individual pieces such as semiconductor chips, the TTV in the chip area is cut due to its small size. Sometimes it is almost negligible. The inventor of the present invention has conceived of first cutting each semiconductor chip from the semiconductor substrate and then flattening the surface of the fine bumps by cutting using the above-mentioned bumps in the state of the semiconductor chip. Then, the semiconductor chips are electrically connected and joined with the bumps facing each other. As a result, the step of controlling the TTV can be omitted, and the bump bonding can be easily performed. Further, in the present invention, the above-mentioned cutting technology is applied to a semiconductor device by a so-called TAB bonding method.
通常、 T A B接続は、 メツキバンプ法による場合では、 金メッキバンプに直 接に金の表面処理を施された短冊状の銅箔リードを位置合わせして 3 0 0 °C以上 に加熱し、 1つのバンプ当たり 3 0 g以上の加圧圧着を必要とする。 他方、 スタ ッ ドバンプ法にいる場合では、予めスタツ ドバンプの形成された半導体チップを、 ガラス板又は金属板に押し当て加熱し、 スタツドバンプ先端を平坦に加工して用 いることが必要である。 メツキ終端面には、 凹凸や表面に特有の金属的及び有機的汚染がある。 また、 チップ内でのメツキ高さのばらつきも数ミクロンのレベルで発生している。 これ らのメツキ終端面に T A Bボンディングする場合、 高温と高荷重が必要になる。 ボンディング時に高温になると微細なピッチのリードの接続では、 銅とシリコン の熱膨張率の差が大きくなるため位置ずれが発生し易い。 他方、 スタッドバンプ においては、 高さにバラツキが大きく、 形状も一定でないことから更に高温及び 高荷重が必要であり、 同様に微細ピッチの接続は難しい。 Normally, in the case of the TAB connection, when the plating bump method is used, a strip-shaped copper foil lead that has been subjected to a gold surface treatment is directly aligned with the gold-plated bump, and heated to 300 ° C or more, and one bump is formed. It requires 30 g or more of pressure bonding. On the other hand, in the case of using the stud bump method, it is necessary to press the semiconductor chip on which the stud bump is formed in advance against a glass plate or a metal plate and heat it so as to flatten the tip of the stud bump. The end surface of the plating has metallic and organic contaminants peculiar to irregularities and surfaces. In addition, variations in die height within the chip occur at the level of several microns. TAB bonding to these terminations requires high temperatures and high loads. At high temperatures during bonding, fine pitch lead connections tend to be misaligned due to the large difference in thermal expansion between copper and silicon. On the other hand, stud bumps require a higher temperature and a higher load because the height varies widely and the shape is not constant, and it is also difficult to connect fine pitches.
T A Bボンディング時の位置ずれを小さくするためには、 温度を下げるととも に、 銅のリード端子が同時にバンプに接触することが必要である。 本発明では、 バイ トによる切削技術を用いメツキバンプ及びスタツドバンプの表面を切削加工 により平坦化して清浄化を図り、 これにより T A Bボンディング時の温度及び荷 重を低減させ、 微細ピッチのリ一ドを位置ずれなく接続することが可能となる。 一本発明の具体的な実施形態一 To reduce the misalignment during TAB bonding, it is necessary to lower the temperature and make the copper lead terminals simultaneously contact the bumps. In the present invention, the surfaces of the metal bumps and the stud bumps are flattened by cutting using a byte cutting technique to purify the surface, thereby reducing the temperature and the load at the time of TAB bonding and leading to a fine pitch lead. Connection can be performed without displacement. One specific embodiment of the present invention
以下、 上述した基本骨子を踏まえ、 本発明の具体的な諸実施形態について図面 を用いて詳細に説明する。  Hereinafter, specific embodiments of the present invention will be described in detail with reference to the drawings, based on the basic gist described above.
[第 1の実施形態] [First Embodiment]
ここでは、 基板としてシリコン半導体基板を例示し、 この半導体基板上に外部 と電気的接続を行うために設けられてなるバンプを形成する方法及びこの方法を 用いた半導体装置及びその製造方法について開示する。  Here, a silicon semiconductor substrate is exemplified as a substrate, and a method of forming a bump provided for making electrical connection with the outside on the semiconductor substrate, a semiconductor device using this method, and a method of manufacturing the same are disclosed. .
(バンプの形成方法） (Bump formation method)
図 1 A〜図 1 D， 図 2 A， 図 2 Bは、 本実施形態によるバンプの形成方法をェ 程順【こ示す概略断面図である。 先ず、 シリコン半導体基板 1を用意し、 基板表面 1 aの素子形成部位に所望の 1A to 1D, 2A, and 2B are schematic cross-sectional views showing a method of forming a bump according to the present embodiment in order. First, a silicon semiconductor substrate 1 is prepared.
L S I半導体素子 （不図示） を形成する。 このように、 素子形成部位に L S I半 導体素子等の形成された半導体基板 1について、 以下で各工程を説明する。 図 1 Aに示すように、 通常、 シリコン半導体基板は、 図示の如く厚みが一様で はなく、 しかもうねりを伴う状態にある。 そこで、 半導体基板 1の表面 1 aに後 述するバイ トを用いた切削加工を施すための前工程として、 その裏面 1 bを平坦 化する。 具体的には、 支持面が平坦とされた基板支持台 （不図示） を用意し、 この支持 面に吸着、 例えば真空吸着により表面 1 aを吸着させて半導体基板 1を基板支持 台に固定する。 このとき、 表面 1 aは支持面への吸着により強制的に平坦とされ ており、 これにより表面 1 aが裏面 1 bの平坦化の基準面となる。 この状態で、 裏面 l bを機械加工、 ここでは機械研削し、 裏面 1 bの凸部 1 cを研削除去して 平坦化処理する。 この場合、 裏面 1 bの切削量を表面 1 aからの距離により制御 することが好ましい。 これにより、 図 1 Bに示すように、 半導体基板 1の厚みが 一定、 具体的には T T V (基板の最大厚みと最小厚みとの差） が所定値以下とな るように、 具体的には T T Vが 1 /i m以下に制御されることになる。 続いて、 図 1 Cに示すように、 半導体基板 1を基板支持台から外し、 半導体基 板 1の表面 1 a上に感光性樹脂、 例えばフォトレジストを塗布し、 このフォ トレ ジス卜をフォトリソグラフィ一により加工して、 所定のバンプパターン 1 2 aを 有するレジストマスク 1 2を形成する。 続いて、 レジストマスク 1 2をマスクとして用い、 例えば蒸着法により金属、 例えば銅膜を形成し、 メツキ電極（不図示） を形成した後、 図 1 Dに示すように、 メッキ電極をシ一ドとしてメツキ法によりレジストマスク 1 2の各バンプパター ン 1 2 aを埋め込むように金 （A u ) を堆積させ、 A u突起 2を形成する。なお、 A u以外にも C u， A g , N i , S n又はこれらの合金等を用いて突起を形成し ても良い。 続いて、' 半導体基板 1の表面 1 aにバイ トを用いた切削加工を施し、 平坦化す る。 An LSI semiconductor device (not shown) is formed. In this way, the LSI half The respective steps of the semiconductor substrate 1 on which the conductor elements and the like are formed will be described below. As shown in FIG. 1A, the silicon semiconductor substrate is usually not uniform in thickness as shown in FIG. Therefore, the back surface 1b of the semiconductor substrate 1 is flattened as a pre-process for performing a cutting process using a byte described later on the front surface 1a. Specifically, a substrate support table (not shown) having a flat support surface is prepared, and the semiconductor substrate 1 is fixed to the substrate support table by suctioning the surface 1a by suction, for example, by vacuum suction. . At this time, the front surface 1a is forcibly flattened by adsorption to the support surface, whereby the front surface 1a becomes a reference surface for flattening the back surface 1b. In this state, the rear surface lb is machined, in this case, mechanically ground, and the convex portion 1c of the rear surface 1b is ground and removed to be flattened. In this case, it is preferable to control the cutting amount of the back surface 1b by the distance from the front surface 1a. As a result, as shown in FIG. 1B, the thickness of the semiconductor substrate 1 is constant, specifically, the TTV (difference between the maximum thickness and the minimum thickness of the substrate) is equal to or less than a predetermined value. TTV will be controlled to 1 / im or less. Subsequently, as shown in FIG. 1C, the semiconductor substrate 1 is removed from the substrate support, and a photosensitive resin, for example, a photoresist is applied on the surface 1a of the semiconductor substrate 1, and the photoresist is subjected to photolithography. Then, a resist mask 12 having a predetermined bump pattern 12a is formed. Subsequently, using a resist mask 12 as a mask, a metal, for example, a copper film is formed by, for example, an evaporation method, and a plating electrode (not shown) is formed. Then, as shown in FIG. Then, gold (Au) is deposited so as to bury each bump pattern 12a of the resist mask 12 by a plating method, and an Au projection 2 is formed. Note that the projections may be formed using Cu, Ag, Ni, Sn, or an alloy thereof in addition to Au. Subsequently, the surface 1 a of the semiconductor substrate 1 is subjected to cutting using a byte to be flattened.
具体的には、 図 2 Aに示すように、 基板支持台 1 1の支持面 1 1 aに例えば真 空吸着により裏面 1 bを吸着させ、 半導体基板 1を基板支持台 1 1に固定する。 このとき、 裏面 1 bへの図 1 Bの平坦化処理により半導体基板 1の厚みが一定の 状態とされており、 更に裏面 1 bが支持面 1 1 aへの吸着により強制的にうねり 等もない状態となり、 これにより裏面 1 bが表面 1 aの平坦化の基準面となる。 この状態で、 表面 1 aにおける各 A u突起 2及びフォトレジスト 1 2の表層を機 械加工、 ここではダイヤモンド等からなるバイ ト 1 0を用いて切削加工し、 各 A u突起 2及びレジストマスク 1 2の表面が連続して平坦となるように平坦化処理 する。 これにより、 A u突起 2の上面が鏡面状に平坦化される。 この切削加工による平坦化の結果を図 3 A , 図 3 Bの顕微鏡写真の図及び模式 図に示す。  Specifically, as shown in FIG. 2A, the back surface 1b is sucked to the support surface 11a of the substrate support 11 by, for example, vacuum suction, and the semiconductor substrate 1 is fixed to the substrate support 11. At this time, the thickness of the semiconductor substrate 1 is kept constant by flattening the back surface 1b as shown in FIG. 1B, and the back surface 1b is also forced to undulate due to adsorption to the support surface 11a. As a result, the back surface 1b becomes a reference surface for flattening the front surface 1a. In this state, each Au projection 2 and the surface layer of the photoresist 12 on the surface 1a are machined, in this case, cut using a byte 10 made of diamond or the like, and each Au projection 2 and the resist mask are cut. A flattening process is performed so that the surface of 12 is continuously flat. Thereby, the upper surface of the Au projection 2 is flattened to a mirror surface. The results of the flattening by this cutting are shown in the micrographs and schematic diagrams of FIGS. 3A and 3B.
切削加工前には、図 3 Aのように A u突起の表面は凹凸状であったのに対して、 切削加工後には、 図 3 Bに示すように、 A u突起の表面が高精度に平坦化されて いることが判る。 続いて、 図 2 Bに示すように、 レジストマスク 1 2を灰化処理等により除去す る。 このとき、 半導体基板 1の表面 1 a上には、 高さが均一であり、 各 A u突起 2が切削加工されて上面 3 aがー様に平坦化されてなるバンプ 3が形成される。 この半導体基板 1を用い、 例えばこれをチップ化した後、 他の半導体基板 4とバ ンプ 3により電気的に接続する。 なお、 本実施形態では、 1枚の半導体基板について説明したが、 ロットを構成 する複数の半導体基板について本実施形態の各工程を実行し、 各半導体基板の厚 みを同一に均一化することが好適である。 また、 図 2 Aの平坦化工程において、 図 4 A， 図 4 Bに示すように、 裏面 l b 3 005092 を基準に半導体基板 1の平行出しを行うとともに、 表面 1 aの位置を検出し、 検 出された表面 1 aから削り量を算出して制御する。 具体的には、 図 4 Aに示すように、 表面 1 aの位置を検出する際に、 半導体基 板 1の表面 1 aの周辺部位の複数箇所、 ここでは例えば図 4 Bに示す 3箇所 A， B , Cにおけるレジストマスク 1 2にレーザ光 1 3を照射し、 これらを加熱飛散 させ、 表面 1 aの一部を露出させることが好適である。 またこの場合、 図 5に示すように、 表面 1 aの位置を検出する際に、 半導体基 板 1を開口 1 1 bの形成された基板支持台 1 1に吸着固定し、 開口 1 1 bから裏 面 1 bに赤外レーザ光を照射して、 表面 1 aからの反射光を例えば赤外レーザ測 定器 1 4により測定するようにしても良い。 Before cutting, the surface of the Au projection was uneven, as shown in Fig. 3A. After cutting, however, the surface of the Au projection was highly accurate, as shown in Fig. 3B. It can be seen that it has been flattened. Subsequently, as shown in FIG. 2B, the resist mask 12 is removed by ashing or the like. At this time, on the surface 1 a of the semiconductor substrate 1, bumps 3 having a uniform height, each Au projection 2 being cut and the upper surface 3 a being flattened in a flat manner are formed. Using this semiconductor substrate 1, for example, it is chipped and then electrically connected to another semiconductor substrate 4 by a bump 3. In this embodiment, one semiconductor substrate has been described. However, it is possible to execute each process of this embodiment on a plurality of semiconductor substrates constituting a lot so that the thickness of each semiconductor substrate is made uniform. It is suitable. Also, in the flattening process of FIG. 2A, as shown in FIG. 4A and FIG. The semiconductor substrate 1 is parallelized with reference to 3005092, the position of the surface 1a is detected, and the amount of shaving is calculated from the detected surface 1a for control. Specifically, as shown in FIG. 4A, when detecting the position of the surface 1a, a plurality of locations around the surface 1a of the semiconductor substrate 1, for example, three locations shown in FIG. , B, and C, it is preferable to irradiate the resist mask 12 with a laser beam 13 and scatter it by heating to expose a part of the surface 1a. In this case, as shown in FIG. 5, when detecting the position of the front surface 1a, the semiconductor substrate 1 is suction-fixed to the substrate support base 11 having the opening 11b, and the semiconductor substrate 1 is fixed through the opening 1 The back surface 1b may be irradiated with an infrared laser beam, and the reflected light from the front surface 1a may be measured by, for example, an infrared laser measuring device 14.
(切削加工装置の構成） (Configuration of cutting equipment)
ここで、上述した切削加工工程を実行するための具体的な装置構成を説明する。 図 6は切削加工装置の構成を表したプロック図、 図 7は同様の概略構成図であ る。 この切削加工装置は、 半導体基板を収納する収納部 1 0 1、 半導体基板 1を 各処理部へ搬送するためのハンド部 1 0 2、 半導体基板 1の位置決めを行うセン シング部 1 0 3、 切削時の半導体基板 1をチャックするチヤックテーブル部 1 0 4、 半導体基板 1の平坦化切削を行う切削部 1 0 5、 切削後の洗浄を行う洗浄部 1 0 6、そしてこれらをコントロールする制御部 1 0 7を有して構成されている。 チャックテーブル部 1 0 4は、 上述したように半導体基板 1を載置固定する基板 支持台 （チャックテーブル） 1 1を構成しており、 切削部 1 0 5はダイヤモンド 等からなる切削工具である硬質のバイ ト 1 0を有している。 次に、 切削加工工程のフローについて、 図 7及び図 8を用いて説明する。  Here, a specific apparatus configuration for executing the above-described cutting process will be described. FIG. 6 is a block diagram showing the configuration of the cutting apparatus, and FIG. 7 is a similar schematic configuration diagram. The cutting apparatus includes a storage unit 101 for storing the semiconductor substrate, a hand unit 102 for transporting the semiconductor substrate 1 to each processing unit, a sensing unit 103 for positioning the semiconductor substrate 1, and a cutting unit. A chuck table 104 for chucking the semiconductor substrate 1 at the time, a cutting unit 105 for flattening and cutting the semiconductor substrate 1, a cleaning unit 106 for cleaning after cutting, and a control unit 1 for controlling these. 07. The chuck table section 104 constitutes a substrate support (chuck table) 11 on which the semiconductor substrate 1 is mounted and fixed as described above, and the cutting section 105 is a hard cutting tool made of diamond or the like. It has 10 bytes. Next, the flow of the cutting process will be described with reference to FIGS.
先ず、 半導体基板 1が収納された収納部 1 0 1の収納カセッ卜 1 1 1から、 ハ ンド部 1 0 2の搬送ハンドが半導体基板 1を取り出す。 収納部 1 0 1にはエレべ 一夕機構があり、 搬送ハンドの半導体基板 1の取り出し高さまで昇降する。 次に 搬送ハンドが半導体基板をバキューム吸着し、 センシング部 1 0 3へ搬送する。 搬送ハンドは、 ® 3軸と Z軸のスカラー型口ポットになっており、 各処理部へ容 易にハンドリングすることができる。 口ポットの機構はこの限りではなく、 X Y 軸直行型でも良い。 センシング部 1 0 3では、 回転テーブル 1 1 2により半導体基板 1を 3 6 0 ° 回転させ、 その半導体基板 1の外周を C C Dカメラ 1 1 1で撮像し、 その結果を 制御部 1 0 7の演算部で処理して半導体基板 1のセンタ一位置を算出する。 次に、 搬送ハンドは、 その結果を元に、 位置を補正して半導体基板 1をチヤッ クテ一ブル部 1 0 4へ搬送し、 チヤックテーブル 1 1はバキュームによってこれ を固定する。 このチャックテーブル 1 1が加工の基準面となる。 従って固定時及 び加工時の平面精度を保っため、 チャック面は多穴質の材料を使用して半導体基 板 1を全面チャックする構造が好ましい。 材質は金属系、 セラミック系、 樹脂系 などを用いる。 チャックされた半導体基板 1と対向して投光部 1 1 4である光セ ンサ部が配置され、 受光部 1 1 5であるカメラ部と共に半導体基板 1の寸法を測 定及び演算し、 その結果を切削部 1 0 5の X軸駆動部へフィードパックし、 切削 するための移動量を指令する。 切削面が配線形成面の場合、具体的には図 4に示すように、レーザ光を照射し、 レジストマスクを加熱飛散させ、 表面を露出させることが好ましい。 そして図 5 に示すように、赤外レーザ光を利用した透過型センサを利用して位置を計測する。 そして、 そこで演算された結果を元に、 実際に切削を行うバイ ト 1 0が搭載され たテーブルが X方向に移動し、 切削を開始する。 ここで使用するバイ ト 1 0は、 ダイヤモンド等からなる。 このようにして設定寸法までの切削を完了する。 次に、 搬送ハンドがチャックテーブル 1 1から半導体基板 1を取り出し、 洗浄 部へと搬送する。 洗浄部 1 0 5では半導体基板 1をバキューム固定して回転させ ながら、 洗净水により加工後の表面残留異物を洗い流す。 その後、 エアブローし ながら高速回転させ、洗浄水を吹き飛ばしながら乾燥させる。乾燥が完了したら、 再び搬送ハンドが半導体基板 1を取り出し、 最後に収納部 1 0 1の収納カセット 1 1 1に収納する。 以上の各工程を、 先ずバンプ及びバンプ間に絶縁膜が形成されている面を基準 として裏面を切削し、 その後、 裏面を基準として各バンプの表面及び絶縁膜の表 面を切削という処理を行い、 平坦化処理を完了する。 First, the transfer hand of the hand unit 102 takes out the semiconductor substrate 1 from the storage cassette 111 of the storage unit 101 in which the semiconductor substrate 1 is stored. The storage unit 101 has an elevator mechanism, which moves up and down to a level at which the semiconductor substrate 1 is taken out of the transfer hand. next The transfer hand vacuum sucks the semiconductor substrate and transfers it to the sensing unit 103. The transfer hand is a 3-axis and Z-axis scalar type pot and can be easily handled to each processing unit. The mechanism of the mouth pot is not limited to this, and the XY axis perpendicular type may be used. In the sensing unit 103, the semiconductor substrate 1 is rotated by 360 ° using the rotary table 112, the outer periphery of the semiconductor substrate 1 is imaged by the CCD camera 111, and the result is calculated by the control unit 107. The processing is performed by the section to calculate one center position of the semiconductor substrate 1. Next, the transfer hand corrects the position based on the result, and transfers the semiconductor substrate 1 to the check table 104, and the check table 11 is fixed by vacuum. The chuck table 11 serves as a reference surface for processing. Therefore, in order to maintain the planar accuracy at the time of fixing and at the time of processing, it is preferable that the chuck surface is made of a material having a plurality of holes and chucks the entire surface of the semiconductor substrate 1. The material is metal, ceramic, resin, etc. An optical sensor unit, which is a light emitting unit 114, is arranged opposite to the chucked semiconductor substrate 1, and the dimensions of the semiconductor substrate 1 are measured and calculated together with a camera unit, which is a light receiving unit 115. Is fed to the X-axis drive unit of the cutting unit 105, and the movement amount for cutting is commanded. When the cut surface is a wiring forming surface, specifically, as shown in FIG. 4, it is preferable to irradiate a laser beam to heat and scatter the resist mask to expose the surface. Then, as shown in FIG. 5, the position is measured using a transmission sensor using infrared laser light. Then, based on the result calculated, the table on which the byte 10 for actually performing cutting is mounted moves in the X direction, and cutting is started. The byte 10 used here is made of diamond or the like. Thus, the cutting to the set dimension is completed. Next, the transfer hand takes out the semiconductor substrate 1 from the chuck table 11 and transfers it to the cleaning unit. In the cleaning unit 105, the semiconductor substrate 1 is vacuum-fixed and rotated, and the surface residual foreign matter after processing is washed away with the washing water. Then air blow While rotating at high speed, dry while washing away the washing water. When the drying is completed, the transport hand takes out the semiconductor substrate 1 again, and finally stores it in the storage cassette 111 of the storage section 101. In each of the above steps, first, the back surface is cut with reference to the bumps and the surface on which the insulating film is formed between the bumps, and then the front surface of each bump and the surface of the insulating film are cut with reference to the back surface. Complete the planarization process.
(半導体装置及びその製造方法） (Semiconductor device and manufacturing method thereof)
次に、 上述したバンプの形成方法を実行する半導体製造装置を用いて、 半導体 装置を製造する方法について説明する。 なおここでは、 半導体装置の構成をその 製造方法と共に述べる。  Next, a method of manufacturing a semiconductor device using a semiconductor manufacturing apparatus that executes the above-described method of forming a bump will be described. Here, the configuration of the semiconductor device will be described together with its manufacturing method.
図 9 A〜図 9 Cは、 本実施形態による半導体装置の製造方法を工程順に示す概 略平面図である。 先ず、 図 1及び図 2で説明した各工程を経て、 L S I素子等が搭載され、 バイ トを用いた切削加工により上面 3 aの平坦化されたバンプ 3を有する半導体基板 1から、 図 9 Aに示すように、 各半導体チップ 2 1を切り出す。 続いて、 図 9 Bに示すように、 バイ トを用いた切削加工により上面の平坦化さ れたバンプ 3を有する半導体基板 2 2を用意し、 この半導体基板 2 2上に、 各半 導体チップ 2 1をバンプ 3の平坦化された上面 3 a同士で電気的に接続する。 具 体的には、 半導体基板 2 2と半導体チップ 2 1 aとを上面 3 a同士で対向するよ うに配置し、 室温〜 3 5 0 、 ここでは 1 7 0 C程度で圧着させ、 接続する。 各 上面 3 aは共に高精度に平坦化されているため、 従来のように高温 · 高圧等を要 することなく、 半導体基板 2 2.と半導体チップ 2 1とを容易に接続することがで きる。 そして、 図 9 Cに示すように、 半導体チップ 2 1の接続された半導体基板 2 2 から半導体チップ 2 3毎に切 ¾)出し、 ワイヤボンディング法 （ワイヤ 2 5を用い た接続） 等の工程を経て、 基板 2 4上に半導体チップ 2 3を搭載し、 半導体装置 を完成させる。 以上説明したように、 本実施形態によれば、 C M Pに替わり、 半導体基板 1上 に形成された微細なバンプ 3の表面を、 ディッシング等の不都合を発生させるこ となく安価に高速で平坦化し、 バンプ 3の接続を容易且つ確実に行うことが可能 となる。 これにより、 バンプ 3同士の高温 · 高圧等の条件を要しない接続が可能 となり、 信頼性の高い半導体装置を歩留まり良く製造することができる。 9A to 9C are schematic plan views illustrating the method for manufacturing the semiconductor device according to the present embodiment in the order of steps. First, through the steps described with reference to FIGS. 1 and 2, the semiconductor device 1 on which the LSI element and the like are mounted and which has the bumps 3 whose upper surfaces 3a are flattened by cutting using a byte is shown in FIG. Each semiconductor chip 21 is cut out as shown in FIG. Subsequently, as shown in FIG. 9B, a semiconductor substrate 22 having bumps 3 whose upper surface is flattened by cutting using a byte is prepared, and each semiconductor chip is placed on the semiconductor substrate 22. 2 1 is electrically connected between the flattened upper surfaces 3 a of the bumps 3. Specifically, the semiconductor substrate 22 and the semiconductor chip 21a are arranged so that the upper surfaces 3a face each other, and are connected by being press-bonded at room temperature to 350, here, about 170C. Since each upper surface 3a is flattened with high precision, the semiconductor substrate 2 2. and the semiconductor chip 21 can be easily connected without requiring high temperature and high pressure as in the conventional case. . Then, as shown in FIG. 9C, the semiconductor substrate 22 to which the semiconductor chip 21 is connected The semiconductor chip 23 is mounted on the substrate 24 through processes such as wire bonding (connection using the wire 25) and the like, and the semiconductor device is completed. As described above, according to the present embodiment, instead of CMP, the surface of the fine bumps 3 formed on the semiconductor substrate 1 is flattened at low cost and at high speed without inconvenience such as dishing. The connection of the bumps 3 can be performed easily and reliably. As a result, the bumps 3 can be connected to each other without requiring conditions such as high temperature and high pressure, and a highly reliable semiconductor device can be manufactured with high yield.
[第 2の実施形態] [Second embodiment]
次に、 第 2の実施形態について説明する。 第 1の実施形態では、 バンプ材料と して A uを例示したが、 本実施形態ではニッケル （N i ) を用いる場合を例示す る。  Next, a second embodiment will be described. In the first embodiment, Au is exemplified as the bump material. However, in the present embodiment, a case in which nickel (Ni) is used will be described.
図 1 0 A〜図 1 0 Fは、 本実施形態によるバンプの形成方法を工程順に示す概 略断面図である。 先ず、 第 1の実施形態の図 1 A , Bと同様の工程を経て、 半導体基板 1を裏面 研削し、 T T Lを所定値以下、 具体的には 1 ii m以下に制御する。  10A to 10F are schematic cross-sectional views showing a method for forming a bump according to the present embodiment in the order of steps. First, the semiconductor substrate 1 is ground back through the same steps as in FIGS. 1A and 1B of the first embodiment, and the TTL is controlled to a predetermined value or less, specifically, 1 im or less.
この半導体基板 1を用い、 図 1 0 Aに示すように、 半導体基板 1の表面アルミ 二ゥム系金属からなる電極 3 1をパターン形成した後、 この電極 3 1に無電解メ ツキ法によりニッケルリンメツキ膜 3 2を膜厚 5 /z m〜 1 0 /z m程度に形成する, ニッケルリンメツキ膜 3 2は、 汎用の無電解メツキ法によって、 ニッケルーリ ン、ニッケル一リン—ホウ素、ニッケル一ホウ素などを用いて形成する。例えば、 ニッケル一リン合金は次亜リン酸浴（次亜リン酸ナトリゥムまたは次亜リン酸カ リゥム）で形成し、ニッケル一ホウ素合金は水素化ホウ素ナトリゥム浴またはジメ チルアミノポランを用い弱酸性浴または中性浴で形成し、 ニッケル—リン一ホウ 素合金は中性浴で形成する。 ここで、 ニッケルリン系無電解メツキでは、 上述した如何なる合金系を選択して も、 ニッケルリンメツキ膜 3 2の表層に機械的な脆弱層であるリン濃縮層 3 3が 形成される。 半田バンプ形成後、 このリン濃縮層が原因となりメツキと半田バン プとの界面強度が低下する。 このリン濃縮層の厚みは、 2 0 n m ~ 4 0 n m程度 であり、 メツキ浴中のリン含有率が高くなるほど厚くなる。 また、 このリン濃縮層は下地の材料（ガラス基板、 鉄基板、 アルミニウム基板） によらず、 またメツキの厚みに依らず生成される。 また、 例えば特許文献 6で記 載されているようなニッケル系無電解メツキを半田融点以上のァニール処理をし ても、 表層には必ずリン濃縮層が生成される。 リン濃縮層を除去しなければ、 高 信頼性のあるメツキ被膜と半田バンプの形成は困難である。 これらの問題について、 半田材料に銅を添加す'ることにより、 銅一ニッケル— 錫系の化合物層が形成され、 そのバリァ効果によりリン濃縮層の形成を抑制する 方法がある。 ところが、 A uメツキ厚が 5 0 0 n m以上ではリン濃縮層が形成さ れるなど、 A uメツキ厚の制約や、 半田材料の選択性が狭まるという問題点があ る。 そこで本例では、 ニッケルリンメツキ膜 3 2の切削加工による平坦化時に、 同 時にこのリン濃縮層 3 3を除去する。 Using this semiconductor substrate 1, as shown in FIG. 10A, an electrode 31 made of an aluminum-based metal is patterned on the surface of the semiconductor substrate 1, and then nickel is applied to the electrode 31 by an electroless plating method. Nickel phosphorus, nickel-phosphorus-boron, nickel-boron, etc. are formed by a general-purpose electroless plating method by forming a phosphorus plating film 32 to a thickness of about 5 / zm to 10 / zm. It is formed using. For example, a nickel-phosphorous alloy is formed in a hypophosphorous acid bath (sodium hypophosphite or calcium hypophosphite), and a nickel-boron alloy is formed in a sodium borohydride bath or a weak acid bath using dimethylaminoporan. Alternatively, it is formed in a neutral bath, and the nickel-phosphorus-boron alloy is formed in a neutral bath. Here, in the nickel-phosphorus electroless plating, a phosphorus-enriched layer 33, which is a mechanically fragile layer, is formed on the surface of the nickel-phosphorus plating film 32, regardless of which alloy system is selected. After the formation of the solder bumps, the interface strength between the plating and the solder bumps is reduced due to the phosphorus concentration layer. The thickness of the phosphorus-enriched layer is about 20 nm to 40 nm, and the thickness increases as the phosphorus content in the plating bath increases. In addition, this phosphorus concentration layer is generated irrespective of the underlying material (glass substrate, iron substrate, aluminum substrate) and regardless of the thickness of the plating. Further, for example, even if a nickel-based electroless plating described in Patent Document 6 is subjected to an annealing treatment at a temperature equal to or higher than the solder melting point, a phosphorus-enriched layer is always generated on the surface layer. Unless the phosphorus enrichment layer is removed, it is difficult to form highly reliable plating films and solder bumps. Regarding these problems, there is a method of forming a copper-nickel-tin-based compound layer by adding copper to a solder material, and suppressing the formation of a phosphorus-enriched layer by its barrier effect. However, when the Au plating thickness is 500 nm or more, there is a problem that the Au plating thickness is restricted and the selectivity of the solder material is narrowed, such as the formation of a phosphorus-enriched layer. Therefore, in this example, when the nickel phosphor plating film 32 is flattened by cutting, the phosphorus enriched layer 33 is removed at the same time.
具体的には、 先ず図 1 0 Bに示すように、 基板表面を覆うように保護膜 3 4と して液状レジストを被覆し、 後述の切削加工による物理的衝撃の緩和層とする。 保護膜 3 4は、 回転塗布等で 1 0 m〜 1 5 程度の厚みに塗布し、 キュアす ることにより形成する。 その後、 図 2 Aと同様、 基板支持台の支持面に例えば真空吸着により裏面を吸 着させ、 半導体基板 1を基板支持台に固定する。 このとき、 裏面 l bへの図 1 B の平坦化処理により半導体基板 1の厚みが一定の状態とされており、 更に裏面 1 bが支持面 1 1 aへの吸着により強制的にうねり等もない状態となり、 これによ り裏面 1 bが表面 1 aの平坦化の基準面となる。 この状態で、 図 1 0 Cに示すよ うに、 表面 1 aにおける各ニッケルリンメツキ膜 3 2及び保護膜 3 4の表層を機 械加工、 ここではダイヤモンド等からなるバイトを用いて切削加工し、 ニッケル リンメツキ膜 3 2のリン濃縮層 3 3を除去するとともに、 ニッケルリンメツキ膜 3 2及び保護膜 3 4の表面が連続して平坦となるように平坦化処理する。 切削量 は、 リン濃縮層 3 3を確実に除去できる 1 π！〜 2 m程度とする。 続いて、 必要に応じて、 図 1 0 Dに示すように、 無電解メツキ法により、 ニッ ケルリンメツキ膜 3 2上に金メッキ膜 3 5を形成する。 金メッキ膜 3 5の厚みは 3 0 n m〜 5 0 n m程度が好ましい。 続いて、 図 1 0 Eに示すように、 保護膜 3 4を灰化処理等により,除去する。 こ のとき、 半導体基板 1の表面 1 a上には、 高さが均一であり、 切削加工により上 面が一様に平坦化され、 金メツキ膜 3 5が形成されてなるバンプ 3 6が形成され る。 そして、 必要に応じて、 図 1 0 Fに示すように、 バンプ 3 6上に半田バンプ 3 7を形成する。 この半田バンプ 3 7は、 スクリーン印刷、 半田ポール法、 溶融等 により形成する。 半田の材質としては、 鉛を含まない、 スズー銀系、 スズ—亜鉛 系、 等の半田を用いることが望ましい。 その後、 フルカツ トダイシングにより半導体基板 1を分割して半導体チップを 切り出し、 第 1の実施形態と同様に半導体装置を完成させる。 以上説明したように、 本実施形態によれば、 C M Pに替わり、 半導体基板 1上 に形成されたニッケルのバンプ 3 6の表面を、 デイツシング等の不都合を発生さ せることなく安価に高速で平坦化し、 これにより、 バンプ 3 6同士の高温 ·高圧 等の条件を要しない接続が可能となり、 信頼性の高い半導体装置を歩留まり良く 製造することができる。 しかも、 バンプ 3 6と半田バンプ 3 7との接合部位にお ける信頼性を低下させるリン濃縮層 3 4を低コス卜で完全に除去できるため、 上 面が平坦化されたバンプ 3 6上に半田バンプ 3 7を確実に形成することが可能と なる。 Specifically, first, as shown in FIG. 10B, a liquid resist is coated as a protective film 34 so as to cover the surface of the substrate, thereby forming a layer for alleviating a physical impact by a cutting process described later. The protective film 34 is formed by spin coating or the like to a thickness of about 10 m to 15 and curing. Then, as in FIG. 2A, the back surface is sucked to the support surface of the substrate support by, for example, vacuum suction, and the semiconductor substrate 1 is fixed to the substrate support. At this time, the thickness of the semiconductor substrate 1 is kept constant by the flattening process of FIG. The b is forcibly absorbed into the support surface 11a, so that there is no waviness or the like, whereby the back surface 1b becomes a reference surface for flattening the front surface 1a. In this state, as shown in Fig. 10C, the surface layer of each nickel phosphor coating film 32 and the protective film 34 on the surface 1a is machined, and in this case, cut using a cutting tool made of diamond or the like, The phosphorus concentration layer 33 of the nickel phosphorus plating film 32 is removed, and a flattening process is performed so that the surfaces of the nickel phosphorus plating film 32 and the protective film 34 are continuously flat. The amount of cutting is 1π, which can reliably remove the phosphorus enriched layer 3 3! ~ 2 m. Subsequently, if necessary, as shown in FIG. 10D, a gold plating film 35 is formed on the nickel plating film 32 by an electroless plating method. The thickness of the gold plating film 35 is preferably about 30 nm to 50 nm. Subsequently, as shown in FIG. 10E, the protective film 34 is removed by ashing or the like. At this time, bumps 36 are formed on the surface 1 a of the semiconductor substrate 1 with a uniform height, and the upper surface is uniformly flattened by the cutting process, and the gold plating film 35 is formed. Is performed. Then, as necessary, a solder bump 37 is formed on the bump 36 as shown in FIG. 10F. The solder bumps 37 are formed by screen printing, a solder pole method, melting, or the like. As a material of the solder, it is desirable to use a solder containing no lead, such as tin-silver or tin-zinc. Thereafter, the semiconductor substrate 1 is divided by full-cut dicing, and semiconductor chips are cut out to complete a semiconductor device as in the first embodiment. As described above, according to the present embodiment, in place of CMP, the surface of the nickel bump 36 formed on the semiconductor substrate 1 is flattened at low cost and at high speed without inconvenience such as dicing. This makes it possible to connect the bumps 36 with each other without requiring conditions such as high temperature and high pressure, and to produce a highly reliable semiconductor device with high yield. Can be manufactured. Moreover, since the phosphorus-enriched layer 34, which lowers the reliability at the joint between the bump 36 and the solder bump 37, can be completely removed at low cost, the bump 36 having a flat upper surface can be removed. The solder bumps 37 can be reliably formed.
[第 3の実施形態] [Third embodiment]
次に、 第 3の実施形態について説明する。 第 1の実施形態では、 半導体基板に 多数の半導体チップを接合する場合について例示したが、 本実施形態では半導体 チップの状態で上述の平坦化処理を実行し、 この半導体チップ同士を接合する場 合について開示する。  Next, a third embodiment will be described. In the first embodiment, the case where a large number of semiconductor chips are bonded to the semiconductor substrate is described. In the present embodiment, the case where the above-described flattening process is performed in the state of the semiconductor chip and the semiconductor chips are bonded to each other Is disclosed.
図 1 1 A , 図 1 1 Bは、 本実施形態による半導体装置の製造方法を工程順に示 す概略断面図である。 先ず、 図 1 1 Aに示すように、 第 1の実施形態の裏面研削をすることなく、 L S I素子等が搭載され、 高さの異なる （未だ高さにバラツキのある） 複数のバン プ、 ここでは A uバンプ 4 2が形成されてなる半導体基板から、 個々の半導体チ ップ 4 1を切り出す。 続いて、 半導体チップ 4 1の表層を機械加工、 ここでは第 1の実施形態と同様 にダイヤモンド等からなるバイ トを用いて切削加工し、 各 A uバンプ 4 2の表面 が連続して平坦となるように平坦化処理する。 これにより、 各 A uバンプ 4 2の 高さが均一化されるとともに、 上面が鏡面状に平坦化される。 続いて、 図 1 1 Bに示すように、 一対の半導体チップ 4 1を対向させ、 A uバ ンプ 4 2の平.坦化された上面同士で両者を電気的に接続する。 具体的には、 一対 の半導体チップ 4 1を上面同 ±で対向するように配置し、 室温〜 3 5 0 °C、 ここ では 1 7 0で程度で圧着させ、 接続する。 各上面は共に高精度に平坦化されてい るため、 従来のように高温 ·高圧等を要することなく、 一対の半導体チップ 4 1 を容易に接続することができる。 このように、 本実施形態によれば、 C M Pに替わり、 半導体チップ 4 1上に形 成された微細な A uバンプ 4 2の表面を、 ディッシング等の不都合を発生させる ことなく安価に高速で平坦化し、 一対の半導体チップ 4 1における A uバンプ 4 2の接続を容易且つ確実に行うことが可能となる。 これにより、 八11パンプ4 2 同士の高温 ·高圧等の条件を要しない接続が可能となり、 信頼性の高い半導体装 置を歩留まり良く製造することができる。 しかも、 半導体基板から個々の半導体 チップ 4 1に切り出した後に上述の切削加工を実行するため、 T T Vを制御する 工程を省略することができ、 工程数削減に寄与する。 11A and 11B are schematic cross-sectional views showing the method for manufacturing the semiconductor device according to the present embodiment in the order of steps. First, as shown in FIG. 11A, a plurality of bumps having different heights (the heights still vary) are mounted without mounting the back surface of the first embodiment, without mounting the LSI element. Then, individual semiconductor chips 41 are cut out from the semiconductor substrate on which the Au bumps 42 are formed. Subsequently, the surface layer of the semiconductor chip 41 is machined, in this case, cut using a byte made of diamond or the like as in the first embodiment, so that the surface of each Au bump 42 is continuously flat. A flattening process is performed. Thereby, the height of each Au bump 42 is made uniform, and the upper surface is flattened to a mirror surface. Subsequently, as shown in FIG. 11B, a pair of semiconductor chips 41 are opposed to each other, and the flat upper surfaces of the Au bumps 42 are electrically connected to each other. Specifically, a pair of semiconductor chips 41 are arranged so as to face each other at the same upper surface, and are bonded by pressure bonding at room temperature to 350 ° C., here at about 170 °. Since each upper surface is flattened with high precision, the pair of semiconductor chips 41 can be easily connected without requiring high temperature and high pressure as in the conventional case. As described above, according to the present embodiment, instead of CMP, the surface of the fine Au bump 42 formed on the semiconductor chip 41 is flattened inexpensively at high speed without inconvenience such as dishing. Thus, the Au bumps 42 on the pair of semiconductor chips 41 can be easily and reliably connected. This makes it possible to connect the eight pumps 42 without requiring conditions such as high temperature and high pressure, and to manufacture a highly reliable semiconductor device with high yield. In addition, since the above-mentioned cutting is performed after the individual semiconductor chips 41 are cut out from the semiconductor substrate, the step of controlling the TTV can be omitted, which contributes to a reduction in the number of steps.
[変形例 1 ] [Modification 1]
ここで、 本実施形態の変形例 1について説明する。  Here, a first modification of the present embodiment will be described.
図 1 2 A〜図 1 2 Cは、 変形例 1による半導体装置の製造方法を工程順に示す 概略断面図である。 先ず、 図 1 2 Aに示すように、 第 1の実施形態の裏面研削をすることなく、 L S I素子等が搭載され、 高さの異なる （未だ高さにバラツキのある） 複数のバン プ、 ここでは A uバンプ 4 2が形成されてなる半導体基板から、 個々の半導体チ ップ 4 1を切り出す。 続いて、 半導体チップ 4 1の表面に A uバンプ 4 2を埋め込むように絶縁材か らなる樹脂層 4 3を形成する。 なお、 半導体基板の状態で A uバンプ 4 2を埋め 込むように樹脂層 4 3を形成した後、 個々の半導体チップ 4 1を切り出すように しても良い。 続いて、 図 1 2 Bに示すように、 半導体チップ 4 1の表層を機械加工、 ここで は第 1の実施形態と同様にダイヤモンド等からなるバイ トを用いて切削加工し、 各 A uバンプ 4 2の表面及び樹脂層 4 3の表面が連続して平坦となるように平坦 化処理する。 これにより、 各 A uバンプ 4 2の高さが均一化されるとともに、 上 面が鏡面状に平坦化される。 ' 続いて、 一対の半導体チップ 4 1を対向させ、 A uバンプ' 4 2及び樹脂層 4 3 の平坦化された上面同士で両者を電気的に接続する。 具体的には、 一対の半導体 チップ 4 1を上面同士で対向するように配置し、 室温〜 3 5 0 °C、 ここでは 1 7 0 °C程度で圧着させ、 接続する。 各上面は共に高精度に平坦化されているため、 従来のように高温 · 高圧等を要することなく、 一対の半導体チップ 4 1を容易に 接続することができる。 更に、 樹脂膜 4 3がー対の半導体チップ 4 1の接合を確 実にするとともに、 電極 4 2等を保護するアンダーフィルとして寄与する。 このように、 本変形例 1によれば、 C M Pに替わり、 半導体チップ 4 1上に形 成された微細な A uバンプ 4 2の表面を、 ディッシング等の不都合を発生させる ことなく安価に高速で平坦化し、 一対の半導体チップ 4 1における A uバンプ 4 2の接続を容易且つ確実に行うことが可能となる。 これにより、 A uバンプ 4 2 同士の高温 ·高圧等の条件を要しない接続が可能となり、 信頼性の高い半導体装 置を歩留まり良く製造することができる。 しかも、 半導体基板から個々の半導体 チップ 4 1に切り出した後に上述の切削加工を実行するため、 T T Vを制御する 工程を省略することができ、 工程数削減に寄与する。 12A to 12C are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to Modification 1 in the order of steps. First, as shown in FIG. 12A, a plurality of bumps having different heights (the height still varies) are mounted on the LSI device and the like without grinding the back surface of the first embodiment. Then, individual semiconductor chips 41 are cut out from the semiconductor substrate on which the Au bumps 42 are formed. Subsequently, a resin layer 43 made of an insulating material is formed on the surface of the semiconductor chip 41 so as to bury the Au bumps 42. After forming the resin layer 43 so as to bury the Au bumps 42 in the state of the semiconductor substrate, the individual semiconductor chips 41 may be cut out. Subsequently, as shown in FIG. 12B, the surface layer of the semiconductor chip 41 is machined. Here, as in the first embodiment, cutting is performed using a byte made of diamond or the like, and each Au bump is cut. A flattening process is performed so that the surface of 42 and the surface of the resin layer 43 are continuously flat. As a result, the height of each Au bump 42 is made uniform, and The surface is flattened to a mirror surface. Subsequently, the pair of semiconductor chips 41 are opposed to each other, and the Au bumps 42 and the flattened upper surfaces of the resin layer 43 are electrically connected to each other. Specifically, a pair of semiconductor chips 41 are arranged so that the upper surfaces thereof are opposed to each other, and are crimped at room temperature to 350 ° C., here about 170 ° C., and connected. Since both upper surfaces are flattened with high precision, the pair of semiconductor chips 41 can be easily connected without requiring high temperature, high pressure, or the like as in the related art. Further, the resin film 43 ensures the bonding of the pair of semiconductor chips 41 and also serves as an underfill for protecting the electrodes 42 and the like. As described above, according to the first modification, instead of CMP, the surface of the fine Au bump 42 formed on the semiconductor chip 41 can be inexpensively operated at high speed without inconvenience such as dishing. The flattening makes it possible to easily and reliably connect the Au bumps 42 on the pair of semiconductor chips 41. As a result, the Au bumps 42 can be connected to each other without requiring conditions such as high temperature and high pressure, and a highly reliable semiconductor device can be manufactured with high yield. In addition, since the above-mentioned cutting is performed after the individual semiconductor chips 41 are cut out from the semiconductor substrate, the step of controlling the TTV can be omitted, which contributes to a reduction in the number of steps.
[変形例 2 ] [Modification 2]
次いで、 本実施形態の変形例 2について説明する。  Next, a second modification of the present embodiment will be described.
図 1 3 A〜図 1 3 Cは、 変形例 2による半導体装置の製造方法を工程順に示す 概略断面図である。 先ず、 図 1 3 Aに示すように、 第 1の実施形態の裏面研削をすることなく、 L S I素子等が搭載され、 高さの異なる （未だ高さにバラツキのある） 複数のバン プ、 ここでは A uバンプ 4 2が形成されてなる半導体基板から、 個々の半導体チ ップ 4 1を切り出す。 続いて、 半導体チップ 4 1の表層を機械加工、 ここでは第 1の実施形態と同様 にダイヤモンド等からなるバイ トを用いて切削加工し、 各 A uバンプ 4 2の表面 表面が連続して平坦となるように平坦化処理する。 これにより、 各 A uバンプ 4 2の高さが均一化されるとともに、 上面が鏡面状に平坦化される。 続いて、 図 1 3 Bに示すように、 平坦化処理された半導体チップ 4 1を 2つ一 組で一対の半導体チップ 4 1とし、 一方の半導体チップ 4 1の表面に A uバンプ 4 2を完全に埋め込む厚みに、 絶縁性の樹脂に導電性微粒子 4 5を含有する樹脂 層 4 4を形成する。 続いて、 一対の半導体チップ 4 1を対向させ、 A uバンプ 4 2の平坦化された 上面同士で両者を電気的に接続する。 具体的には、 一対の半導体チップ 4 1を上 面同士で対向するように配置し、 室温〜 3 5 0 °C、 ここでは 1 7 0 °C程度で圧着 させる。 ここで、 熱圧着により対向する A uバンプ 4 2同士が導電性微粒子 4 5 を介して接触し、 電気的に接続される。 各上面は共に高精度に平坦化されている ため、 従来のように高温 ·高圧等を要することなく、 一対の半導体チップ 4 1を 容易に接続することができる。 更に、 樹脂層 4 4の樹脂が一対の半導体チップ 4 1の密着性及び電気的接続を確実にするとともに、 電極 4 2等を保護するアンダ —フィルとして寄与する。 このように、 本変形例 2によれば、 C M Pに替わり、 半導体チップ 4 1上に形 成された微細な A uバンプ 4 2の表面を、 ディッシング等の不都合を発生させる ことなく安価に高速で平坦化し、 一対の半導体チップ 4 1における A uバンプ 4 2の接続を容易且つ確実に行うことが可能となる。 これにより、 八11バンプ4 2 同士の高温 ·高圧等の条件を要しない接続が可能となり、 信頼性の高い半導体装 置を歩留まり良く製造することができる。 しかも、 半導体基板から個々の半導体 チップ 4 1に切り出した後に上述の切削加工を実行するため、 T T Vを制御する 工程を省略することができ、 工程数削減に寄与する。 [第 4の実施形態] 13A to 13C are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to Modification 2 in the order of steps. First, as shown in FIG. 13A, a plurality of bumps having different heights (the heights still vary) are mounted without the back surface grinding of the first embodiment and the LSI elements and the like are mounted. Then, individual semiconductor chips 41 are cut out from the semiconductor substrate on which the Au bumps 42 are formed. Subsequently, the surface layer of the semiconductor chip 41 is machined. Here, as in the first embodiment, cutting is performed using a byte made of diamond or the like, and the surface of each Au bump 42 is continuously flat. The flattening process is performed so that Thereby, the height of each Au bump 42 is made uniform, and the upper surface is flattened to a mirror surface. Subsequently, as shown in FIG. 13B, the pair of the semiconductor chips 41 subjected to the flattening treatment is formed into a pair of semiconductor chips 41, and Au bumps 42 are formed on the surface of one of the semiconductor chips 41. A resin layer 44 containing conductive fine particles 45 in an insulating resin is formed to a thickness completely embedded. Subsequently, the pair of semiconductor chips 41 are opposed to each other, and the flattened upper surfaces of the Au bumps 42 are electrically connected to each other. Specifically, a pair of semiconductor chips 41 are arranged so that their upper surfaces face each other, and they are pressure-bonded at room temperature to 350 ° C., here about 170 ° C. Here, the Au bumps 42 facing each other by thermocompression bonding contact each other via the conductive fine particles 45 and are electrically connected. Since each of the upper surfaces is flattened with high precision, the pair of semiconductor chips 41 can be easily connected without requiring high temperature, high pressure, or the like as in the related art. Further, the resin of the resin layer 44 ensures the adhesion and electrical connection between the pair of semiconductor chips 41, and also contributes as an underfill for protecting the electrodes 42 and the like. As described above, according to the second modification, instead of CMP, the surface of the fine Au bump 42 formed on the semiconductor chip 41 can be inexpensively operated at high speed without inconvenience such as dishing. The flattening makes it possible to easily and reliably connect the Au bumps 42 on the pair of semiconductor chips 41. This makes it possible to connect the eight bumps 42 without requiring conditions such as high temperature and high pressure, and to manufacture highly reliable semiconductor devices with high yield. In addition, since the above-mentioned cutting is performed after the individual semiconductor chips 41 are cut out from the semiconductor substrate, the step of controlling the TTV can be omitted, which contributes to a reduction in the number of steps. [Fourth embodiment]
次に、 第 4の実施形態について説明する。 第 1の実施形態では、 半導体基板に 外部接続用のバンプを形成する場合について例示したが、 本実施形態ではワイヤ ボンディング法を用いたスタツドバンプを形成する場合について開示する。  Next, a fourth embodiment will be described. In the first embodiment, the case where the bump for external connection is formed on the semiconductor substrate is illustrated. However, the present embodiment discloses the case where the stud bump is formed using the wire bonding method.
図 1 4 A〜図 1 4 Fは、 本実施形態による半導体装置の製造方法を工程順に示 す概略断面図である。 先ず、 図 1 4 A及び図 1 4 Bに示すように、 図 1 Aと同様に素子形成部位に L S I半導体素子と電極パッ ド等の形成された半導体基板 5 1の裏面を研削し、 半 導体基板 5 1の厚みを一定、 具体的には T T V (基板の最大厚みと最小厚みとの 差） を 1 以下に制御する。 ここで、 前記研削工程においては、 半導体基板 5 1の裏面を研削した後に、 ス パッ夕法等により半導体基板 5 1上に金属膜、 例えば A 1膜を形成し、 これをパ 夕一ニングすることにより、 電気的接続箇所となる部位に電極パッド 5 2を形成 しても良い。 続いて、 図 1 4 Cに示すように、 金属として A uを用いたワイヤボンディ ング 法により、 例えば 2 0 / m径の A uボンディ ングワイヤの先端を溶融して形成 したポール状の塊を電極パッ ド 5 2上に圧着した後、 当該ワイヤを引きちぎり (プレカッ ト）、 電極パッ ド 5 2上に A u突起 5 3を形成する。 このとき、 各 A u突起 5 3の電極パッ ド 5 2からの高さをボンディ ングワイヤ径の 2倍以上、 .ここでは 6 0 m程度となるように規定する。 この場合、 実際には A u突起 5 3の高さにはバラツキがあり、 5 0 m〜 6 0 / m程度であれば良い。 続いて、 図 1 4 Dに示すように、 ダイヤモンド等からなるバイ ト 1 0を用いて 切削加工し、 各 A u突起 5 3の上面が連続して平坦となるように平坦化処理し、 スタツ ドバンプ 5 4を形成する。 ここでは、 切削位置を電極パッ ド 5 2から例え ば 5 0 m程度の高さとする。 切削条件は切削速度 1 0 m Z s 、 1回当たりの 送りを 2 0 m程度とし、 最初の切削位置から 2 mずつ追い込んでゆく。 これ により、 図 1 4 Eに示すように、 A u突起 5 3の上面が鏡面状に平坦化され、 ス タッ ドバンプ 5 4が形成される。 この切削加工による平坦化方法は C M Pと比べてスラリーなどが必要なく、 切削工具であるバイ トはたとえ摩耗を起こして研磨して繰り返し使用できる ので、 コストが安い。 チヤックテーブルにチヤッキングした半導体基板を高速 回転させ、 その上でバイ トを所定の速度で移動させて、 任意の切り込み量を一 度に切削するため、 半導体基板 1枚当たり 1 ~ 2分間で終了可能であり、 非常 にスループッ トの高い方法である。 バイ トによる切削加工では、 切削条件を適. 切にすることにより、 A uのボンディ ングワイヤを用いたス夕ッ ドバンプの突 起なども、 突起の先端部で切削した場合でも、 突起の傾きや折れなどのない平 面出しが可能である。 しかしながら、 3 0 H V以下の硬度であると、 切削時に 突起の傾きが生じる恐れがあるため、 ワイヤの硬度は 3 O H v以上であること が望ましい。 本実施形態では、 切削加工の終点として、 全てのスタッ ドバンプについて、 切削面の径がワイヤ径と同等以上になった時点とする。 通常、 スタツ ドバンプ はプレカツ ト後の高さにばらつきが大きく、全てのスタツ ドバンプで切削面の 径がワイヤ径と同等以上になった点を確認するのは困難である。切削方法とし ては、バイ トが最も高いバンプに接触した点から 1〜 3 ^ m位ずつ追い込んで ゆき、 全てのバイ トの切削面を出すことが適当であるが、 毎回拡大されたカメ ラ画像等で確認するのは非効率的である。 そこで本実施形態では、 図 1 5 Aに示すように、 終点検出方法として、 レー ザ発信器 6 1及び検出器 6 2を備える検出装置を用いて、 切削加工後のスタツ ドバンプ 5 4の上面にレーザビームを操引し、 当該上面にて反射したレ一ザを 検出器 6 2で検出する方法を採用する。 そして、 図 1 5 Bに示すように、 検出されたレーザ強度が全ての A u突起 5 3にて所定の強度に達するまで加工を繰り返す。 この検出装置は切削工具の進 行方向後方に設置され、 切削工具と同期して進行することが望ましい。 スタツ ドバンプ 5 4の上面 （切削面） はほぼ鏡面とされているため、 レーザ光などは 全反射する。 切削工具と同期している場合、 切削工具の進行速度に比例して遅 延が生ずるため、 厳密には全ての反射光が検出されるとは限らないが、 切削速 度は速くとも 1 0数 m / sであるため、 ほぼ検出されると見なして良い。 本実施形態では、バイ トの後部からバイ トの進行と同期して.動くレーザ発信器 6 1及び検出器 6 2により、平坦化された A u突起 5 3の上面から反射されたレ —ザ光強度を測定しながら追い込んでゆき、 例えば 4 6 /i mの高さで全ての A u 突起 5 3の上面が露出されたことを感知し、 切削を終了とした。 ここで、 図 1 5 Cに示すように、 切削加工が不充分である塲合や、 切削面の 径がワイヤ径以下である場合には、切削面以外の箇所に当たったレーザ光は乱 反射し、 検出器に検出されない。 そのため、 図 1 5 Dに示すように、 検出され たレーザ光強度はボンディ ングワイヤと同径まで切削された面よりも弱くな る。 このようなスタッ ドバンプが一箇所でも確認された場合には、 自動的に更 に 1 ； α π！〜 2 ； a m程度追い込み、最終的に全バンプで一定量以上のレーザ光強 度が検出されるまで切削する。 これにより、 未切削又は切削不足による接続不 良を防止することができるとともに、 加工時間の大幅な短縮が可能となる。 そして、 図 1 4 Fに示すように、 半導体基板 5 1から各半導体チップ 5 5を 切り出し、 例えばフリップチップ法により、 半導体チップ 5 5 と回路基板 5 6 とを接続する。 具体的には、 半導体チップ 5 5の上面平坦化されたスタッ ドパ ンプ 5 4と、 回路基板 5 6の表面に形成された電極 5 7 とを対向させて接触さ せ、 加圧及び加熱により両者を接合する。 なおこの場合、 回路基板 5 6の電極14A to 14F are schematic cross-sectional views showing the method for manufacturing the semiconductor device according to the present embodiment in the order of steps. First, as shown in FIGS. 14A and 14B, similarly to FIG. 1A, the back surface of a semiconductor substrate 51 on which an LSI semiconductor element and an electrode pad are formed in an element forming portion is ground, and a semiconductor is formed. The thickness of the substrate 51 is kept constant, specifically, the TTV (difference between the maximum thickness and the minimum thickness of the substrate) is controlled to 1 or less. Here, in the grinding step, after grinding the back surface of the semiconductor substrate 51, a metal film, for example, an A1 film is formed on the semiconductor substrate 51 by a sputtering method or the like, and this is patterned. Thus, the electrode pad 52 may be formed at a portion that becomes an electrical connection portion. Then, as shown in Fig. 14C, a pole-shaped lump formed by melting the tip of a 20 / m diameter Au bonding wire, for example, by a wire bonding method using Au as the metal was used as an electrode. After crimping on the pad 52, the wire is torn off (precut) to form an Au projection 53 on the electrode pad 52. At this time, the height of each Au projection 53 from the electrode pad 52 is specified to be at least twice the diameter of the bonding wire, in this case about 60 m. In this case, the height of the Au projections 53 actually varies, and may be about 50 m to 60 / m. Subsequently, as shown in FIG. 14D, cutting is performed using a byte 10 made of diamond or the like, and a flattening process is performed so that the upper surface of each Au projection 53 is continuously flat. The bumps 54 are formed. Here, the cutting position is, for example, about 50 m from the electrode pad 52. The cutting conditions are as follows: cutting speed 10 mZ s, Feed is set to about 20 m, and drive in 2 m each from the first cutting position. As a result, as shown in FIG. 14E, the upper surface of the Au projection 53 is flattened into a mirror-like shape, and the stud bump 54 is formed. This flattening method by cutting requires less slurry than CMP, and the cost of the cutting tool is low because it can be worn and polished repeatedly, even if it is worn. The semiconductor substrate chucked on the chuck table is rotated at high speed, and then the byte is moved at a predetermined speed to cut an arbitrary cutting amount at a time, so it can be completed in 1 to 2 minutes per semiconductor substrate This is a very high-throughput method. In cutting with a byte, the cutting conditions are set to the appropriate value. By setting the cutting conditions, the bump of the bump using an Au bonding wire can be prevented. A flat surface without breakage is possible. However, if the hardness is less than 30 HV, the projection may be inclined during cutting, so that the hardness of the wire is preferably 3 OHv or more. In the present embodiment, the end point of the cutting process is a point in time when the diameter of the cut surface of all stud bumps becomes equal to or larger than the wire diameter. Normally, the height of stud bumps varies greatly after precutting, and it is difficult to confirm that the diameter of the cut surface of all stud bumps is equal to or larger than the wire diameter. As a cutting method, it is appropriate to drive in the order of 1 to 3 m from the point where the byte comes in contact with the highest bump, and to expose the cut surfaces of all the bytes. It is inefficient to check with an image or the like. Therefore, in the present embodiment, as shown in FIG. 15A, as an end point detection method, a detection device including a laser oscillator 61 and a detector 62 is used, and an upper surface of the cut bump 54 is used. A method is employed in which the laser beam is steered and the laser reflected from the upper surface is detected by the detector 62. Then, as shown in FIG. 15B, the processing is repeated until the detected laser intensity reaches a predetermined intensity at all the Au projections 53. It is desirable that this detector be installed behind the cutting tool in the traveling direction, and proceed in synchronization with the cutting tool. Since the upper surface (cut surface) of the stud bump 54 is almost mirror surface, the laser beam and the like are totally reflected. When synchronized with the cutting tool, delay occurs in proportion to the traveling speed of the cutting tool, so not all reflected light is detected strictly, but the cutting speed is at most 10 Since it is m / s, it can be considered that it is almost detected. In this embodiment, the laser reflected from the upper surface of the flattened Au projection 53 by the laser oscillator 61 and the detector 62 moving from the rear of the byte in synchronization with the advance of the byte. The cutting was completed while measuring the light intensity and detecting that the upper surfaces of all the Au projections 53 were exposed at a height of, for example, 46 / im. Here, as shown in Fig. 15C, when the cutting process is insufficient, or when the diameter of the cut surface is smaller than the wire diameter, the laser light that hits a part other than the cut surface is irregularly reflected. And is not detected by the detector. Therefore, as shown in Fig. 15D, the detected laser beam intensity is weaker than the surface cut to the same diameter as the bonding wire. If any such stud bump is found, it is automatically added to 1; α π! ~ 2: Drive in about am, and cut until all the bumps finally detect a certain amount or more of laser light intensity. As a result, connection failure due to uncut or insufficient cutting can be prevented, and the processing time can be significantly reduced. Then, as shown in FIG. 14F, each semiconductor chip 55 is cut out from the semiconductor substrate 51, and the semiconductor chip 55 and the circuit board 56 are connected by, for example, a flip chip method. Specifically, a stud pump 54 having a flattened upper surface of the semiconductor chip 55 and an electrode 57 formed on the surface of the circuit board 56 are brought into contact with each other, and pressurized and heated. Join them together. In this case, the electrodes of the circuit board 56
5 7 もスタツ ドバンプ 5 4と同様に、 上述した切削加工により平坦化した後、 フリップチップ接続するようにしても好適である。 以上説明したように、 本実施形態によれば、 C M Pに替わり、 半導体基板 5 1上に形成された微細なスタツ ドバンプ 5 4の表面を、 ディッシング等の不都合 を発生させることなく安価に高速で平坦化し、 スタツドバンプ 5 4の接続を容易 且つ確実に行うことが可能となる。 これにより、 バンプ同士の高温 · 高圧等の条 件を要しない接続が可能となり、 信頼性の高い半導体装置を歩留まり良く製造す ることができる。しかも、切削平坦化後におけるスタツ ドバンプ 5 4の高さを、 ワイヤ径を規定しない場合に比べて 1 . 5倍以上とすることができ、 半導体素 子への応力を緩和することが可能となり、 デバイス寿命を延ばすことが可能とな る。 更に、 切削における平坦面はワイヤ径と同等以上であるため、 同じワイヤ 径でも 2倍以上の接合強度を得ることができる。 また、 従来と同程度の接合強 度で充分な場合には、 ワイヤ径を細くすることができるため、 バンプピッチを 狭めることが可能なうえ、ボンディングワイヤにかかるコストを下げることが 可能となる。 Similarly to the case of the stud bump 54, it is preferable that the flattening 57 is flattened by the above-mentioned cutting process and then the flip chip is connected. As described above, according to the present embodiment, instead of CMP, the surface of the fine stud bump 54 formed on the semiconductor substrate 51 can be inexpensively and quickly flattened without causing inconvenience such as dishing. The connection of the stud bumps 54 can be easily and reliably performed. As a result, the bumps can be connected without requiring conditions such as high temperature and high pressure, and a highly reliable semiconductor device can be manufactured with high yield. In addition, the height of the stud bumps 54 after cutting and flattening can be 1.5 times or more as compared with the case where the wire diameter is not specified, so that stress on the semiconductor element can be reduced. Device life can be extended. Furthermore, since the flat surface in cutting is equal to or larger than the wire diameter, it is possible to obtain a bonding strength twice or more even with the same wire diameter. If the same bonding strength as the conventional one is sufficient, the wire diameter can be reduced, so that the bump pitch can be reduced and the cost of the bonding wire can be reduced.
[第 5の実施形態] [Fifth Embodiment]
次に、 第 5の実施形態について説明する。 ここでは、 いわゆる T A Bボンディ ング法による半導体装置を例示する。  Next, a fifth embodiment will be described. Here, a semiconductor device according to the so-called TAB bonding method is exemplified.
図 1 6及び図 1 7は、 本実施形態による半導体装置の製造方法を示す概略断面 図である。 この半導体装置を製造するには、 先ず第 1の実施形態と同様に、 図 1及び図 2 に示す諸工程を経て、 素子形成部位に L S I半導体素子等の形成された半導体基 板 1の電極 7 1上に下地金属膜 7 2を介して、 高さが均一であり、 各 A u突起 2 が切削加工されて上面 3 aがー様に平坦化されてなるバンプ 3を形成する。 ここ で、 半導体基板 1のバンプ 3の周囲には絶縁性の保護膜 7 3が形成されている。 続いて、 バンプ 3の上面にプローブを接触させることにより、 半導体基板 1の 半導体素子等の電気的特性を検査する。 ここで、 従来では、 当該検査の際にはバ ンプの凹凸や汚染の存するメツキ終端面にプローブを接触させていたため、 安定 した接触が得られず、 プローブの先端が当該凹凸部位で引っ掛り破損するという トラブルもあった。 これに対して本実施形態では、 上述の切削加工により高度に 平坦化及び清浄化されたバンプ 3の表面にプローブを接触させるため、 極めて安 定な状態で検査を行うことができる。 続いて、 この半導体基板 1から個々の半導体チップ 2 1を切り出した後、 図 1 6に示すように、 T A Bボンディング法により半導体チップ 2 1の接続を行う。 具体的には、 銅箔 7 5からなり A uの表面処理が施されて A u膜 7 6が形成さ れており、 一端に位置する箇所が接続部位に該り、 他端に樹脂層 7 7が設けられ てなる T A Bリード 7 4を用意する。 そして、 半導体チップ 2 1をボンディング ステージ 8 0上に載置固定して、 半導体チップ 2 1の平坦化及ぴ清浄化されたバ ンプ 3の上面に T A Bリード 7 4の接続部位の A u膜 7 6を接触させ、 ヒータ 7 8により加熱しながら加圧し、 両者を接合する。 ここで、 加熱温度は 2 0 0 °C程 度の比較的低温で良く、 接着荷重も約 2 0 gと従来の 2 / 3程度に低減が可能と なる。 結果として 4 0 i mピッチ以下の微細ピッチの T A Bリードを位置ずれな く接続することが可能となる。 しかる後、 図 1 7に示すように、 半導体チップ 2 1をボンディングステージ 8 0から外し、 バンプ 3と T A Bリード 7 4との接続部位を含む半導体チップ 2 1 の表面を覆うように封止樹脂 7 9を形成し、 半導体装置を完成させる。 なお、 本実施形態では、 バンプとレてメツキバンプを形成する場合を例示した が、 ワイヤボンディング法によるスタツ ドバンプを形成するようにしても良い。 以上説明したように、 本実施形態によれば、 C M Pに替わり、 半導体基板 1 上に形成された微細なバンプ 3の表面を、 ディッシング等の不都合を発生させる ことなく安価に高速で平坦化し、 バンプ 3の接続を容易且つ確実に行うことが可 能となる。 これにより、 バンプとリード端子との高温 · 高圧等の条件を要しない 確実な接続が可能となり、 信頼性の高い T A Bボンディングタイプの半導体装置 を歩留まり良く製造することができる。 FIGS. 16 and 17 are schematic sectional views showing the method for manufacturing the semiconductor device according to the present embodiment. In order to manufacture this semiconductor device, first, as in the first embodiment, through the various steps shown in FIGS. 1 and 2, the electrode 7 of the semiconductor substrate 1 on which an LSI semiconductor element or the like is formed A bump 3 having a uniform height, each Au projection 2 being cut, and an upper surface 3a being flattened on the upper surface 1 is formed on an underlying metal film 72. Here, an insulating protective film 73 is formed around the bumps 3 of the semiconductor substrate 1. Subsequently, the probe is brought into contact with the upper surface of the bump 3 to inspect the electrical characteristics of the semiconductor element and the like of the semiconductor substrate 1. Here, in the past, a conventional Because the probe was in contact with the bump end surface of the bump, which had unevenness and contamination, stable contact was not obtained, and there was a problem that the tip of the probe was caught and damaged by the uneven portion. On the other hand, in the present embodiment, since the probe is brought into contact with the surface of the bump 3 that has been highly flattened and cleaned by the above-described cutting, the inspection can be performed in an extremely stable state. Subsequently, after the individual semiconductor chips 21 are cut out from the semiconductor substrate 1, the semiconductor chips 21 are connected by a TAB bonding method as shown in FIG. Specifically, an Au film 76 is formed by a copper foil 75 subjected to a surface treatment of Au, and a portion located at one end corresponds to a connection portion, and a resin layer 7 at the other end. Prepare TAB lead 74 on which 7 is provided. Then, the semiconductor chip 21 is placed and fixed on the bonding stage 80, and the Au film 7 at the connection site of the TAB lead 74 is placed on the upper surface of the flattened and cleaned bump 3 of the semiconductor chip 21. 6 are brought into contact with each other and pressurized while being heated by a heater 78 to join them together. Here, the heating temperature may be a relatively low temperature of about 200 ° C., and the bonding load can be reduced to about 20 g, which is about 2/3 of the conventional value. As a result, it is possible to connect TAB leads having a fine pitch of 40 im pitch or less without displacement. Thereafter, as shown in FIG. 17, the semiconductor chip 21 is removed from the bonding stage 80, and the sealing resin 7 is covered so as to cover the surface of the semiconductor chip 21 including the connection portion between the bump 3 and the TAB lead 74. 9 is formed to complete the semiconductor device. In the present embodiment, the case in which the metal bump is formed instead of the bump is illustrated. However, the metal bump may be formed by a wire bonding method. As described above, according to the present embodiment, instead of CMP, the surface of the fine bump 3 formed on the semiconductor substrate 1 is flattened at low cost and at high speed without inconvenience such as dishing. Connection 3 can be easily and reliably performed. This eliminates the need for conditions such as high temperature and high pressure between bumps and lead terminals Reliable connection is possible, and highly reliable TAB bonding type semiconductor devices can be manufactured with high yield.
[第 6の実施形態] [Sixth embodiment]
次に、 第 6の実施形態について説明する。 ここでは、 上述した諸実施形態を実 行するに際して、 一対の基体 （ここでは、 フリップチップ法による半導体チップ 及び回路基板を例示する。） について、 上述の切削加工工程及び接合工程を実行す るための装置構成を開示する。 図 1 8は、 本実施形態による半導体製造装置を示す模式図である。  Next, a sixth embodiment will be described. Here, when executing the above-described embodiments, a pair of substrates (here, a semiconductor chip and a circuit board by a flip chip method are exemplified) are used to execute the above-described cutting process and joining process. The configuration of the device will be disclosed. FIG. 18 is a schematic diagram illustrating the semiconductor manufacturing apparatus according to the present embodiment.
この半導体製造装置は、 表面にバンプの形成された半導体チップを導入するた めのチップ導入部 8 1と、 表面に電極の形成された回路基板を導入するための回 路基板導入部 8 2と、 上述したバイ トを用いた切削加工により半導体チップのバ ンプ表面を平坦化する工程を実行する切削部 8 3と、 半導体チップと回路基板と を平坦化されたバンプと電極とで接合する工程を実行する接合部 8 4と、 接合さ れ一体化されてなる半導体装置を搬出するための搬出部 8 5とを備えており、 更 に、 切削部 8 3及び接合部 8 4を不活性雰囲気で包含する清浄化保持部 8 6を有 して構成されている。 ここで、 切削部 8 3では、 半導体チップのみならず回路基 板の電極表面も同様に切削加工により平坦化するようにしても良い。 清浄化保持部 8 6は、 平坦化工程と接合工程を共に清浄化雰囲気、 具体的には 不活性雰囲気内、 例えば A rや N 2等の酸素を含まない気相中、 又は酸素を含む 1 a t m以下の雰囲気中に保持する機能を有している。 これにより、 接合工程の 直前に A rプラズマ等を用いた清浄化工程を付加することなく、 比較的容易に理 想に極めて近い平坦化状態を維持することができ、 バンプと電極の確実な接合が 可能となる。 なお、 本実施形態では、 フリップチップ実装を例示したが、 本発明はこれに限 定されることなく、 半導体チップと半導体ゥエー八、 半導体チップ同士等の接合 TJP2003/005092 に利用しても好適である。 産業上の利用可能性 The semiconductor manufacturing apparatus includes a chip introducing section 81 for introducing a semiconductor chip having bumps formed on the surface thereof, and a circuit board introducing section 82 for introducing a circuit board having electrodes formed on the surface thereof. A cutting section 83 for performing a step of flattening the bump surface of the semiconductor chip by cutting using the above-mentioned bytes, and a step of joining the semiconductor chip and the circuit board with the flattened bumps and electrodes. And an unloading unit 85 for unloading the bonded and integrated semiconductor device. In addition, the cutting unit 83 and the bonding unit 84 are connected to an inert atmosphere. It is configured to have a cleaning holding section 86 encompassed by the above. Here, in the cutting portion 83, not only the semiconductor chip but also the electrode surface of the circuit board may be similarly flattened by cutting. Cleaning holder 8 6, the flattening step and the bonding step together cleaning atmosphere, in particular including an inert atmosphere, for example in the gas phase which does not contain oxygen, such as A r and N 2, or an oxygen 1 It has the function of keeping the atmosphere below atm. This makes it possible to maintain a flattened state, which is very close to the ideal, relatively easily, without adding a cleaning step using Ar plasma or the like immediately before the bonding step. Is possible. In this embodiment, the flip chip mounting is exemplified. However, the present invention is not limited to this, and the bonding between the semiconductor chip and the semiconductor chip, the bonding between the semiconductor chips, and the like are not limited to this. It is also suitable for use in TJP2003 / 005092. Industrial applicability
本発明によれば、 CMPに替わり、 基板上に形成された微細なバンプの表面を 安価に高速で平坦化し、 バンプ同士の接続を、 デイツシング等の不都合を発生さ せることなく容易且つ確実に行うことが可能となる。  According to the present invention, in place of CMP, the surface of fine bumps formed on a substrate is flattened at low cost and at high speed, and bumps are easily and reliably connected without causing inconvenience such as dicing. It becomes possible.

Claims

請 求 の 範 囲 The scope of the claims
1 -基板の表面に外部と電気的接続を行うためのバンプを形成する方法であって、 前記基板の表面に、 複数の前記バンプ及ぴ前記バンプ間に絶縁膜を形成するェ 程と、 1-A method of forming a bump for making an electrical connection with the outside on a surface of a substrate, comprising: forming a plurality of the bumps and an insulating film between the bumps on the surface of the substrate;
バイ トを用いた切削加工により、 前記各バンプの表面及び前記絶縁膜の表面が 連続して平坦となるように平坦化処理する工程と、  A step of performing a flattening process by cutting using a byte so that the surface of each of the bumps and the surface of the insulating film are continuously flat;
前記絶縁膜を除去する工程と  Removing the insulating film;
を含むことを特徴とするバンプの形成方法。  A method for forming a bump, comprising:
2 . 前記バンプを形成するに際して、  2. When forming the bump,
前記絶縁膜を加工して電極形状の複数の開口を有するマスクを形成した後、 前 記マスクの前記各開口を導電材料で埋め込むことを特徴とする請求項 1に記載の バンプの形成方法。  2. The bump forming method according to claim 1, wherein, after processing the insulating film to form a mask having a plurality of electrode-shaped openings, the openings of the mask are filled with a conductive material.
3 . メツキ法により、 前記マスクの前記各開口を前記導電材料で埋め込むことを 特徴とする請求項 2に記載のバンプの形成方法。  3. The method for forming a bump according to claim 2, wherein each of the openings of the mask is filled with the conductive material by a plating method.
4 . 前記バンプをニッケル系無電解メツキ法により形成し、  4. The bump is formed by a nickel-based electroless plating method,
前記バンプの表面を前記切削加工する際に、 前記バンプに表層に生成された高 リン濃度の層を除去することを特徴とする請求項 1に記載のバンプの形成方法。 2. The bump forming method according to claim 1, wherein, when the surface of the bump is cut, a layer having a high phosphorus concentration generated in a surface layer of the bump is removed.
5 . 前記バンプをニッケル系無電解メツキ法により形成した後、 前記バンプを覆 うように前記絶縁膜を形成することを特徴とする請求項 4に記載のバンプの形成 方法。 5. The bump forming method according to claim 4, wherein, after forming the bump by a nickel-based electroless plating method, the insulating film is formed so as to cover the bump.
6 . 前記基板には L S I素子が設けられており、 前記バンプが前記 L S I素子と 接続されていることを特徴とする請求項 1に記載のバンプの形成方法。  6. The bump forming method according to claim 1, wherein an LSI element is provided on the substrate, and the bump is connected to the LSI element.
7 . 前記棊板上で同一の高さとなるように、 前記バンプの表面を前記切削加工す ることを特徴とする請求項 1に記載のバンプの形成方法。  7. The bump forming method according to claim 1, wherein the surface of the bump is cut so as to have the same height on the slab.
8 . 前記基板の表面を基準として、 前記基板の裏面を機械加工により平坦化処理 する工程を更に含み、  8. The method further includes flattening the back surface of the substrate by machining with reference to the front surface of the substrate,
前記基板の前記裏面を基準として、 前記バンプの表面及び前記絶縁膜の表面の 前記平坦化処理を行うことを特徴とする請求項 7に記載のバンプの形成方法。 8. The bump forming method according to claim 7, wherein the flattening process is performed on a surface of the bump and a surface of the insulating film with reference to the back surface of the substrate.
9 . 複数の前記基板に前記各工程を実行し、 前記各基板の厚みを同一に均一化す ることを特徴とする請求項 8に記載のバンプの形成方法。 9. The bump forming method according to claim 8, wherein the steps are performed on a plurality of the substrates, and the thicknesses of the respective substrates are made uniform.
1 0 . 前記バンプの表面及び前記絶縁膜の表面を平坦化処理するに際して、 前記裏面を基準に前記半導体基板の平行出しを行うとともに、 前記表面の位置 を検出し、 検出された前記表面から.削り量を算出して制御することを特徴とする 請求項 8に記載のバンプの形成方法。  10.When flattening the surface of the bump and the surface of the insulating film, the semiconductor substrate is parallelized with reference to the back surface, the position of the front surface is detected, and from the detected front surface. 9. The bump forming method according to claim 8, wherein the amount of shaving is calculated and controlled.
1 1 . 前記基板の前記表面の位置を検出する際に、 前記表面の周辺部位の複数箇 所における絶縁膜にレーザ光を照射して絶縁物を加熱飛散させ、 前記表面の一部 を露出させることを特徴とする請求項 1 0に記載のバンプの形成方法。  1 1. When detecting the position of the surface of the substrate, the insulating film is irradiated with laser light at a plurality of locations around the surface of the substrate to heat and scatter the insulator, thereby exposing a part of the surface. The method for forming a bump according to claim 10, wherein:
1 2 . 前記基板の前記表面の位置を検出する際に、 前記裏面に赤外レーザ光を照 射し、 前記表面からの反射光を測定することを特徴とする請求項 1 0に記載の配 線の形成方法。  12. The arrangement according to claim 10, wherein when detecting the position of the front surface of the substrate, the back surface is irradiated with infrared laser light, and reflected light from the front surface is measured. The method of forming the line.
1 3 . それぞれ、 外部と電気的接続を行うための複数のバンプが表面に形成され てなる一対の半導体基板を有しており、  1 3. Each of them has a pair of semiconductor substrates having a plurality of bumps formed on the surface for electrical connection with the outside,
前記各バンプの表面が前記各半導体基板上で連続して均一に平坦化されており、 前記各半導体基板は、 前記各バンプの平坦化された前記表面同士を対向させて 接続し、 一体化してなることを特徴とする半導体装置。  The surface of each of the bumps is continuously and uniformly flattened on each of the semiconductor substrates, and each of the semiconductor substrates is connected such that the flattened surfaces of each of the bumps face each other, are connected, and are integrated. A semiconductor device, comprising:
1 4 . 前記各半導体基板にはそれぞれ L S I素子が設けられており、 前記各半導 体基板上で前記各バンプが前記各 L S I素子と接続されていることを特徴とする 請求項 1 3に記載の半導体装置。  14. The semiconductor device according to claim 13, wherein each of the semiconductor substrates is provided with an LSI element, and each of the bumps is connected to each of the LSI elements on each of the semiconductor substrates. Semiconductor device.
1 5 . 前記各バンプは、 前記各半導体基板上で同一の高さとされてなることを特 徵とする請求項 1 3に記載の半導体装置。  15. The semiconductor device according to claim 13, wherein each of the bumps has the same height on each of the semiconductor substrates.
1 6 . 前記各半導体基板は、 その裏面側に前記表面を基準とした機械加工が施さ れ、 前記裏面の平坦化及び基板厚の均一化がなされていることを特徴とする請求 項 1 5に記載の半導体装置。  16. The semiconductor substrate according to claim 15, wherein the back surface of each of the semiconductor substrates is subjected to machining based on the front surface, and the back surface is flattened and the substrate thickness is made uniform. 13. The semiconductor device according to claim 1.
1 7 . —対の半導体基板の各表面に、 絶縁膜内に埋め込まれるように各バンプを 形成する工程と、  17. Forming a bump on each surface of the pair of semiconductor substrates so as to be embedded in the insulating film;
バイ トを用いた切削加工により、 前記各バンプの表面及び前記絶縁膜の表面が 連続して平坦となるように平坦化処理する工程と、 前記絶縁膜を除去する工程と、 A step of performing a flattening process by cutting using a byte so that the surface of each of the bumps and the surface of the insulating film are continuously flat; Removing the insulating film;
前記各半導体基板を、 前記各バンプの平坦化された前記表面同士を対向させて 接続し、 一体化する工程と  Connecting and integrating the semiconductor substrates with the flattened surfaces of the bumps facing each other,
を含むことを特徴とする半導体装置の製造方法。  A method for manufacturing a semiconductor device, comprising:
1 8 . 前記各半導体基板にはそれぞれ L S I素子が設けられており、 前記各半導 体基板上で前記各バンプが前記各 L S I素子と接続されていることを特徴とする 請求項 1 7に記載の半導体装置の製造方法。  18. The semiconductor device according to claim 17, wherein each of the semiconductor substrates is provided with an LSI element, and each of the bumps is connected to each of the LSI elements on each of the semiconductor substrates. Manufacturing method of a semiconductor device.
1 9 . 前記基板の表面を基準として、 前記基板の裏面を機械加工により平坦化処 理する工程を更に含み、  19. The method further includes a step of flattening the back surface of the substrate by machining with reference to the front surface of the substrate,
前記各半導体基板の前記裏面を基準として、 前記バンプの表面及び前記絶縁膜 の表面の前記平坦化処理を行うことを特徴とする請求項 1 7に記載の半導体装置 の製造方法。  18. The method according to claim 17, wherein the flattening process is performed on the surface of the bump and the surface of the insulating film with reference to the back surface of each semiconductor substrate.
2 0 . 基板の表面に外部と電気的接続を行うためのバンプを形成する方法であつ て、  20. A method for forming a bump on the surface of a substrate for making an electrical connection with the outside,
前記基板の表面に、 複数の前記バンプを形成する工程と、  Forming a plurality of the bumps on the surface of the substrate;
バイ トを用いた切削加工により、 前記複数のバンプの表面が連続して平坦とな るように平坦化処理する工程と  A step of performing a flattening process by cutting using a byte so that the surfaces of the plurality of bumps are continuously flat.
を含むことを特徴とするバンプの形成方法。  A method for forming a bump, comprising:
2 1 . —対の半導体チップの各表面に、 それぞれ複数の前記バンプを形成するェ 程と、  21. forming a plurality of the bumps on each surface of the pair of semiconductor chips;
バイ トを用いた切削加工により、 前記複数のバンプの表面が連続して平坦とな るように平坦化処理する工程と、  A step of performing a flattening process by cutting using a byte so that the surfaces of the plurality of bumps are continuously flattened;
前記複数のバンプの表面が平坦化された前記一対の半導体チップを、 前記各バ ンプ同士が対向するように接続して一体化する工程と  A step of connecting and integrating the pair of semiconductor chips in which the surfaces of the plurality of bumps are flattened so that the bumps face each other;
を含むことを特徴とする半導体装置の製造方法。  A method for manufacturing a semiconductor device, comprising:
2 2 . 前記一対の半導体チップの各表面を基準として、 各裏面を機械加工により 平坦化処理する工程を更に含み、  22. The method further includes flattening each back surface by machining with reference to each front surface of the pair of semiconductor chips,
前記裏面を基準として、 前記切削加工により前記バンプの表面の前記平坦化処 理を行うことを特徴とする請求項 2 1に記載の半導体装置の製造方法。 22. The method for manufacturing a semiconductor device according to claim 21, wherein the flattening process of the front surface of the bump is performed by the cutting with reference to the back surface.
2 3 . 前記バンプを形成した後、 前記バンプを覆うように樹脂膜を形成し、 前記 切削加工により、 前記各バンプの表面及び前記樹脂膜の表面が連続して平坦とな るように平坦化処理することを特徴とする請求項 2 1に記載の半導体装置の製造 方法。 23. After the formation of the bumps, a resin film is formed so as to cover the bumps, and the surface of each of the bumps and the surface of the resin film are planarized by the cutting process so as to be continuously flat. 22. The method for manufacturing a semiconductor device according to claim 21, wherein the method is performed.
2 4 . それぞれ、 外部と電気的接続を行うための複数のバンプが表面に形成され てなる一対の半導体チップを有しており、  24. Each has a pair of semiconductor chips having a plurality of bumps formed on the surface for electrical connection with the outside,
前記各バンプの表面が前記各半導体チップ上で連続して均一に平坦化されてお り、 '  The surface of each of the bumps is continuously and uniformly planarized on each of the semiconductor chips.
前記各半導体チップは、 前記各バンプの平坦化された前記表面同士を対向させ て接続し、 一体化してなることを特徴とする半導体装置。  The semiconductor device, wherein each of the semiconductor chips is integrated by connecting and connecting the flattened surfaces of the bumps to each other.
2 5 . 前記各半導体チップは、 その裏面側に前記表面を基準とした機械加工が施 され、 前記裏面の平坦化及び基板厚の均一化がなされていることを特徴とする請 求項 2 4に記載の半導体装置。  25. A claim according to claim 24, wherein each of the semiconductor chips is machined on the back surface side with reference to the front surface, and the back surface is flattened and the substrate thickness is made uniform. 3. The semiconductor device according to claim 1.
2 6 . 前記バンプを覆うように樹脂膜が形成されており、 前記各バンプの表面及 び前記樹脂膜の表面が連続して均一に平坦化されていることを特徴とする請求項 2 に記載の半導体装置。  26. The resin film according to claim 2, wherein a resin film is formed so as to cover the bump, and a surface of each of the bumps and a surface of the resin film are continuously and uniformly flattened. Semiconductor device.
2 7 . 半導体基板の表面に外部と電気的接続を行うためのバンプであり、 ワイヤ ボンディング法を用いたス夕ッ ドバンプを形成する方法であって、  27. A bump for making electrical connection to the outside on the surface of the semiconductor substrate, and a method for forming a solid bump using a wire bonding method.
前記半導体基板の表面の電気的接続箇所にボンディングワイヤを用いて複数の 突起部を形成する工程と、  Forming a plurality of protruding portions using bonding wires at electrical connection points on the surface of the semiconductor substrate;
バイ トを用いた切削加工により、 前記複数の突起部の上面が連続して平坦とな るように平坦化処理し、 前記ス夕ッドバンプを形成する工程と  A step of performing a flattening process by cutting using a byte so that upper surfaces of the plurality of protrusions are continuously flattened, and forming the smooth bumps;
を含むことを特徴とするバンプの形成方法。  A method for forming a bump, comprising:
2 8 . レーザ発信器及び検出器を備えた検出装置を用い、 前記切削加工後の前 記突起部の前記上面にレーザビームを操引し、前記上面にて反射したレーザ光 を前記検出器により検出する方法により、検出されたレーザ光の強度が全ての 前記突起部について所定値に達するまで、前記切削加工を繰り返し実行するこ とを特徴とする請求項 2 7に記載のバンプの形成方法。  28. Using a detector equipped with a laser transmitter and a detector, a laser beam is steered to the upper surface of the protrusion after the cutting, and the laser beam reflected on the upper surface is detected by the detector. 28. The bump forming method according to claim 27, wherein the cutting process is repeatedly performed until the intensity of the detected laser beam reaches a predetermined value for all of the protrusions by a detection method.
2 9 . 前記検出器を前記バイ トの進行方向の後方に設置し、 前記バイ 卜の動作 と同期するように前記検出器を移動させることを特徴とする請求項 2 8 に記 載のバンプの形成方法。 29. Install the detector behind the direction of travel of the byte and operate the byte. 29. The bump forming method according to claim 28, wherein the detector is moved so as to synchronize with the bump.
3 0 . 前記複数の突起部を覆うように保護膜を形成する工程と、  30. a step of forming a protective film so as to cover the plurality of protrusions;
前記切削加工により、 前記複数の突起部の上面及び前記保護膜の表面が連続 して平坦となるように平坦化処理した後、 前記保護膜を除去する工程と  Removing the protective film after performing a flattening process by the cutting process so that the upper surfaces of the plurality of protrusions and the surface of the protective film are continuously flat.
を更に含むことを特徴とする請求項 2 7に記載のバンプの形成方法。  28. The method for forming a bump according to claim 27, further comprising:
3 1 . 外部と電気的接続を行うためのバンプであり、 ワイヤボンディング法を用 いた複数のス夕ッドバンプが表面に形成されてなる半導体チップを有しており、 前記各スタツドバンプの上面が前記半導体チップ上で連続して均一に平坦化さ れてなることを特徵とする半導体装置。  3 1. A bump for making an electrical connection to the outside, comprising a semiconductor chip having a plurality of solid bumps formed on the surface using a wire bonding method, wherein the upper surface of each of the stud bumps is A semiconductor device characterized by being continuously and uniformly planarized on a semiconductor chip.
3 2 . 半導体基板の表面に複数のバンプを形成する工程と、  3 2. Forming a plurality of bumps on the surface of the semiconductor substrate;
バイ トを用いた切削加工により、 前記複数のバンプの表面が連続して平坦とな るように平坦化処理する工程と、  A step of performing a flattening process by cutting using a byte so that the surfaces of the plurality of bumps are continuously flattened;
前記複数のバンプの表面が平坦化された前記半導体基板から、 各半導体チップ を切り出す工程と、  Cutting out each semiconductor chip from the semiconductor substrate in which the surfaces of the plurality of bumps are flattened;
前記半導体チップの前記バンプとリ一ド端子の一端部とを接続する工程と を含むことを特徴とする半導体装置の製造方法。  Connecting the bump of the semiconductor chip to one end of a lead terminal.
3 3 . 前記半導体基板の表面を基準として、 裏面を機械加工により平坦化処理す る工程を更に含み、  33. The method further includes a step of flattening the back surface by machining with reference to the front surface of the semiconductor substrate,
前記裏面を基準として、 前記切削加工により前記バンプの表面の前記平坦化処 理を行うことを特徴とする請求項 3 2に記載の半導体装置の製造方法。  33. The method for manufacturing a semiconductor device according to claim 32, wherein the flattening process of the front surface of the bump is performed by the cutting with reference to the back surface.
3 4 . 半導体基板の表面の電気的接続箇所にワイヤボンディング法を用いた複数 の突起部を形成する工程と、  34. A step of forming a plurality of projections using a wire bonding method at electrical connection points on the surface of the semiconductor substrate;
バ.ィトを用いた切削加工により、 前記複数の突起部の上面が連続して平坦とな るように平坦化処理し、 スタツ ドバンプを形成する工程と、  Forming a stud bump by performing a flattening process by cutting using a byte so that the upper surfaces of the plurality of protrusions are continuously flat.
複数のスタツドバンプの形成され.た前記半導体基板から、 各半導体チップを切 り出す工程と、  Cutting each semiconductor chip from the semiconductor substrate on which a plurality of stud bumps are formed;
前記半導体チップの前記スタツ ドバンプとリード端子の一端部とを接続するェ 程と を含むことを特徴とする半導体装置の製造方法。 Connecting the stud bump of the semiconductor chip to one end of a lead terminal; A method for manufacturing a semiconductor device, comprising:
3 5 . 前記半導体基板の表面を基準として、 裏面を機械加工により平坦化処理す る工程を更に含み、  35. The method further includes a step of flattening the back surface by machining with reference to the front surface of the semiconductor substrate,
前記裏面を基準として、 前記切削加工により前記バンプの表面の前記平坦化処 理を行うことを特徴とする請求項 3 4に記載の半導体装置の製造方法。  35. The method for manufacturing a semiconductor device according to claim 34, wherein the flattening process of the front surface of the bump is performed by the cutting with reference to the back surface.
3 6 . 前記バンプの表面を平坦化した後、 前記リード端子と接続する前に、 前記 バンプの表面に試験用針を接触させて検査を行う工程を更に有することを特徴と する請求項 3 4に記載の半導体装置の製造方法。 36. The method according to claim 34, further comprising, after flattening the surface of the bump and before connecting to the lead terminal, performing an inspection by bringing a test needle into contact with the surface of the bump. 13. The method for manufacturing a semiconductor device according to item 5.
3 7 . 外部と電気的接続を行うための複数のバンプが表面に形成されてなる半導 体チップを有しており、  37. A semiconductor chip having a plurality of bumps formed on the surface for electrical connection with the outside,
前記各バンプの表面が前記半導体チップ上で連続して均一に平坦化されており、 前記半導体チップの前記バンプとリ一ド端子の一端部とが接続され、 一体化し てなることを特徴とする半導体装置。  The surface of each of the bumps is continuously and uniformly flattened on the semiconductor chip, and the bump of the semiconductor chip and one end of a lead terminal are connected and integrated. Semiconductor device.
3 8 . 前記バンプが金からなるとともに、 前記リード端子の前記一端部に金又は 錫の表面処理が施されていることを特徴とする請求項 3 7に記載の半導体装置。 38. The semiconductor device according to claim 37, wherein the bump is made of gold, and the one end of the lead terminal is subjected to a surface treatment of gold or tin.
3 9 . 外部と電気的接続を行うための複数のバンプであり、 ワイヤボンディング 法を用いた複数のスタツ ドバンプが表面に形成されてなる半導体チップを有して おり、 39. A plurality of bumps for making an electrical connection with the outside, and a semiconductor chip having a plurality of stud bumps formed on the surface using a wire bonding method.
前記各スタツ ドバンプの表面が前記半導体チップ上で連続して均一に平坦化さ れており、  The surface of each of the stud bumps is continuously and uniformly flattened on the semiconductor chip,
前記半導体チップの前記スタツドバンプとリ一ド端子の一端部とが接続され、 一体化してなることを特徴とする半導体装置。  A semiconductor device, wherein the stud bump of the semiconductor chip and one end of a lead terminal are connected and integrated.
4 0 . 前記スタッドバンプが金からなるとともに、 前記リード端子の前記一端部 に金又は錫の表面処理が施されていることを特徴とする請求項 3 9に記載の半導 体装置。  40. The semiconductor device according to claim 39, wherein the stud bump is made of gold, and the one end of the lead terminal is subjected to a surface treatment of gold or tin.
4 1 . 表面に複数の電極が形成された半導体チップを不活性雰囲気内に導入し、 バイ トを用いた切削加工により、 前記複数の電極の表面が連続して平坦となるよ うに平坦化処理する工程と、  4 1. A semiconductor chip having a plurality of electrodes formed on its surface is introduced into an inert atmosphere, and a cutting process using a byte is performed so that the surfaces of the plurality of electrodes are continuously flattened. The process of
平坦化された前記複数の電極の表面が前記不活性雰囲気内で清浄に保たれた状 態で、 前記半導体チップの前記複数の電極と回路基板とを接続し、 一体化するェ 程と A state where the surfaces of the flattened electrodes are kept clean in the inert atmosphere. Connecting the plurality of electrodes of the semiconductor chip to a circuit board and integrating them.
を含むことを特徴とする半導体装置の製造方法。  A method for manufacturing a semiconductor device, comprising:
4 2 . 前記回路基板上に形成された複数の電極は、 バイ トを用いた切削加工によ り表面が連続して平坦となるように平坦化処理されており、  42. The plurality of electrodes formed on the circuit board are flattened by cutting using a byte so that the surface is continuously flat.
前記半導体チップと回路基板とを、前記電極表面同士が対向するように接続し、 一体化することを特徴とする請求項 4 1に記載の半導体装置の製造方法。  42. The method of manufacturing a semiconductor device according to claim 41, wherein the semiconductor chip and the circuit board are connected and integrated such that the electrode surfaces face each other.
4 3 . バイ トを有する切削加工手段と、 4 3. Cutting means having bytes,
導入された一対の基体を接合させる接合手段と、  Joining means for joining the introduced pair of substrates,
前記切削加工手段及び前記接合手段の環境を不活性雰囲気の状態に保つ不活性 雰囲気手段と  An inert atmosphere means for maintaining an environment of the cutting means and the joining means in an inert atmosphere state;
を含み、  Including
前記切削加工手段は、 前記不活性雰囲気内において、 表面に複数の電極が形成 された前記一対の基体の少なくとも一方に対して、 前記バイ トを用いた切削加工 により、 前記複数の電極の表面が連続して平坦となるように平坦化処理する機能 を有し、  In the inert atmosphere, at least one of the pair of bases having a plurality of electrodes formed on the surface thereof is cut using the byte in the inert atmosphere. It has the function of flattening so that it is continuously flat,
前記接合手段は、 平坦化された前記複数の電極の表面が前記不活性雰囲気内で 清浄に保たれた状態で、 前記一対の基体を前記複数の電極で接続し、 一体化する 機能を有することを特徴とする半導体製造装置。  The bonding means has a function of connecting and unifying the pair of substrates with the plurality of electrodes while the flattened surfaces of the plurality of electrodes are kept clean in the inert atmosphere. A semiconductor manufacturing apparatus characterized by the above-mentioned.
4 4 . 基板の表面に外部と電気的接続を行うためのバンプを形成する際の基板処 理装置であって、  4 4. A substrate processing apparatus for forming a bump on the surface of a substrate for making an electrical connection to the outside,
平坦な支持面を有しており、 基板をその一面で前記支持面に吸着させ、 前記一 面を強制的に平坦な基準面として支持固定する基板支持台と、  A substrate support having a flat support surface, adsorbing the substrate to the support surface on one side thereof, and forcibly supporting and fixing the one side as a flat reference surface;
前記基板の他面を切削加工するパイ 卜と  A pipe for cutting the other surface of the substrate;
を含み、  Including
表面に複数の前記バンプ及び前記バンプ間に絶縁膜が形成されてなる基板を前 記基板支持台に支持固定し、 前記バイ トを用いた切削加工により、 前記各バンプ の表面及び前記絶縁膜の表面が連続して平坦となるように平坦化処理することを 特徴とする基板処理装置。 A substrate having a plurality of bumps on the surface and an insulating film formed between the bumps is supported and fixed to the substrate support, and the surface of each bump and the insulating film are cut by using the bytes. A substrate processing apparatus for performing a flattening process so that a surface is continuously flattened.
4 5 . 前記基板支持台により前記基板の表面を基準面として、 前記バイ トにより 前記基板の裏面を切削加工した後、 前記基板支持台により前記基板の前記裏面を 基準面として、 前記バイ トにより前記基板の前記表面を切削加工し、 前記各バン プの表面及び絶縁膜の表面が連続して平坦となるように平坦化処理することを特 徵とする請求項 4 4に記載の基板処理装置。 45. After the back surface of the substrate is cut by the bytes with the substrate as a reference surface using the substrate support base, the back surface of the substrate is set as the reference surface with the bytes by the substrate support base. The substrate processing apparatus according to claim 44, wherein the surface of the substrate is cut and flattened so that the surface of each bump and the surface of the insulating film are continuously flat. .
4 6 . 前記裏面を基準に前記半導体基板の平行出しを行うとともに、 前記配線形 成面の位置を検出し、 検出された前記配線形成面から削り量を算出して制御する ことを特徴とする請求項 4 4に記載の基板処理装置。  46. Parallelizing the semiconductor substrate with reference to the back surface, detecting the position of the wiring forming surface, and calculating and controlling the amount of shaving from the detected wiring forming surface. The substrate processing apparatus according to claim 44.
4 7 . 前記配線形成面の位置を検出する際に、 前記配線形成面の周辺部位の複数 箇所における絶縁膜にレーザ光を照射して絶縁物を加熱飛散させ、 前記配線形成 面の一部を露出させることを特徴とする請求項 4 6に記載の基板処理装置。  47. When detecting the position of the wiring formation surface, the insulating film is irradiated with laser light at a plurality of locations around the wiring formation surface to heat and scatter the insulator, and a part of the wiring formation surface is removed. 47. The substrate processing apparatus according to claim 46, wherein the substrate processing apparatus is exposed.
4 8 .前記配線形成面の位置を検出する際に、前記裏面に赤外レーザ光を照射し、 前記配線形成面からの反射光を測定することを特徴とする請求項 4 6に記載の基 板処理装置。 48. The base according to claim 46, wherein when detecting the position of the wiring forming surface, the back surface is irradiated with infrared laser light, and reflected light from the wiring forming surface is measured. Plate processing equipment.
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JP2009094545A (en) 2009-04-30
CN1685489A (en) 2005-10-19
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JP4785937B2 (en) 2011-10-05
CN102044413B (en) 2012-11-21
CN100477139C (en) 2009-04-08

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