CN100477139C - Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus and semiconductor manufacturing apparatus - Google Patents

Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus and semiconductor manufacturing apparatus Download PDF

Info

Publication number
CN100477139C
CN100477139C CNB038227576A CN03822757A CN100477139C CN 100477139 C CN100477139 C CN 100477139C CN B038227576 A CNB038227576 A CN B038227576A CN 03822757 A CN03822757 A CN 03822757A CN 100477139 C CN100477139 C CN 100477139C
Authority
CN
China
Prior art keywords
mentioned
projection
substrate
cut
semiconductor substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB038227576A
Other languages
Chinese (zh)
Other versions
CN1685489A (en
Inventor
水越正孝
石月义克
中川香苗
冈本圭史郎
手代木和雄
酒井泰治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of CN1685489A publication Critical patent/CN1685489A/en
Application granted granted Critical
Publication of CN100477139C publication Critical patent/CN100477139C/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1183—Reworking, e.g. shaping
    • H01L2224/1184—Reworking, e.g. shaping involving a mechanical process, e.g. planarising the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/4501—Shape
    • H01L2224/45012—Cross-sectional shape
    • H01L2224/45015—Cross-sectional shape being circular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/741—Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L2224/749—Tools for reworking, e.g. for shaping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/75252—Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L24/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01011—Sodium [Na]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01018—Argon [Ar]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01019—Potassium [K]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01023—Vanadium [V]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0103—Zinc [Zn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01039—Yttrium [Y]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0105—Tin [Sn]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3025—Electromagnetic shielding

Abstract

The rear (1b) of a semiconductor substrate (1) is fixed to the support face (11a) of a substrate support base (11) by vacuum clamping. The thickness of the semiconductor substrate (1) is uniform by planarizing the rear (1b), and the rear (1b) is forcedly free of waviness caused by the vacuum clamping to the support face (11a), so that the rear (1b) functions as the reference face of the planarization of the front (1a). In this state, Au projections (2) on the front (1a) and the surface layer of a resist mask (12) is cut with a single point tool (10) to planarize the surface of Au projections (2) and that of the resist mask (12) so as to be flat continuously. Thus, instead of CMP, the surface of a fine bump formed on a substrate is planarized at low cost low costly and speedily.

Description

Projection formation method, semiconductor device and manufacture method thereof, substrate board treatment and semiconductor-fabricating device
Technical field
The present invention relates on the surface of substrate, to be formed for method, semiconductor device and manufacture method thereof, substrate board treatment and semiconductor-fabricating device with the outside fine projection that is electrically connected.
Background technology
In the prior art, the fine metal terminal that is used to carry out being connected with external electric on the surface of semiconductor substrate has used gold (Au) projection etc.This Au projection forms with electroplating, and the roughness on surface is big.For the such metal terminal of leveling, use chemico-mechanical polishing (Chemical Mechanical Polishing:CMP) method.This method is to be pre-formed more smooth metal that becomes machined surface and resin, contact smooth polishing pad after, use the mechanically smooth exquisitely finished surface in slip (chemical polishing material) chemical ground.Animi resin that sets in advance or metal covering become prevents layer, thereby finishes CMP.The CMP method is the method that does not exist with ... TTV (Total Thickness Variation), and this TTV is defined by the thickness deviation of semiconductor substrate or the maximum ga(u)ge of semiconductor substrate and the difference of minimum thickness.
In addition, engage the big Au projection of existing surface roughness etc., just need utilize load, heat or ultrasonic wave etc. to give the installation method that load disappears up to its roughness projection.
Except CMP, the leveling method of cutting tools (for example, open with reference to Japanese patent laid-open 7-326614 communique, spy flat 8-11049 communique, spy are opened flat 9-82616 communique, the spy opens the 2000-173954 communique) has for example been proposed also to use.But, all be the smooth object that turns to the sog film of the subregion on the LSI, be with CMP be the method that benchmark cuts similarly to be cut face, do not exist with ... the TTV of semiconductor substrate.In addition, the method (opening 2000-173954 (special hope flat 10-345201 number) number communique) that the cutting projection is also arranged and the surface is exposed with reference to the Japan Patent spy, but this is to be formed on the smooth object that turns to of the projection part on the LSI, to be cut face is the method that benchmark cuts, and does not exist with ... the TTV of semiconductor substrate.
As mentioned above, the Au projection has been used in fine connection, but because the roughness of lug surface is big, therefore, it is very difficult each other to engage these projections.In addition, under the situation of using metal such as CMP leveling simultaneously Au and resin, owing to the difference of the polishing velocity of metal and resin causes the hollow that recess (dishing) occur being known as.Because this recessed shaping in order to obtain bump bond accurately, just need be given the big load of load, heat or ultrasonic wave etc. to projection.
Summary of the invention
The present invention forms in view of above-mentioned problem, its purpose is to provide a kind of can replace CMP, cheap and at high speed leveling is carried out on the surface that is formed on the fine bump on the substrate, and do not produce the unfavorable condition of recess etc., can be easily and carry out semiconductor device and the manufacture method and the semiconductor-fabricating device of the projection formation method and the high reliability of projection connection each other exactly.
Projection formation method of the present invention is formed for carrying out the projection that is connected with external electric on the surface of substrate, it is characterized in that comprising: on the surface of aforesaid substrate, form the operation of dielectric film between a plurality of above-mentioned projections and above-mentioned projection; Carry out planarizing process by the cut of using cutter, make the surface of above-mentioned each projection and the surperficial continuous and smooth operation of above-mentioned dielectric film; Remove the operation of above-mentioned dielectric film.
Semiconductor device of the present invention: have a pair of semiconductor substrate, it is formed for respectively constituting with the outside a plurality of projections that are electrically connected from the teeth outwards; The surface of above-mentioned each projection of leveling continuously and equably on above-mentioned each semiconductor substrate; The above-mentioned surface of being flattened that makes above-mentioned each projection is opposite to one another and connect, and integrated and constitute above-mentioned each semiconductor substrate.
The manufacture method of semiconductor device of the present invention comprises: on each surface of a pair of semiconductor substrate to be embedded to the operation that mode in the dielectric film forms each projection; Carry out planarizing process by the cut of using cutter, make the surface of above-mentioned each projection and the surperficial continuous and smooth operation of above-mentioned dielectric film; Remove the operation of above-mentioned dielectric film; Make the opposite to one another and connection in above-mentioned surface of being flattened of above-mentioned each projection, with the incorporate operation of above-mentioned each semiconductor substrate.
Projection formation method of the present invention is formed on the surface of substrate and the outside projection that is electrically connected, and comprising: the operation that forms a plurality of above-mentioned projections on the surface of aforesaid substrate; Carry out planarizing process by the cut of using cutter, make the surperficial continuous and smooth operation of above-mentioned a plurality of projections.
The manufacture method of semiconductor device of the present invention comprises: the operation that forms a plurality of above-mentioned projections on each surface of a pair of semiconductor substrate respectively; Carry out planarizing process by the cut of using cutter, make the surperficial continuous and smooth operation of above-mentioned a plurality of projections; To the above-mentioned a pair of semiconductor chip of being flattened of surface of above-mentioned a plurality of projections,, connect and incorporate operation in above-mentioned each projection mode opposite to one another.
Semiconductor device of the present invention: have a pair of semiconductor chip, it is formed for respectively constituting with the outside a plurality of projections that are electrically connected from the teeth outwards; The surface of above-mentioned each projection of leveling continuously and equably on above-mentioned each semiconductor chip; The above-mentioned surface of being flattened that makes above-mentioned each projection is opposite to one another and connect, and integrated and constitute above-mentioned each semiconductor chip.
Projection formation method of the present invention, on the surface of semiconductor substrate, form the column-like projection block that uses terminal conjunction method, this projection is used for being electrically connected with the outside, comprising: use bonding wire, electrical connection place on the surface of above-mentioned semiconductor substrate forms the operation of a plurality of juts; Carry out planarizing process by the cut of using cutter, make the top continuous and smooth of above-mentioned a plurality of juts, form the operation of above-mentioned column-like projection block.
Semiconductor device of the present invention has a plurality of column-like projection blocks that form the use terminal conjunction method from the teeth outwards and the semiconductor chip that constitutes, and this projection is used for being electrically connected with the outside; On above-mentioned semiconductor chip, make above-mentioned each leveling equably continuously above the column-like projection block.
The manufacture method of semiconductor device of the present invention comprises: the operation that forms a plurality of projections on the surface of semiconductor substrate; Carry out planarizing process by the cut of using cutter, make the surperficial continuous and smooth operation of above-mentioned a plurality of projections; Cut out the operation of each semiconductor chip from the above-mentioned semiconductor substrate of being flattened of surface of above-mentioned a plurality of projections; The operation that connects an end of the above-mentioned projection of above-mentioned semiconductor chip and conductor terminal.
The manufacture method of semiconductor device of the present invention comprises: the operation that forms a plurality of juts that use terminal conjunction method in electrical connection place on the surface of semiconductor substrate; Carry out planarizing process by the cut of using cutter, make the top continuous and smooth of above-mentioned a plurality of juts, form the operation of column-like projection block; From having formed the above-mentioned semiconductor substrate of a plurality of column-like projection blocks, cut out the operation of each semiconductor chip; The operation that connects an end of the above-mentioned column-like projection block of above-mentioned semiconductor chip and conductor terminal.
Semiconductor device of the present invention has and forms a plurality of semiconductor chips of constituting with the outside projection that is electrically connected of being used for from the teeth outwards; On above-mentioned semiconductor chip, make the surface leveling equably continuously of above-mentioned each projection; Connect an end of the above-mentioned projection of above-mentioned semiconductor chip and conductor terminal and make it integrated.
Semiconductor device of the present invention has a plurality of column-like projection blocks that form the use terminal conjunction method from the teeth outwards and the semiconductor chip that constitutes, and these a plurality of projections are used for being electrically connected with the outside; On above-mentioned semiconductor chip, make above-mentioned each leveling equably continuously above the column-like projection block; Connect an end of the above-mentioned column-like projection block of above-mentioned semiconductor chip and conductor terminal and make it integrated.
The manufacture method of semiconductor device of the present invention comprises: import the surface and go up the semiconductor chip that forms a plurality of electrodes in inert atmosphere, carry out planarizing process by the cut of using cutter, make the surperficial continuous and smooth operation of above-mentioned a plurality of electrodes; In above-mentioned inert atmosphere, keep cleanly under the state on surface of above-mentioned a plurality of electrodes of being flattened, connect above-mentioned a plurality of electrodes of above-mentioned semiconductor chip and circuit substrate and carry out incorporate operation.
Semiconductor-fabricating device of the present invention comprises: the cutting apparatus with cutter; Make the coupling device of a pair of matrix joint of importing; The environment of above-mentioned cutting apparatus and above-mentioned coupling device is remained on inert atmosphere device in the inert atmosphere state, wherein: above-mentioned cutting apparatus has following function, promptly in above-mentioned inert atmosphere, for at least one side who forms the above-mentioned a pair of matrix of a plurality of electrodes on the surface, carry out planarizing process by the cut of using above-mentioned cutter, make the surperficial continuous and smooth of above-mentioned a plurality of electrodes; Above-mentioned coupling device has following function, promptly keeps cleanly connecting above-mentioned a pair of matrix and carrying out integrated with above-mentioned a plurality of electrodes under the state on surface of above-mentioned a plurality of electrodes of being flattened in above-mentioned inert atmosphere.
Substrate board treatment of the present invention, it uses when being formed for the outside projection that is electrically connected on the surface of substrate, comprise: the substrate supporting platform, this substrate supporting platform has smooth bearing-surface, substrate is adsorbed on the above-mentioned bearing-surface with one face, supports fixing as smooth datum level an above-mentioned face forcibly; The cutter of other faces of cut aforesaid substrate, wherein: at aforesaid substrate supporting station upper support fixing base, this substrate from the teeth outwards, form dielectric film at a plurality of above-mentioned projections with between above-mentioned projection and constitute, carry out planarizing process by the cut of using above-mentioned cutter, make the surperficial continuous and smooth of the surface of above-mentioned each projection and above-mentioned dielectric film.
Projection formation method of the present invention, on the surface of substrate, form projection, this projection is used for being electrically connected with the outside, it is characterized in that comprising: the surface with aforesaid substrate is a benchmark, utilizes machining the back side of aforesaid substrate to be carried out the operation of planarizing process; On the surface of aforesaid substrate, form the operation of the dielectric film between a plurality of above-mentioned projections and the above-mentioned projection; Carry out planarizing process by the cut of using cutter, make the surface of above-mentioned each projection and the surperficial continuous and smooth operation of above-mentioned dielectric film, in this operation, the above-mentioned back side with aforesaid substrate is benchmark, and above-mentioned planarizing process is carried out on the surface of above-mentioned projection and the surface of above-mentioned dielectric film; Remove the operation of above-mentioned dielectric film.
Semiconductor device of the present invention is characterized in that having: first semiconductor substrate, and it has a plurality of first projections from the teeth outwards, and these a plurality of first projections are used for being electrically connected with the outside, and have continuous and even each smooth surface; Second semiconductor substrate, it has a plurality of second projections from the teeth outwards, these a plurality of second projections are used for being electrically connected with the outside, and have by resulting continuous and even each the smooth surface of the cut of using cutter, smooth above-mentioned each surface that makes each above-mentioned first and second projection toward each other to and connect, thereby above-mentioned first and second semiconductor substrate is integrated.
The manufacture method of semiconductor device of the present invention is characterized in that comprising: the surface with substrate is a benchmark, utilizes machining the back side of aforesaid substrate to be carried out the operation of planarizing process; On each surface of a pair of semiconductor substrate to be embedded to the operation that mode in the dielectric film forms each projection; Carry out planarizing process by the cut of using cutter, make the surface of above-mentioned each projection and the surperficial continuous and smooth operation of above-mentioned dielectric film, in this operation, the above-mentioned back side with above-mentioned half and half conductor substrate is benchmark, and above-mentioned planarizing process is carried out on the surface of above-mentioned projection and the surface of above-mentioned dielectric film; Remove the operation of above-mentioned dielectric film; The smooth above-mentioned surface that makes above-mentioned each projection toward each other to and connect, thereby with the incorporate operation of above-mentioned each semiconductor substrate.
Projection formation method of the present invention, on the surface of substrate, form projection, this projection is used for being electrically connected with the outside, it is characterized in that comprising: the surface with aforesaid substrate is a benchmark, utilizes machining the back side of aforesaid substrate to be carried out the operation of planarizing process; On the surface of aforesaid substrate, form the operation of a plurality of above-mentioned projections; Carrying out planarizing process by the cut of using cutter, make the surperficial continuous and smooth operation of above-mentioned a plurality of projections, in this operation, is benchmark with the above-mentioned back side of aforesaid substrate, and above-mentioned planarizing process is carried out on the surface of above-mentioned projection.
Semiconductor device of the present invention, have: first semiconductor chip, it has a plurality of first projections from the teeth outwards, and these a plurality of first projections are used for being electrically connected with the outside, and has by resulting continuous and even each the smooth surface of the cut of using cutter; Second semiconductor chip, it has a plurality of second projections from the teeth outwards, these a plurality of second projections are used for being electrically connected with the outside, and have by resulting continuous and even each the smooth surface of the cut of using cutter, smooth above-mentioned each surface that makes each above-mentioned first and second projection toward each other to and connect, thereby above-mentioned first and second semiconductor chip is integrated.
Projection formation method of the present invention, on the surface of semiconductor substrate, form the column-like projection block that uses terminal conjunction method, this projection is used for being electrically connected with the outside, it is characterized in that comprising: the surface with aforesaid substrate is a benchmark, utilizes machining the back side of aforesaid substrate to be carried out the operation of planarizing process; Use bonding wire, electrical connection place on the surface of above-mentioned semiconductor substrate forms the operation of a plurality of juts; Carry out planarizing process by the cut of using cutter, make the top continuous and smooth of above-mentioned a plurality of juts, form the operation of above-mentioned column-like projection block, in this operation, the above-mentioned back side with aforesaid substrate is benchmark, and above-mentioned planarizing process is carried out on the surface of above-mentioned jut.
Semiconductor device of the present invention, have: semiconductor chip, it has a plurality of column-like projection blocks from the teeth outwards, and these a plurality of column-like projection blocks are used for being electrically connected with the outside, and by using the cut of cutter, it is continuous and evenly smooth that the upper surface of jut becomes on above-mentioned semiconductor chip; Substrate, it has a plurality of electrodes from the teeth outwards, and to also being connected, above-mentioned thus semiconductor chip and aforesaid substrate constitute one relatively for the smooth above-mentioned surface of above-mentioned each column-like projection block and the surface of above-mentioned each electrode.
The manufacture method of semiconductor device of the present invention is characterized in that, comprising: the surface with above-mentioned semiconductor substrate is a benchmark, utilizes machining the back side to be carried out the operation of planarizing process; On the surface of semiconductor substrate, form the operation of a plurality of projections; Carrying out planarizing process by the cut of using cutter, make the surperficial continuous and smooth operation of above-mentioned a plurality of projections, in this operation, is benchmark with the above-mentioned back side, utilizes above-mentioned cut that above-mentioned planarizing process is carried out on the surface of above-mentioned projection; Cut out the operation of each semiconductor chip from the above-mentioned semiconductor substrate of being flattened of surface of above-mentioned a plurality of projections; The operation that connects an end of the above-mentioned projection of above-mentioned semiconductor chip and conductor terminal.
The manufacture method of semiconductor device of the present invention is characterized in that, comprising: the surface with above-mentioned semiconductor substrate is a benchmark, utilizes machining the back side to be carried out the operation of planarizing process; Forming the operation of a plurality of juts that use terminal conjunction method in electrical connection place on the surface of semiconductor substrate, in this operation, is benchmark with the above-mentioned back side, utilizes above-mentioned cut that above-mentioned planarizing process is carried out on the surface of above-mentioned projection; Carry out planarizing process by the cut of using cutter, make the top continuous and smooth of above-mentioned a plurality of juts, form the operation of column-like projection block; From having formed the above-mentioned semiconductor substrate of a plurality of column-like projection blocks, cut out the operation of each semiconductor chip; The operation that connects an end of the above-mentioned column-like projection block of above-mentioned semiconductor chip and conductor terminal.
Semiconductor device of the present invention, it is characterized in that having: semiconductor chip, it has a plurality of projections from the teeth outwards, these a plurality of projections are used for being electrically connected with the outside, and have by resulting continuous and even each the smooth surface of the cut of using cutter; Conductor terminal, it is connected with the above-mentioned projection of above-mentioned semiconductor chip with an end, and this conductor terminal and above-mentioned semiconductor chip constitute one thus.
Description of drawings
Figure 1A～Fig. 1 D illustrates general profile chart according to the projection formation method of first execution mode according to process sequence.
Fig. 2 A, Fig. 2 B illustrate general profile chart according to the projection formation method of first execution mode according to process sequence.
Fig. 3 A, Fig. 3 B illustrate to utilize cut to carry out the result's of leveling figure.
Fig. 4 A, Fig. 4 B illustrate to utilize cut to carry out the general profile chart of the concrete example of leveling.
Fig. 5 illustrates to utilize cut to carry out the general profile chart of the concrete example of leveling.
Fig. 6 is the block diagram that the structure of cutting apparatus is shown.
Fig. 7 is the summary construction diagram of cutting apparatus.
Fig. 8 is the flow chart of cut operation.
Fig. 9 A～Fig. 9 C illustrates general profile chart according to the manufacture method of the semiconductor device of second execution mode according to process sequence.
Figure 10 A～Figure 10 F illustrates general profile chart according to the projection formation method of second execution mode according to process sequence.
Figure 11 A, Figure 11 B illustrate general profile chart according to the manufacture method of the semiconductor device of the 3rd execution mode according to process sequence.
Figure 12 A～Figure 12 C illustrates general profile chart according to the manufacture method of the semiconductor device of the 3rd execution mode variation 1 according to process sequence.
Figure 13 A～Figure 13 C illustrates general profile chart according to the manufacture method of the semiconductor device of the 3rd execution mode variation 2 according to process sequence.
Figure 14 A～Figure 14 F illustrates general profile chart according to the manufacture method of the semiconductor device of the 4th execution mode according to process sequence.
Figure 15 A～Figure 15 D is the figure that illustrates according to the cutting end-point detection method of the 4th execution mode.
Figure 16 is the general profile chart of manufacture method that the semiconductor device of the 5th execution mode is shown.
Figure 17 is the general profile chart of manufacture method that the semiconductor device of the 5th execution mode is shown.
Figure 18 is the ideograph that illustrates according to the semiconductor-fabricating device of the 6th execution mode.
Embodiment
-bare bones of the present invention-
At first, describe about bare bones of the present invention.
As replacing the CMP method, cheap and leveling simultaneously at high speed is formed on the method on the surface of a plurality of fine projections on the substrate, and the inventor has expected the method for the cut of suitable use cutter.According to this cut, on semiconductor substrate, be formed with in the situation that is embedded in the projection in the dielectric film, do not resemble and exist with ... polishing velocity of metal and insulant etc. the CMP method, can be on substrate cutting metal and insulant continuously simultaneously, do not produce recess etc., make both levelings equably on the whole.Insulating material such as metal such as copper, aluminium, nickel and polyimides be can be easily with the material of Tool in Cutting.In the present invention, as the metal material and the insulating material of projection, preferably the former is a ductile metal, and the latter is the resin etc. with 200Gpa for example or its above rigidity modulus.
Under this situation, for above-mentioned cut being used in the leveling of lug surface, preferably the back side (the inside) benchmark by substrate cuts.Usually, the TTV of silicon substrate is in the scope of 1 μ m～5 μ m, and in the technology of LSI, the TTV about 5 μ m can not exert an influence to photoengraving, is considering outside the object usually.But, in the situation of cut, the value of TTV is had a significant impact.The smooth precision of cutting is not in the value of TTV or below it.Thereby, under the situation of the leveling that cut is used in semiconductor substrate, at first the TTV of substrate must be controlled at below the cutting precision of target.
The inventor is in view of above-mentioned thing, when above-mentioned cut is used in the leveling of lug surface, as the concrete practice of carrying out this leveling exactly, expected with the substrate surface being its back side of benchmark grinding, the TTV that suppresses semiconductor substrate tinily is to below the purpose cutting precision.Under this situation, more satisfactory is TTV is very little and the thickness deviation of each semiconductor substrate is suppressed to below the cutting precision.But,, just can when cutting, detect the thickness of each semiconductor substrate if can make TTV very little.Can control cutting output by the thickness that detects this each semiconductor substrate.
As projection, except utilizing galvanoplastic form, have the projection that utilizes terminal conjunction method to form (below be called column-like projection block), that is, and the spherical-shaped piece that pressure welding forms the most advanced and sophisticated fusion of bonding wire on electrode pad, and tear this lead-in wire, thus form projection.
Under the situation that forms column-like projection block, form the projection of pin shape by tearing bonding wire, so must the such projection of leveling.In the present invention, will use the planarization process of above-mentioned cut to be applicable to column-like projection block.Under this situation, the height difference of each jut when tearing lead-in wire (precuting) will as one man be carried out leveling with minimum projection, and because the high more stress that can relax more equipment of height of column-like projection block, prolong equipment life, therefore need stipulate the height of each jut.In the present invention, the height of the jut distance electrode pad of regulation when precuting is more than or equal to 2 times of diameter wire, and as the terminal point of cut, the diameter in cutting face that is made as whole column-like projection blocks is more than or equal to moment of diameter wire.Like this, compare, can make the height of the column-like projection block after the cutting leveling be located at 1.5 times or more than it, can relax stress, can prolong equipment life semiconductor element with the situation of regulation diameter wire not.
Then, control TTV as described above, utilize cut that the surface of fine projection is carried out cutting out each semiconductor chip that becomes semiconductor device from semiconductor substrate (wafer) after the leveling.Like this, make semiconductor substrate with the surface after the leveling and semiconductor chip or between semiconductor chip with projection relative to and the mode that is electrically connected engages.At this moment, because the projection of subtend is top together by leveling accurately, therefore, does not need the such HTHP of prior art etc. and engage easily.
At this, the inventor has further found out actual conditions and the state that the projection that is used for realizing exactly subtend is engaged with each other.In view of the leveling state that in above-mentioned joint, also projection is remained after just finishing cut more satisfactory, in order to keep just having finished the leveling state after the cut as far as possible, expected that purifying atmosphere specifically be to carry out the leveling operation in the inert atmosphere and engage operation.By the additional cleaning procedure that has used Ar plasma etc. before engaging operation, just can realize this point, but have the shortcoming that causes the increase of operation quantity.In the present invention, can not cause the increase of operation quantity and keep the desirable leveling state that is in close proximity to comparalive ease, can realize the joint accurately of projection.
As other modes of the present invention, the inventor is the starting point with the state of this semiconductor chip.That is, in wafer-level, the TTV of this semiconductor substrate becomes problem as described above, but about the singualtion of semiconductor chip etc., because its size is little, so the TTV in the chip area only is subjected to almost negligible the influence when cutting.
Therefore, the inventor has expected at first under the state of this semiconductor chip, by the cut of using above-mentioned projection leveling being carried out on the surface of fine bump after semiconductor substrate cuts out each semiconductor chip.Then, make projection to being electrically connected the bond semiconductor chip backward each other.Like this, the operation of control TTV can be omitted, simultaneously, the joint of projection can be easily carried out.
In addition, in the present invention, above-mentioned Machining Technology for Cutting also is applicable in the semiconductor device by so-called TAB bonding method.
Usually, TAB is connected under the situation of utilizing the plated bumps method, need be on gold-plated projection contraposition directly implement the rectangular Copper Foil lead of surface-treated of gold, and be heated to 300 ℃ or more than it, each projection pressurization 30g or carry out crimping more than it.On the other hand, utilizing under the situation of column-like projection block, the semiconductor chip that has been pre-formed column-like projection block is contacted with glass plate or metallic plate and heating, using after entirely processing the front end of column-like projection block.
Electroplate concavo-convex and surperficial distinctive metal and organic contamination are arranged on the end face.In addition, the deviation of the height of the plating in the chip also has several microns degree.Electroplate under the situation of carrying out the TAB joint on the end face at these, need high temperature and top load.If high temperature during joint is just in the connection of the lead of minuteness space, because the difference of copper and the thermal coefficient of expansion of silicon becomes big, so easy occurrence positions is offset.On the other hand, in column-like projection block, because deviation is big in the height, therefore shape also not necessarily more needs high temperature and top load, similarly, and the connection difficulty of minuteness space.
Offset when TAB is engaged is little, when needs reduce temperature, the conductor terminal of copper is contacted with projection.In the present invention,, the surface of plated bumps and column-like projection block is carried out leveling and makes every effort to realize purifying by using cutting technology by cutter, like this, temperature and load in the time of just reducing the TAB joint, no offset ground connects the lead of minuteness space.
-the specific embodiment of the present invention-
Below, based on above-mentioned bare bones, use accompanying drawing, at length describe about the specific embodiment of the present invention.
[first execution mode]
At this, as substrate, the illustration silicon semiconductor substrate is about forming on this semiconductor substrate in order to carry out that electric property is connected and the method for the projection that is provided with and the semiconductor device and the manufacture method thereof of this method of use with the outside.
(projection formation method)
Figure 1A～Fig. 1 D, Fig. 2 A, Fig. 2 B illustrate general profile chart according to the projection formation method of present embodiment according to process sequence.
At first, prepared silicon semiconductor substrate 1 forms desirable LSI semiconductor element (not shown) on the element formation position of substrate surface 1a.Below, about forming semiconductor substrate 1 each operation of explanation that forms LSI semiconductor element etc. on the position at element in this wise.
Shown in Figure 1A, common silicon semiconductor substrate is in the variable thickness sample as shown in the figure and is attended by the state of fluctuating.Therefore, as the preceding operation that is used for the surperficial 1a of semiconductor substrate 1 is implemented the cut of use cutter described later, with the 1b leveling of its back side.
Specifically, prepare the smooth substrate supporting platform (not shown) of bearing-surface, utilize and adsorb for example vacuum suction, surperficial 1a is adsorbed on this bearing-surface, and semiconductor substrate 1 is fixed on the substrate supporting platform.At this moment, surperficial 1a is smooth in order to be forced to bearing-surface absorption, and like this, surperficial 1a just becomes the datum level of the leveling of back side 1b.Under this state, machining back side 1b carries out mechanical grinding at this, and the protuberance 1c that back side 1b is removed in grinding carries out planarizing process.Under this situation, preferably utilize the cutting output of controlling back side 1b apart from the distance of surperficial 1a.Like this, shown in Figure 1B, the thickness of semiconductor substrate 1 is just certain, and specifically, TTV (maximum ga(u)ge of substrate and minimum thickness poor) just becomes setting or below it, specifically is controlled to TTV at 1 μ m or below it.
Then, shown in Fig. 1 C, take off semiconductor substrate 1 from the substrate supporting platform, apply photosensitive resin on the surperficial 1a of semiconductor substrate 1, for example photoresist utilizes photoengraving to process this photoresist, and forms the resist mask 12 of the projection figure 12a with regulation.
Then, use resist mask 12 as mask, for example utilizing, vapour deposition method forms for example copper film of metal film, formed electroplated electrode (not shown) afterwards, shown in Fig. 1 D, as seed (seed), utilize galvanoplastic to pile up gold (Au) with electroplated electrode, thereby form Au projection 2 in the mode of each projection figure 12a of imbedding resist mask 12.Have again, except Au, also can use Cu, Ag, Ni, Sn or their alloy to wait and form projection.
Then, to the cut that the surperficial 1a of semiconductor substrate 1 implements the use cutter, carry out leveling.
Specifically, shown in Fig. 2 A, utilize for example vacuum suction, back side 1b is adsorbed on the bearing-surface 11a of substrate supporting platform 11, semiconductor substrate 1 is fixed on the substrate supporting platform 11.At this moment, because to the planarizing process of Figure 1B of back side 1b, the thickness of semiconductor substrate 1 becomes certain state, in addition, back side 1b is owing to being forced to become the state that does not does not rise and fall etc. to bearing-surface 11a absorption, like this, back side 1b just becomes the datum level of the leveling of surperficial 1a.Under this state, each the Au projection 2 among the surperficial 1a and the top layer of photoresist 12 are carried out machining, use the cutter 10 that constitutes by diamond etc. to carry out cut at this, carry out planarizing process, make the surperficial continuous and smooth of each Au projection 2 and resist mask 12.Like this, just make the top smooth mirror-like that changes into of Au projection 2.
The result who there is shown the leveling that utilizes this cut in microphotograph figure and the pattern of Fig. 3 A, Fig. 3 B.
Before cut, as shown in Figure 3A, the surface of Au projection is concavo-convex, and is relative therewith, and after cut, shown in Fig. 3 B, the surface of Au projection is by leveling accurately as can be known.
Then, utilize ashing treatment etc. to remove resist mask 12.At this moment, on the surperficial 1a of semiconductor substrate 1, form projection 3, these projection 3 height homogeneous, and after each Au projection 2 of cut, shown in Fig. 2 B, upper surface 3a is by leveling similarly.Use this semiconductor substrate 1,, utilize projection 3 to be electrically connected with other semiconductor substrates 4 for example with after its chipization.
Have again, in the present embodiment, be illustrated, but be suitable for carrying out each operation of present embodiments, make the thickness homogenization of each semiconductor substrate and identical constituting in batches a plurality of semiconductor substrates about a slice semiconductor substrate.
In addition, in the leveling operation of Fig. 2 A, shown in Fig. 4 A, Fig. 4 B, be the parallel taking-up that benchmark carries out semiconductor substrate 1 with back side 1b, simultaneously, detect the position of surperficial 1a, calculate cutting output from the surperficial 1a that detects and control.
Specifically, shown in Fig. 4 A, when detecting the position of surperficial 1a, be resist mask 12 irradiating lasers 13 among local A, B of 3 places shown in Fig. 4 B, the C for example to the many places at the peripheral position of the surperficial 1a of semiconductor substrate 1, at this, its heating is dispersed, the part of surperficial 1a is exposed.
In addition, under this situation, also can be as shown in Figure 5, when detecting the position of surperficial 1a, semiconductor substrate 1 is absorbed and fixed on the substrate supporting platform 11 that forms opening 11b, to back side 1b irradiation infrared laser, for example utilize the reverberation of infrared laser analyzer 14 mensuration from opening 11b from surperficial 1a.
(structure of cutting apparatus)
The concrete apparatus structure that is used to carry out above-mentioned cut operation in this explanation.
Fig. 6 is the block diagram that the structure of cutting apparatus is shown, and Fig. 7 is same summary construction diagram.The structure of this cutting apparatus has the storage part 101 of depositing semiconductor substrate, be used for to each handling part carrying semiconductor substrate 1 handle portion 102, carry out the detecting means 103 of the location of semiconductor substrate 1, the semiconductor substrate 1 when clamping cutting chuck platform part 104, carry out the cutting portion 105 of the leveling cutting of semiconductor substrate 1, the cleaning after cutting cleaning part 106, control their control part 107 then and constitute.Chuck platform part 104 has constituted as described above places the fixedly substrate supporting platform of semiconductor substrate 1 (chuck platform) 11, and it is the cutter 10 of hard that cutting portion 105 has the cutting tools that is made of diamond etc.
Below, use Fig. 7 and Fig. 8, describe about the flow process of cut operation.
At first, the carrying hand of handle portion 102 takes out semiconductor substrates 1 from the case 111 of the storage part 101 of depositing semiconductor substrate 1.In storage part 101, elevating mechanism is arranged, be elevated to the height that the carrying hand takes out semiconductor substrate 1.Then, carrying hand vacuum suction semiconductor substrate is to detecting means 103 carryings.The carrying hand is the articulated manipulator of 3 of Θ and Z axle, can be easily to each handling part carrying.The mechanism of manipulator is not limited thereto, and also can be XY axle craspedodrome type.
In detecting means 103, utilize rotation platform 112 to make 360 ° of semiconductor substrate 1 rotations, with the periphery of CCD camera 111 these semiconductor substrates 1 of shooting, in the operational part of control part 107, handle its result, calculate the center of semiconductor substrate 1.
Then, the carrying hand is based on this result, and to chuck platform part 104 carrying semiconductor substrates 1, chuck platform 11 utilizes vacuum to be fixed after the correction position.This chuck platform 11 just becomes the datum level of processing.Thereby in order to guarantee fixedly and add the plane precision in man-hour, the chuck face preferably uses material and whole structure that clamps semiconductor substrate 1 of porous matter.Material is used metal system, pottery system, resin system etc.Disposing light-projecting portion 114 with clamped semiconductor substrate 1 subtend is optical sensor portion, being that camera portion is common with light accepting part 115 measures and the size of computing semiconductor substrate 1, its result is fed back to the X-axis drive division of cutting portion 105, the amount of movement that instruction is used to cut.
In the cutting face is under the situation of wiring formation face, and specifically, as shown in Figure 4, preferably irradiating laser disperses the heating of resist mask, makes its exposing surface.Then, as shown in Figure 5, use and utilize the infiltration type transducer of infrared laser to come the instrumentation position.Then, based on the result in this computing, the platform that has carried the actual cutter that cuts 10 moves to directions X, begins cutting.Cutter 10 is made of diamond etc. as used herein.Finish in this wise up to the cutting of setting size.
Then, the carrying hand takes out semiconductor substrate 1 from chuck platform 11, carries to cleaning part.In cleaning part 105, vacuum is semiconductor substrate 1 and make its rotation fixedly, utilizes the remained on surface foreign matter after the rinse water washing processing simultaneously.Afterwards, air blowing limit, limit makes its high speed rotating, blows rinse water off and makes its drying.After drying was over, the carrying hand took out semiconductor substrate 1 once more, leaves at last in the case 111 of storage part 101.
Each above operation is that benchmark cuts the back side with the face that is formed with dielectric film between projection and projection at first, afterwards, is benchmark with the back side, carries out the processing on the surface of the surface of so-called each projection of cutting and dielectric film, finishes planarizing process.
(semiconductor device and manufacture method thereof)
Below, describe about the method for using the semiconductor-fabricating device of carrying out above-mentioned projection formation method to make semiconductor substrate.Have again,, record and narrate the structure of semiconductor device with this manufacture method at this.
Fig. 9 A～Fig. 9 C illustrates approximate vertical view according to the manufacture method of the semiconductor device of present embodiment according to process sequence.
At first, through Fig. 1 and each operation illustrated in fig. 2, shown in Fig. 9 A, cut out each semiconductor chip 21 from semiconductor substrate 1, this semiconductor substrate 1 has carried LSI element etc., and has the projection 3 that is made top 3a leveling by the cut of using cutter.
Then, shown in Fig. 9 B, prepare semiconductor substrate 22, this semiconductor substrate 22 has the projection 3 that is made the upper surface leveling by the cut of using cutter, on this semiconductor substrate 22, each other each semiconductor chip 21 is electrically connected with the top 3a of being flattened of projection 3.Specifically, it is opposite to one another to make semiconductor substrate 22 and semiconductor chip 21 be configured to top 3a, in room temperature～350 ℃, is to carry out the pressure welding connection about 170 ℃ down at this.Because 3a is by leveling accurately above each, therefore, not resembling the prior art needs HTHP etc., and can easily connect semiconductor substrate 22 and semiconductor chip 21.
Then, shown in Fig. 9 C, cut out each semiconductor chip 23 from the semiconductor substrate 22 that connects semiconductor chip 21, through the operation of terminal conjunction method (used go between 25 connection) etc., on substrate 24, carry semiconductor chip 23, thereby finish semiconductor device.
Ground as described above according to present embodiment, can replace CMP, and is cheap and make the surfacingization of the fine bump 3 that is formed on the semiconductor substrate 1 at high speed, and do not produce the unfavorable condition of recess etc., can easily and carry out the connection of projection 3 exactly.Like this, just can carry out projection 3 connection that does not need conditions such as HTHP each other, can rate of finished products the high semiconductor device of fabrication reliability well.
[second execution mode]
Below, describe about second execution mode.In the first embodiment, as bump material, illustration Au, but illustration is used the situation of nickel (Ni) in the present embodiment.
Figure 10 A～Figure 10 F illustrates general profile chart according to the projection formation method of present embodiment according to process sequence.
At first, through the operation identical with Figure 1A, the B of first execution mode, back side grinded semiconductor substrate 1, TTL is at setting or below it in control, concrete is 1 μ m or below it.
Use this semiconductor substrate 1, shown in Figure 10 A, after the surface patterning of semiconductor substrate 1 has formed the electrode 31 that is made of aluminum-based metal, utilize non-electrolytic plating method, at the nickel phosphorus electroplating film 32 that forms on this electrode 31 about thickness 5 μ m～10 μ m.
Utilize general non-electrolytic plating method, use nickel-phosphorus, nickel-phosphorus-boron, nickel-boron etc. to form nickel phosphorus electroplating film 32.For example, form nickel-phosphor alloy,, form nickel-phosphorus-boron alloy with neutral solution with having used sodium borohydride liquid or dimethylamino monoborane (dimethyl amino borane) to form nickel-boron alloy with hypophosphorous acid liquid (sodium hypophosphite or potassium hypophosphite).
At this, be in the electroless plating at nickel phosphorus, even select above-mentioned any alloy system, all forming the mechanicalness fragile layer on the top layer of nickel phosphorus electroplating film 32 is phosphorus enriched layer 33.After solder bump forms, because this phosphorus enriched layer is electroplated the boundary strength decline with solder bump.The thickness of this phosphorus enriched layer is about 20nm～40nm, and high more its thickness of the phosphorus containing ratio in the electroplate liquid is thick more.
In addition, the material (glass substrate, iron substrate, aluminium base) of bottom is not depended in the generation of this phosphorus enriched layer, does not depend on the thickness of plating yet.In addition, even will be that electroless plating carries out scolding tin fusing point or its above annealing in process, also must generate the phosphorus enriched layer on the top layer as the nickel of record in the patent documentation 6 (the flat 2000-252313 of TOHKEMY).If do not remove the phosphorus enriched layer, just be difficult to form the plating tunicle and the solder bump of high reliability.
About these problems, a kind of like this method is arranged, by in soldering tin material, adding the compound layer that copper forms copper-nickel-Xi system, utilize its screen effect to suppress the formation of phosphorus enriched layer.But, form phosphorus enriched layer etc., the restriction of Au electroplating thickness and the narrow problem of the selectivity of soldering tin material because the Au electroplating thickness when 500nm or its are above, exists.
Therefore in this example, when nickel phosphorus electroplating film 32 utilizes cut to carry out leveling, remove this phosphorus enriched layer 33 simultaneously.
Specifically, at first shown in Figure 10 B, the aqueous protective layer and as diaphragm 34 of being covered makes the covered substrate surface, and the relaxation layer of the physical impact that causes as cut described later.Form diaphragm 34 by curing after waiting the thickness that applies into about 10 μ m～15 μ m with the rotation coating.
Afterwards, same with Fig. 2 A, utilize for example vacuum suction, the back side is adsorbed on the bearing-surface of substrate supporting platform, semiconductor substrate 1 is fixed on the substrate supporting platform.At this moment, owing to, become the certain state of thickness of semiconductor substrate 1 to the planarizing process of Figure 1B of back side 1b, in addition, back side 1b is owing to being forced to the state that does not does not rise and fall etc. to bearing-surface 11a absorption, like this, back side 1b becomes the datum level of the leveling of surperficial 1a.Under this state; shown in Figure 10 C; each the nickel phosphorus electroplating film 32 among the surperficial 1a and the top layer of diaphragm 34 are carried out machining; use the cutter that constitutes by diamond etc. to carry out cut at this; in the phosphorus enriched layer 33 of removing nickel phosphorus electroplating film 32, carry out planarizing process, make the surperficial continuous and smooth of nickel phosphorus electroplating film 32 and diaphragm 34.Cutting output is set at about the 1 μ m～2 μ m that can remove phosphorus enriched layer 33 exactly.
Then, as required, shown in Figure 10 D, utilize non-electrolytic plating method, on nickel phosphorus electroplating film 32, form gold-plated film 35.The thickness of gold-plated film 35 is preferably about 30nm～50nm.
Then, shown in Figure 10 E, utilize removal diaphragms 34 such as ashing treatment.At this moment, just on the surperficial 1a of semiconductor substrate 1, formed projection 36, this projection 36 height homogeneous, and top leveling similarly by cut, and form gold-plated film 35 and constitute.
Then, as required, shown in Figure 10 F, on projection 36, form solder bump 37.Utilize silk screen printing, solder ball method, fusion to wait and form this solder bump 37.As the material of scolding tin, preferably use the scolding tin of lead-free Xi-Yin system, tin-zinc etc.
Afterwards, utilize full cutting (full cut dicing) dividing semiconductor substrate 1, and cut out semiconductor chip, similarly finish semiconductor device with first execution mode.
Ground as described above, according to present embodiment, can replace CMP, cheap and make the surfacingization of the projection 36 that is formed on the nickel on the semiconductor substrate 1 at high speed, and do not produce the unfavorable condition of recess etc., like this, just can carry out projection 36 connection that does not need conditions such as HTHP each other, can rate of finished products the high semiconductor device of fabrication reliability well.And, can remove the phosphorus enriched layer 34 of the reduction reliability on the junction that makes projection 36 and solder bump 37 at low cost fully, therefore, form solder bump 37 exactly on the projection 36 of being flattened in the above.
[the 3rd execution mode]
Below, describe about the 3rd execution mode.In the first embodiment, carried out illustration, but disclose the above-mentioned planarizing process of execution under the state of semiconductor chip in the present embodiment, engaged this semiconductor chip situation each other about the situation that engages a plurality of semiconductor chips with semiconductor substrate.
Figure 11 A, Figure 11 B show general profile chart according to the manufacture method of the semiconductor device of present embodiment according to process sequence.
At first, shown in Figure 11 A, do not need to carry out the back side grinding of first execution mode, cut out each semiconductor chip 41 from semiconductor substrate, this semiconductor substrate has carried LSI element etc., and forms highly a plurality of projections of different (highly still having deviation), is Au projection 42 at this.
Then, the top layer of machining semiconductor chip 41, at this, with first execution mode similarly, use the cutter that constitutes by diamond etc. to carry out cut, carry out planarizing process, make the surperficial continuous and smooth of each Au projection 42.Like this, the height of each Au projection 42 is flattened above the while and changes into mirror-like by homogenization.
Then, shown in Figure 11 B, make a pair of semiconductor chip 41 subtends, utilize the top of being flattened of Au projection 42 each other both to be electrically connected.Specifically, it is top opposite to one another that a pair of semiconductor chip 41 is configured to, and in room temperature～350 ℃, is to carry out pressure welding under about 170 ℃ to connect at this.Because all by leveling accurately, therefore, not resembling the prior art needs HTHP etc., and can easily connect a pair of semiconductor chip 41 above each.
In this wise, according to present embodiment, can replace CMP, cheap and make the surfacingization that is formed on the fine Au projection 42 on the semiconductor chip 41 at high speed, and do not produce the unfavorable condition of recess, can be easily and carry out the connection of the Au projection 42 in a pair of semiconductor chip 41 exactly.Like this, just can carry out Au projection 42 connection that does not need conditions such as HTHP each other, can rate of finished products the high semiconductor device of fabrication reliability well.And,, help to cut down operation quantity owing to, therefore, can omit the operation of control TTV cut out the above-mentioned cut of each semiconductor chip 41 back execution from semiconductor substrate.
[variation 1]
At this, describe about modified embodiment of the present embodiment 1.
Figure 12 A～Figure 12 C illustrates general profile chart according to the manufacture method of the semiconductor device of variation 1 according to process sequence.
At first, shown in Figure 12 A, do not carry out the back side grinding of first execution mode, cut out each semiconductor chip 41 from semiconductor substrate, this semiconductor substrate has carried LSI element etc., and forms a plurality of projections of highly different (highly still having deviation) and constitute, and is Au projection 42 at this.
Then, on the surface of semiconductor chip 41, form the resin bed 43 that constitutes by insulating material in the mode of imbedding Au projection 42.Have again, also can be under the state of semiconductor substrate form after the resin bed 43, cut out each semiconductor chip 41 in the mode of imbedding Au projection 42.
Then, shown in Figure 12 B, machining is carried out on the top layer of semiconductor chip 41, at this, with first execution mode similarly, use the cutter that constitutes by diamond etc. to carry out cut, carry out planarizing process, make the surperficial continuous and smooth of the surface of each Au projection 42 and resin bed 43.Like this, the height of each Au projection 42 simultaneously, is flattened above and changes into mirror-like by homogenization.
Then, make a pair of semiconductor chip 41 subtends, each other both are electrically connected with the top of being flattened of Au projection 42 and resin bed 43.Specifically, it is opposite to one another to make a pair of semiconductor chip 41 be configured to upper surface, is to carry out pressure welding under about 170 ℃ to connect in room temperature～350 ℃, at this.Because all by leveling accurately, therefore, not resembling the prior art needs HTHP etc., and can easily connect a pair of semiconductor chip 41 above each.In addition, when making resin molding 43 and a pair of semiconductor chip 41 engage exactly, also help as guard electrode 42 grades owe the dress (underfill).
In this wise, according to this variation 1, can replace CMP, cheap and make the surfacingization that is formed on the fine Au projection 42 on the semiconductor chip 41 at high speed, and do not produce the unfavorable condition of recess etc., can be easily and carry out the connection of the Au projection 42 in a pair of semiconductor chip 41 exactly.Like this, can carry out Au projection 42 connection that does not need conditions such as HTHP each other, can rate of finished products the high semiconductor device of fabrication reliability well.And,, help to cut down operation quantity owing to, therefore, can omit the operation of control TTV cut out the above-mentioned cut of each semiconductor chip 41 back execution from semiconductor substrate.
[variation 2]
At this, describe about modified embodiment of the present embodiment 2.
Figure 13 A～Figure 13 C illustrates general profile chart according to the manufacture method of the semiconductor device of variation 2 according to process sequence.
At first, as shown in FIG. 13A, do not need to carry out the back side grinding of first execution mode, cut out each semiconductor chip 41 from semiconductor substrate, this semiconductor substrate has carried LSI element etc., and forms a plurality of projections of highly different (highly still having deviation) and constitute, and is Au projection 42 at this.
Then, machining is carried out on the top layer of semiconductor chip 41, at this, with first execution mode similarly, use the cutter that constitutes by diamond etc. to carry out cut, carry out planarizing process, make the surperficial continuous and smooth of each Au projection 42.Like this, the height of each Au projection 42 simultaneously, is flattened above and changes into mirror-like by homogenization.
Then, shown in Figure 13 B, two be one group ground with the semiconductor chip after the planarizing process 41 as a pair of semiconductor chip 41, on the surface of a side semiconductor chip 41, form resin bed 44, this resin bed 44 contains electrically conductive microparticle 45 in the resin of insulating properties, its thickness is for imbedding the thickness of Au projection 42 fully.
Then, make a pair of semiconductor chip 41 subtends, each other both are electrically connected with the top of being flattened of Au projection 42.Specifically, it is top opposite to one another that a pair of semiconductor chip 41 is configured to, and in room temperature～350 ℃, is to carry out pressure welding under about 170 ℃ at this.At this, utilize thermocompression bonding, the Au projection 42 that makes subtend is each other by electrically conductive microparticle 45 contacts, and electrical connection.Because all by leveling accurately, therefore, not resembling the prior art needs HTHP etc., and can easily connect a pair of semiconductor chip 41 above each.In addition,, also help to owe dress (underfill) with when a pair of semiconductor chip 41 is adjacent to exactly and is electrically connected at the resin that makes resin bed 44 as guard electrode 42 grades.
In this wise, according to this variation 2, can replace CMP, cheap and make the surfacingization that is formed on the fine Au projection 42 on the semiconductor chip 41 at high speed, and do not produce the unfavorable condition of recess etc., can be easily and carry out the connection of the Au projection 42 in a pair of semiconductor chip 41 exactly.Like this, can carry out Au projection 42 connection that does not need conditions such as HTHP each other, can rate of finished products the high semiconductor device of fabrication reliability well.And,, help to cut down operation quantity owing to, therefore, can omit the operation of control TTV cut out the above-mentioned cut of each semiconductor chip 41 back execution from semiconductor substrate.
[the 4th execution mode]
Below, describe about the 4th execution mode.In the first embodiment, carried out illustration about on semiconductor substrate, forming the outside situation that connects the projection of usefulness, but in the present embodiment, used the situation of the column-like projection block of terminal conjunction method to disclose about formation.
Figure 14 A～Figure 14 F illustrates general profile chart according to the manufacture method of the semiconductor device of present embodiment according to process sequence.
At first, shown in Figure 14 A and Figure 14 B, with Figure 1A back side of grinded semiconductor substrate 51 similarly, this semiconductor substrate 51 forms on the position at element and has formed LSI semiconductor element and electrode pad etc., the thickness of control semiconductor substrate 51 is certain, specifically controls TTV (maximum ga(u)ge of substrate and minimum thickness poor) at 1 μ m or below it.
At this, in above-mentioned grinding process, also can be in grinding after the back side of semiconductor substrate 51, utilize sputtering method, on semiconductor substrate 51, form for example Al film of metal film,, becoming formation electrode pad 52 on the position of electrical connection place by it is constituted figure.
Then, shown in Figure 14 C, utilize to use the terminal conjunction method of Au as metal, on electrode pad 52 pressure welding after the spherical piece that for example forms behind the front end of the Au bonding wire of 20 μ m diameters of fusion, tear (precuting) this lead-in wire, on electrode pad 52, form Au projection 53.At this moment, the height of stipulating each Au projection 53 distance electrode pad 52 is about 60 μ m more than or equal to 2 times of bonding wire diameter at this.Under this situation, actual have deviation in the height of Au projection 53, preferably about 50 μ m～60 μ m.
Then, shown in Figure 14 D, use the cutter 10 that constitutes by diamond etc. to carry out cut, carry out planarizing process, make the top continuous and smooth of each Au projection 53, and form column-like projection block 54.At this, establish cutting position distance electrode pad 52 and for example be the height about 50 μ m.Machining condition is, cutting speed 10m/s, and feeding each time is about 20 μ m, forces into 2 μ m from initial cutting position at every turn.Like this, shown in Figure 14 E, make the top smooth mirror-like that changes into of Au projection 53, form column-like projection block 54.
The leveling method of this cut is compared with CMP, owing to do not need slip, the cutter of cutting tools can use repeatedly through polishing after wearing and tearing, and is therefore with low cost.Owing to make the semiconductor substrate high speed rotating that is clamped on the chuck platform, make cutter in the above in accordance with regulations speed move, cut the depth of cut arbitrarily once, therefore, per 1 chip semiconductor substrate just can be finished with 1～2 minute, was the very high method of a kind of productivity ratio.In utilizing the cut of cutter, by suitably setting machining condition, in the situation of cutting in the projected front ends portion of the projection of the column-like projection block of the bonding wire that has used Au etc., that can carry out projection does not have or crooked plane cutting.But, if the following hardness of 30Hv or its, the probably inclination that when cutting, just produces projection, therefore, the hardness of lead-in wire is preferably in 30Hv or more than it.
In the present embodiment, as the terminal point of cut, the diameter in cutting face that is made as whole column-like projection blocks is more than or equal to moment of diameter wire.Usually, deviation is bigger in the height of column-like projection block after precuting, and is difficult to confirm the point of the diameter in cutting face more than or equal to diameter wire in whole column-like projection blocks.As cutting process, preferably the point that contacts with the highest projection from cutter is forced into 1～3 μ m at every turn, and the cutting face of exposing whole cutters, but that each camera image with amplification etc. are confirmed with regard to efficient is too low.
Therefore, in the present embodiment, shown in Figure 15 A, as the terminal point method for detecting, adopt following method, even with the detection device with laser generator 61 and detector 62, emission of lasering beam above the column-like projection block 54 after cut, detect on this with detector 62 on laser light reflected.
Then, shown in Figure 15 B, process repeatedly, on whole Au projections 53, reach prescribed strength up to the laser intensity that detects.Preferably this detection device is arranged on the rear of the direction of advance of cutting tools, synchronously advances with cutting tools.Because top (cutting face) of column-like projection block 54 roughly becomes minute surface, therefore, laser etc. carry out total reflection.With the synchronous situation of cutting tools under, produce delay pro rata with the pace of cutting tools, therefore, not talkatively strictly detect whole reverberation, but since cutting speed near tens m/s, can detect so can regard as roughly.
In the present embodiment, utilization begins and synchronization-moving laser generator 61 of advancing of cutter and detector 62 from the rear portion of cutter, laser light reflected intensity above the Au projection 53 of one side mensuration after leveling, force on one side, expose above for example on the height of 46 μ m, detecting whole Au projections 53, just finish cutting then.
At this, shown in Figure 15 C, under the situation of diameter smaller or equal to diameter wire in inadequate situation of cut or cutting face, run into cutting face laser in the localities in addition and carry out diffuse reflection, do not detect and can not be detected device.Therefore, shown in Figure 15 D, the laser intensity that detects than be cut to bonding wire with the footpath face on weak strength.In a place, confirm under the situation of such column-like projection block, just automatically further force into about 1 μ m～2 μ m, finally be cut to and in whole projections, detect laser intensity a certain amount of or more than it.Like this, can prevent from not cut or cut deficiency and in the bad connection that causes, can shorten process time significantly.
Then, shown in Figure 14 F, cut out each semiconductor chip 55, utilize for example flip-chip method, connect semiconductor chip 55 and circuit substrate 56 from semiconductor substrate 51.Specifically, make semiconductor chip 55 above the column-like projection block 54 of being flattened contact with lip-deep electrode 57 subtends that are formed on circuit substrate 56, utilize pressurization and heating to engage both.Have again, in this case, the electrode 57 of circuit substrate 56 also with column-like projection block 54 similarly, also be adapted at utilizing after the above-mentioned cut leveling, carry out flip-chip and connect.
Ground as described above, according to present embodiment, can replace CMP, cheap and make the surfacingization that is formed on the fine column-like projection block 54 on the semiconductor substrate 51 at high speed, and do not produce the unfavorable condition of concave pit etc., can easily and carry out the connection of column-like projection block 54 exactly.Like this, just can carry out the projection connection that does not need conditions such as HTHP each other, can rate of finished products the high semiconductor device of fabrication reliability well.And, compare with the situation of regulation diameter wire not, can make the height of the column-like projection block 54 after the cutting leveling be located at 1.5 times or more than it, can relax stress to semiconductor element, can prolong equipment life.In addition, because the burnishing surface in the cutting is more than or equal to diameter wire, therefore, even identical diameter wire also can access the above bond strength of 2 times or its.In addition, bond strength and existing same degree with regard to enough situations under, can make diameter wire thinner, therefore, bump pitch is dwindled, can reduce the required cost of bonding wire.
[the 5th execution mode]
Below, describe about the 5th execution mode.At this, illustration is utilized the semiconductor device of so-called TAB bonding method.
Figure 16 and Figure 17 are the general profile charts that illustrates according to the manufacture method of the semiconductor device of present embodiment.
For making this semiconductor device, at first with first execution mode similarly, through each operation shown in Fig. 1 and Fig. 2, on forming the position, element formed on the electrode 71 of semiconductor substrate 1 of LSI semiconductor element etc., by base metal film 72, form highly homogeneous projection 3,3a leveling above this projection 3 similarly makes and forming after each Au projection 2 of cut.At this, around the projection 3 of semiconductor substrate 1, be formed with the diaphragm 73 of insulating properties.
Then, contact with the top of projection 3, check the electrical characteristics of the semiconductor element etc. of semiconductor substrate 1 by making probe.At this, in the prior art,, therefore, can not get stable contact because probe plating end face concavo-convex with existing of projection or that pollute is contacted, the front end that produces probe is sometimes blocked and damaged fault by this concavo-convex position.Relatively therewith, in the present embodiment since make probe with by above-mentioned cut to heavens leveling contact with the surface of projection 3 after the purification, therefore, can under the state of stabilizer pole, check.
Then, after this semiconductor substrate 1 cuts out each semiconductor chip 21, as shown in figure 16, utilize the TAB bonding method to carry out the connection of semiconductor chip 21.
Specifically, the TAB lead 74 that preparation is made of Copper Foil 75, this TAB lead 74 has formed Au film 76 after the surface treatment of implementing Au, and the place that is positioned at an end is its connecting portion, at the other end resin bed 77 is set.Then, on engagement platform 80, place fixedly semiconductor chip 21, Au film 76 and the leveling of semiconductor chip 21 of the connecting portion of TAB lead 74 are contacted with the top of projection 3 after the purification, pressurize, engage both while utilize heater 78 to heat.At this, heating-up temperature is 200 ℃ lower temperature preferably, and bonding load also can be reduced to about 20g of existing about 2/3.As a result of, can there be the TAB lead that offset ground connects 40 μ m spacings or its following minuteness space.
Like this, as shown in figure 17, take off semiconductor chip 21 from engagement platform 80, form sealing resin 79, semiconductor device is finished on the feasible surface that covers the semiconductor chip 21 of the connecting portion that comprises projection 3 and TAB lead 74.
Have again, in the present embodiment, as the projection illustration form the situation of plated bumps, but also can form the column-like projection block that utilizes terminal conjunction method.
Ground as described above according to present embodiment, can replace CMP, and is cheap and make the surfacingization of the fine bump 3 that is formed on the semiconductor substrate 1 at high speed, and do not produce the unfavorable condition of concave pit etc., can easily and carry out the connection of projection 3 exactly.Like this, can carry out not needing being connected of conditions such as HTHP between projection and the conductor terminal semiconductor device that can the rate of finished products TAB maqting type that fabrication reliability is high well.
[the 6th execution mode]
Below, describe about the 6th execution mode.Disclose at this and to be used for when carrying out each above-mentioned execution mode, carried out above-mentioned cut operation and engage the apparatus structure of operation about a pair of matrix (utilizing the semiconductor chip and the circuit substrate of flip-chip method in this illustration).
Figure 18 is the ideograph that illustrates according to the semiconductor-fabricating device of present embodiment.
This semiconductor-fabricating device has: the chip introduction part 81 that is used to import the semiconductor chip that has formed projection on the surface, be used to import the circuit substrate introduction part 82 of the circuit substrate that has formed electrode on the surface, utilize the cut of above-mentioned use cutter to carry out the cutting portion 83 of operation of the lug surface of leveling semiconductor chip, the projection of execution by being flattened and the junction surface 84 of the operation that engages of electrode pair semiconductor chip and circuit substrate, be used to take out of and engage and the portion that takes out of 85 of incorporate semiconductor device, and then, have and make cutting portion 83 and junction surface 84 be included in the purification maintaining part 86 in the inert atmosphere and constitute.At this, in cutting portion 83, semiconductor chip not only, the electrode surface of circuit substrate utilizes cut to carry out leveling similarly.
Purify maintaining part 86 and have the leveling operation and engage operation and remain on the function that purifies in the atmosphere together, concrete is in the inert atmosphere, for example Ar and N 2Deng do not wrap in the oxygen containing gas phase, perhaps wrap in the following atmosphere of oxygen containing 1atm or its.Like this, before engaging operation, do not need the additional cleaning procedure that has used Ar plasma etc., can keep the desirable leveling state that is in close proximity to comparalive ease, exactly engagement protrusion and electrode.
Have again, in the present embodiment, illustration the flip-chip installation, but the present invention is not limited to this, also goes for semiconductor chip and engaging that semiconductor wafer, semiconductor chip wait each other.
According to the present invention, can replace CMP, cheap and make the surfacingization that is formed on the fine bump on the substrate at high speed, and do not produce the unfavorable condition of recess etc., can be easily and carry out projection connection each other exactly.

Claims (21)

1. a projection formation method forms projection on the surface of substrate, and this projection is used for being electrically connected with the outside, it is characterized in that comprising:
Surface with aforesaid substrate is a benchmark, utilizes machining the back side of aforesaid substrate to be carried out the operation of planarizing process;
On the surface of aforesaid substrate, form the operation of the dielectric film between a plurality of above-mentioned projections and the above-mentioned projection;
Carry out planarizing process by the cut of using cutter, make the surface of above-mentioned each projection and the surperficial continuous and smooth operation of above-mentioned dielectric film, in this operation, the above-mentioned back side with aforesaid substrate is benchmark, and planarizing process is carried out on the surface of above-mentioned projection and the surface of above-mentioned dielectric film;
Remove the operation of above-mentioned dielectric film.
2. projection formation method as claimed in claim 1 is characterized in that,
When forming above-mentioned projection, process above-mentioned dielectric film and also form after the mask of a plurality of openings with electrode shape, imbed above-mentioned each opening of above-mentioned mask with electric conducting material.
3. projection formation method as claimed in claim 2 is characterized in that, utilizes galvanoplastic, imbeds above-mentioned each opening of above-mentioned mask with above-mentioned electric conducting material.
4. projection formation method as claimed in claim 1 is characterized in that, utilizing nickel is that non-electrolytic plating method forms above-mentioned projection,
When the above-mentioned projection of above-mentioned cut surperficial, remove the high layer of inside phosphorus concentration of the above-mentioned projection of ratio on the top layer that is created on above-mentioned projection.
5. projection formation method as claimed in claim 4 is characterized in that, utilizing nickel is that non-electrolytic plating method forms after the above-mentioned projection, forms above-mentioned dielectric film in the mode that covers above-mentioned projection.
6. projection formation method as claimed in claim 1 is characterized in that aforesaid substrate is provided with the LSI element, and above-mentioned projection is connected with above-mentioned LSI element.
7. projection formation method as claimed in claim 1 is characterized in that, the surface of the above-mentioned projection of cut, and making becomes sustained height on aforesaid substrate.
8. projection formation method as claimed in claim 1 is characterized in that, a plurality of aforesaid substrates are carried out above-mentioned each operation, makes the thickness homogeneous of above-mentioned each substrate change into identical.
9. projection formation method as claimed in claim 1 is characterized in that, when planarizing process is carried out on the surface of the surface of above-mentioned projection and above-mentioned dielectric film,
Being when benchmark carries out the parallel cutting of above-mentioned semiconductor substrate with the above-mentioned back side, detect the position on the surface of aforesaid substrate, calculate cutting output from the surface of the aforesaid substrate that detects and control.
10. projection formation method as claimed in claim 9, it is characterized in that, when the position on the above-mentioned surface that detects aforesaid substrate, the dielectric film irradiating laser in the many places at the peripheral position on above-mentioned surface, and the insulant heating is dispersed, the part on above-mentioned surface is exposed.
11. projection formation method as claimed in claim 9 is characterized in that, when the position on the above-mentioned surface that detects aforesaid substrate, to above-mentioned back side illuminaton infrared laser, measures the reverberation from above-mentioned surface.
12. the manufacture method of a semiconductor device is characterized in that comprising:
Surface with substrate is a benchmark, utilizes machining the back side of aforesaid substrate to be carried out the operation of planarizing process;
On each surface of a pair of semiconductor substrate to be embedded to the operation that mode in the dielectric film forms each projection;
Carry out planarizing process by the cut of using cutter, make the surface of above-mentioned each projection and the surperficial continuous and smooth operation of above-mentioned dielectric film, in this operation, the above-mentioned back side with above-mentioned half and half conductor substrate is benchmark, and planarizing process is carried out on the surface of above-mentioned projection and the surface of above-mentioned dielectric film;
Remove the operation of above-mentioned dielectric film;
The smooth above-mentioned surface that makes above-mentioned each projection toward each other to and connect, thereby with the incorporate operation of above-mentioned each semiconductor substrate.
13. the manufacture method of semiconductor device as claimed in claim 12 is characterized in that, is respectively arranged with the LSI element on above-mentioned each semiconductor substrate, on above-mentioned each semiconductor substrate, above-mentioned each projection is connected with above-mentioned each LSI element.
14. a projection formation method forms projection on the surface of substrate, this projection is used for being electrically connected with the outside, it is characterized in that comprising:
Surface with aforesaid substrate is a benchmark, utilizes machining the back side of aforesaid substrate to be carried out the operation of planarizing process;
On the surface of aforesaid substrate, form the operation of a plurality of above-mentioned projections;
Carrying out planarizing process by the cut of using cutter, make the surperficial continuous and smooth operation of above-mentioned a plurality of projections, in this operation, is benchmark with the above-mentioned back side of aforesaid substrate, and planarizing process is carried out on the surface of above-mentioned projection.
15. a projection formation method forms the column-like projection block that uses terminal conjunction method on the surface of semiconductor substrate, this projection is used for being electrically connected with the outside, it is characterized in that comprising:
Surface with aforesaid substrate is a benchmark, utilizes machining the back side of aforesaid substrate to be carried out the operation of planarizing process;
Use bonding wire, electrical connection place on the surface of above-mentioned semiconductor substrate forms the operation of a plurality of juts;
Carry out planarizing process by the cut of using cutter, make the top continuous and smooth of above-mentioned a plurality of juts, form the operation of above-mentioned column-like projection block, in this operation, the above-mentioned back side with aforesaid substrate is benchmark, and planarizing process is carried out on the surface of above-mentioned jut.
16. projection formation method as claimed in claim 15, it is characterized in that, use has the detection device of laser generator and detector, illuminating laser beam above above-mentioned jut after above-mentioned cut above-mentioned, detect by laser light reflected above above-mentioned by above-mentioned detector, carry out above-mentioned cut repeatedly, reach setting for whole above-mentioned juts up to the laser intensity that utilizes aforesaid method to detect.
17. projection formation method as claimed in claim 16 is characterized in that, above-mentioned detector is arranged on the rear of the direction of advance of above-mentioned cutter, makes the same moved further of action of above-mentioned detector and above-mentioned cutter.
18. projection formation method as claimed in claim 15 is characterized in that also comprising:
Form the operation of diaphragm in the mode that covers above-mentioned a plurality of juts;
Utilize above-mentioned cut to carry out planarizing process, make after top and said protection film surperficial continuous and smooth of above-mentioned a plurality of juts, remove the operation of said protection film.
19. the manufacture method of a semiconductor device is characterized in that, comprising:
Surface with semiconductor substrate is a benchmark, utilizes machining the back side to be carried out the operation of planarizing process;
On the surface of above-mentioned semiconductor substrate, form the operation of a plurality of projections;
Carrying out planarizing process by the cut of using cutter, make the surperficial continuous and smooth operation of above-mentioned a plurality of projections, in this operation, is benchmark with the above-mentioned back side, utilizes above-mentioned cut that planarizing process is carried out on the surface of above-mentioned projection;
Cut out the operation of each semiconductor chip from the above-mentioned semiconductor substrate of being flattened of surface of above-mentioned a plurality of projections;
The operation that connects an end of the above-mentioned projection of above-mentioned semiconductor chip and conductor terminal.
20. the manufacture method of a semiconductor device is characterized in that, comprising:
Surface with semiconductor substrate is a benchmark, utilizes machining the back side to be carried out the operation of planarizing process;
Forming the operation of a plurality of juts that use terminal conjunction method in electrical connection place on the surface of above-mentioned semiconductor substrate, in this operation, is benchmark with the above-mentioned back side, utilizes cut that planarizing process is carried out on the surface of above-mentioned projection;
Carry out planarizing process by the cut of using cutter, make the top continuous and smooth of above-mentioned a plurality of juts, form the operation of column-like projection block;
From having formed the above-mentioned semiconductor substrate of a plurality of column-like projection blocks, cut out the operation of each semiconductor chip;
The operation that connects an end of the above-mentioned column-like projection block of above-mentioned semiconductor chip and conductor terminal.
21. the manufacture method of semiconductor device as claimed in claim 20, it is characterized in that, also have after leveling is carried out on the surface of above-mentioned projection, with before above-mentioned conductor terminal is connected, test is contacted and the operation checked with the surface of above-mentioned projection with pin.
CNB038227576A 2002-12-27 2003-04-22 Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus and semiconductor manufacturing apparatus Expired - Fee Related CN100477139C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP381582/2002 2002-12-27
JP2002381582 2002-12-27

Related Child Applications (2)

Application Number Title Priority Date Filing Date
CN2009100066807A Division CN101483144B (en) 2002-12-27 2003-04-22 Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus
CN2010105260859A Division CN102044413B (en) 2002-12-27 2003-04-22 Substrate processing apparatus

Publications (2)

Publication Number Publication Date
CN1685489A CN1685489A (en) 2005-10-19
CN100477139C true CN100477139C (en) 2009-04-08

Family

ID=32708500

Family Applications (3)

Application Number Title Priority Date Filing Date
CN2009100066807A Expired - Fee Related CN101483144B (en) 2002-12-27 2003-04-22 Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus
CNB038227576A Expired - Fee Related CN100477139C (en) 2002-12-27 2003-04-22 Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus and semiconductor manufacturing apparatus
CN2010105260859A Expired - Fee Related CN102044413B (en) 2002-12-27 2003-04-22 Substrate processing apparatus

Family Applications Before (1)

Application Number Title Priority Date Filing Date
CN2009100066807A Expired - Fee Related CN101483144B (en) 2002-12-27 2003-04-22 Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN2010105260859A Expired - Fee Related CN102044413B (en) 2002-12-27 2003-04-22 Substrate processing apparatus

Country Status (3)

Country Link
JP (2) JP4279786B2 (en)
CN (3) CN101483144B (en)
WO (1) WO2004061935A1 (en)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4709535B2 (en) * 2004-11-19 2011-06-22 株式会社東芝 Semiconductor device manufacturing equipment
JP4796330B2 (en) * 2005-05-18 2011-10-19 株式会社ディスコ Bump processing method
JP4768546B2 (en) * 2006-08-16 2011-09-07 富士通株式会社 Manufacturing method of semiconductor device
JP2008182015A (en) * 2007-01-24 2008-08-07 Disco Abrasive Syst Ltd Method for grinding wafer
US7803693B2 (en) * 2007-02-15 2010-09-28 John Trezza Bowed wafer hybridization compensation
JP4466662B2 (en) * 2007-03-06 2010-05-26 株式会社デンソー Method for forming metal electrode of semiconductor device
JP4875532B2 (en) 2007-04-03 2012-02-15 株式会社ディスコ Cutting device
CN101231961B (en) * 2008-02-21 2010-11-17 日月光半导体制造股份有限公司 Basal plate making process of inner embedded component
JP2011009561A (en) * 2009-06-26 2011-01-13 Disco Abrasive Syst Ltd Inspection method of device
JP2011018720A (en) * 2009-07-08 2011-01-27 Casio Computer Co Ltd Method of manufacturing semiconductor device
JP2011109067A (en) 2009-10-19 2011-06-02 Denso Corp Method of manufacturing semiconductor device
JP5520097B2 (en) 2010-03-23 2014-06-11 富士フイルム株式会社 Manufacturing method of microstructure
CN102228953B (en) * 2011-06-15 2012-12-19 山东潍坊福田模具有限责任公司 Stamping die insert lost foam manufacturing method
JP6021386B2 (en) 2012-03-30 2016-11-09 オリンパス株式会社 Wiring substrate manufacturing method and semiconductor device manufacturing method
JP5970680B2 (en) * 2012-11-19 2016-08-17 アピックヤマダ株式会社 Resin molded product manufacturing method and resin removing device
JP6269682B2 (en) * 2013-11-29 2018-01-31 富士通株式会社 Substrate bonding method
CN105448750A (en) * 2014-08-28 2016-03-30 中芯国际集成电路制造(上海)有限公司 Semiconductor device and manufacturing method thereof, and electronic device
JP6536024B2 (en) * 2014-12-04 2019-07-03 日立化成株式会社 Semiconductor device manufacturing method and semiconductor device
WO2016174733A1 (en) 2015-04-28 2016-11-03 オリンパス株式会社 Semiconductor device
DE102015216619B4 (en) 2015-08-31 2017-08-10 Disco Corporation Method for processing a wafer
TW201812887A (en) * 2016-09-23 2018-04-01 頎邦科技股份有限公司 Wafer dicing method
JP6985599B2 (en) * 2018-01-04 2021-12-22 富士通株式会社 Electronic device and manufacturing method of electronic device
JP7028152B2 (en) * 2018-12-14 2022-03-02 トヨタ自動車株式会社 Resolver
WO2023079751A1 (en) * 2021-11-08 2023-05-11 株式会社レゾナック Semiconductor chip stack, electronic component device, and production method for semiconductor chip stack

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5188280A (en) * 1989-04-28 1993-02-23 Hitachi Ltd. Method of bonding metals, and method and apparatus for producing semiconductor integrated circuit device using said method of bonding metals
JP2570468B2 (en) * 1990-06-01 1997-01-08 日本電気株式会社 Manufacturing method of LSI module
JPH05315404A (en) * 1992-05-07 1993-11-26 Nec Corp Semiconductor substrate for tab
JPH0766241A (en) * 1993-08-31 1995-03-10 Oki Electric Ind Co Ltd Connection structure of electronic part using anisotropic conductive bonding agent
JPH07297196A (en) * 1994-04-25 1995-11-10 Sony Corp Method of forming bump electrode
JP3397265B2 (en) * 1994-11-25 2003-04-14 富士通株式会社 Method for manufacturing semiconductor device
JPH1140621A (en) * 1997-07-16 1999-02-12 Canon Inc Device for bonding beam lead of tab film, semiconductor chip electrically bonded by the bonding device and liquid jet recording head
JP3326382B2 (en) * 1998-03-26 2002-09-24 松下電器産業株式会社 Method for manufacturing semiconductor device
JP3515917B2 (en) * 1998-12-01 2004-04-05 シャープ株式会社 Method for manufacturing semiconductor device
US6267650B1 (en) * 1999-08-09 2001-07-31 Micron Technology, Inc. Apparatus and methods for substantial planarization of solder bumps
JP2001332577A (en) * 2000-05-25 2001-11-30 Citizen Watch Co Ltd Method of manufacturing semiconductor device
JP2002110851A (en) * 2000-10-03 2002-04-12 Rohm Co Ltd Semiconductor chip and semiconductor device using the semiconductor chip

Also Published As

Publication number Publication date
CN101483144A (en) 2009-07-15
JP2009094545A (en) 2009-04-30
CN102044413B (en) 2012-11-21
JP4785937B2 (en) 2011-10-05
CN1685489A (en) 2005-10-19
JPWO2004061935A1 (en) 2006-05-18
CN102044413A (en) 2011-05-04
CN101483144B (en) 2013-08-28
JP4279786B2 (en) 2009-06-17
WO2004061935A1 (en) 2004-07-22

Similar Documents

Publication Publication Date Title
CN100477139C (en) Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus and semiconductor manufacturing apparatus
US8962470B2 (en) Method for forming bumps, semiconductor device and method for manufacturing same, substrate processing apparatus, and semiconductor manufacturing apparatus
KR100903472B1 (en) Method of separating semiconductor dies from a wafer
US8044511B2 (en) Function element and function element mounting structure
JPH1013007A (en) Wiring board with solder bump, its manufacturing method, and flattening tool
WO1995019645A1 (en) Methods and apparatus for producing integrated circuit devices
WO1995022172A1 (en) Compliant electrically connective bumps for an adhesive flip chip integrated circuit device and methods for forming same
JP2810101B2 (en) Electric pin and method of manufacturing the same
KR20010060183A (en) Low profile integrated circuit packages
US5494856A (en) Apparatus and method for creating detachable solder connections
TWI233188B (en) Quad flat no-lead package structure and manufacturing method thereof
US20040072396A1 (en) Semiconductor electronic device and method of manufacturing thereof
US6220499B1 (en) Method for assembling a chip carrier to a semiconductor device
CN104541366A (en) Semiconductor device and method for producing same
JP2003188209A (en) Semiconductor device and manufacturing method therefor
CN109346419B (en) Semiconductor device and method for manufacturing the same
JPH03291950A (en) Electronic circuit board and its manufacture
JPH07297196A (en) Method of forming bump electrode
JPH09326535A (en) Optical semiconductor device and manufacture thereof
JP2004006926A (en) Wiring board with solder bump, its manufacturing method, and flattening jig
JP3500132B2 (en) Flip chip mounting method
JPS60130837A (en) Manufacture of semiconductor device
TW201503271A (en) Reducing solder pad topology differences by planarization
JPS6086840A (en) Manufacture of semiconductor device
TW201937613A (en) Premolded substrate for mounting a semiconductor die and a method of fabrication thereof

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090408

Termination date: 20200422

CF01 Termination of patent right due to non-payment of annual fee