JPWO2004061935A1 - Bump forming method, semiconductor device and manufacturing method thereof, substrate processing apparatus and semiconductor manufacturing device - Google Patents

Abstract

The semiconductor substrate (1) is fixed by adsorbing the back surface (1b) to the support surface (11a) of the substrate support base (11). At this time, the thickness of the semiconductor substrate (1) is made constant by the flattening process on the back surface (1b), and the back surface (1b) is also forced to swell due to adsorption to the support surface (11a). Thus, the back surface (1b) becomes the reference surface for flattening the front surface (1a). In this state, the surface layer of each Au protrusion (2) and resist mask (12) on the surface (1a) is cut using a cutting tool (10), and the surface of each Au protrusion (2) and resist mask (12) A flattening process is performed so as to be continuously flat. Thereby, it can replace with CMP and can planarize the surface of the fine bump formed on the board | substrate cheaply at high speed.

Description

  The present invention relates to a method for forming fine bumps for electrical connection to the outside on the surface of a substrate, a semiconductor device and a manufacturing method thereof, and a substrate processing apparatus and a semiconductor manufacturing apparatus.

Conventionally, gold (Au) bumps or the like are used for fine metal terminals in order to make electrical connection with the outside on the surface of a semiconductor substrate. The Au bump is formed by plating and has a large surface roughness. In order to planarize such a metal terminal, a chemical mechanical polishing (CMP) method is used. In this method, a metal and a resin to be processed are formed in a relatively flat state in advance, a flat polishing pad is pressed against the surface, and the surface is precisely and mechanically flattened using a slurry (chemical abrasive). To be processed. The hard resin or metal surface provided in advance serves as a stop layer, and CMP is completed. The CMP method does not depend on TTV (Total Thickness Variation) defined by variations in the thickness of the semiconductor substrate or the difference between the maximum thickness and the minimum thickness of the semiconductor substrate.
In addition, the conventional bonding of Au bumps or the like having a large surface roughness requires a mounting method in which a load is applied to the bumps by a load, heat, ultrasonic waves, or the like until the roughness is eliminated.
Other than CMP, for example, several flattening methods using a cutting tool have been devised (for example, JP-A-7-326614, JP-A-8-11049, JP-A-9-82616, JP-A-9-82616). 2000-173594). However, both are intended for flattening the SOG film in a partial region on the LSI, and, like CMP, are methods based on the surface to be cut and do not depend on the TTV of the semiconductor substrate. There is also a method of exposing the surface by cutting the bump (refer to Japanese Patent Laid-Open No. 10-345201), but this is intended for flattening the bump portion formed on the LSI, and the surface to be cut is used as a reference. This is a cutting method and does not depend on the TTV of the semiconductor substrate.
As described above, Au bumps are used for fine connection, but it is difficult to join the bumps due to the large roughness of the bump surface. In addition, when a metal such as Au and a resin are simultaneously planarized using CMP, a recess called dishing appears due to a difference in polishing rate between the metal and the resin. In order to obtain reliable bump bonding by this dishing, it is necessary to apply a large load such as a load, heat, or ultrasonic waves to the bump.
The present invention has been made in view of the above problems, and instead of CMP, the surface of fine bumps formed on a substrate is flattened at low speed and at high speed, and the bumps are connected with each other with inconvenience such as dishing. It is an object of the present invention to provide a bump forming method, a highly reliable semiconductor device, a manufacturing method thereof, and a semiconductor manufacturing device that can be easily and reliably performed without being generated.

The bump forming method of the present invention is a method of forming a bump for electrical connection to the outside on the surface of a substrate, and forming a plurality of the bumps and an insulating film between the bumps on the surface of the substrate A step of performing a flattening process so that the surface of each bump and the surface of the insulating film are continuously flattened by cutting using a cutting tool, and a step of removing the insulating film.
The semiconductor device of the present invention has a pair of semiconductor substrates each having a plurality of bumps for electrical connection with the outside formed on the surface, and the surfaces of the bumps are formed on the semiconductor substrates. The semiconductor substrates are continuously and uniformly flattened, and the semiconductor substrates are formed by connecting and planarizing the flattened surfaces of the bumps so as to be integrated.
The method for manufacturing a semiconductor device of the present invention includes a step of forming each bump so as to be embedded in an insulating film on each surface of a pair of semiconductor substrates, and a cutting process using a cutting tool. The step of planarizing the surface of the insulating film so as to be continuously flat, the step of removing the insulating film, and the respective semiconductor substrates, with the flattened surfaces of the respective bumps facing each other Connecting and integrating.
The bump forming method of the present invention is a method for forming a bump for electrical connection to the outside on the surface of the substrate, wherein a plurality of bumps are formed on the surface of the substrate, and a cutting tool is used. And a step of flattening so that the surfaces of the plurality of bumps are continuously flat by cutting.
According to the method of manufacturing a semiconductor device of the present invention, the surface of the plurality of bumps is continuously flat by a step of forming the plurality of bumps on each surface of a pair of semiconductor chips and a cutting process using a cutting tool. And a step of connecting and integrating the pair of semiconductor chips in which the surfaces of the plurality of bumps are flattened so that the bumps face each other.
Each of the semiconductor devices of the present invention has a pair of semiconductor chips formed on the surface with a plurality of bumps for electrical connection with the outside, and the surface of each bump is on the semiconductor chip. The semiconductor chips are continuously and uniformly planarized, and the semiconductor chips are formed by connecting and planarizing the planarized surfaces of the bumps so as to be integrated.
The bump forming method of the present invention is a bump for electrical connection to the surface of a semiconductor substrate, and is a method of forming a stud bump using a wire bonding method. Forming a plurality of protrusions using a bonding wire at a target connection location and cutting using a cutting tool so that the upper surfaces of the plurality of protrusions are continuously flattened, and the stud Forming a bump.
The semiconductor device of the present invention is a bump for electrical connection with the outside, and has a semiconductor chip formed on the surface with a plurality of stud bumps using a wire bonding method. The upper surface is continuously flattened on the semiconductor chip.
The method for manufacturing a semiconductor device according to the present invention includes a step of forming a plurality of bumps on a surface of a semiconductor substrate and a cutting process using a cutting tool so that the surfaces of the plurality of bumps are continuously flattened. A step of cutting out each semiconductor chip from the semiconductor substrate on which the surfaces of the plurality of bumps are flattened, and a step of connecting the bumps of the semiconductor chip and one end of a lead terminal.
The method of manufacturing a semiconductor device according to the present invention includes a step of forming a plurality of protrusions using a wire bonding method at an electrical connection location on the surface of a semiconductor substrate, and a cutting process using a cutting tool. A step of flattening the upper surface continuously to be flat and forming a stud bump, a step of cutting each semiconductor chip from the semiconductor substrate on which a plurality of stud bumps are formed, and the stud of the semiconductor chip Connecting the bump and one end of the lead terminal.
The semiconductor device of the present invention has a semiconductor chip on which a plurality of bumps for electrical connection with the outside are formed, and the surface of each bump is continuously uniform on the semiconductor chip. The bumps of the semiconductor chip and one end of the lead terminal are connected and integrated.
The semiconductor device of the present invention includes a plurality of bumps for electrical connection with the outside, and includes a semiconductor chip having a plurality of stud bumps formed on the surface using a wire bonding method. The surface of the bump is continuously flattened on the semiconductor chip, and the stud bump of the semiconductor chip and one end of the lead terminal are connected and integrated.
According to the method for manufacturing a semiconductor device of the present invention, a semiconductor chip having a plurality of electrodes formed on a surface thereof is introduced into an inert atmosphere, and the surface of the plurality of electrodes is continuously flat by cutting using a cutting tool. A step of planarizing so that the surfaces of the planarized electrodes are kept clean in the inert atmosphere, and the circuit board is connected to the plurality of electrodes of the semiconductor chip. And integrating them.
The semiconductor manufacturing apparatus of the present invention includes a cutting means having a cutting tool, a joining means for joining a pair of introduced substrates, and an inert atmosphere that maintains the environment of the cutting means and the joining means in an inert atmosphere. The cutting means includes, in the inert atmosphere, cutting the plurality of the plurality of electrodes, wherein the plurality of electrodes are formed on the surface by cutting using the cutting tool. The bonding means has a function of flattening so that the surfaces of the electrodes are continuously flat, and the bonding means is in a state where the surfaces of the flattened electrodes are kept clean in the inert atmosphere. The pair of substrates are connected by the plurality of electrodes and integrated.
The substrate processing apparatus of the present invention is a substrate processing apparatus for forming bumps for electrical connection to the outside on the surface of the substrate, and has a flat support surface, and the substrate is disposed on the one surface thereof. A substrate support base that is adsorbed to a support surface and forcibly supports and fixes the one surface as a flat reference surface; and a cutting tool that cuts the other surface of the substrate. A substrate on which an insulating film is formed is supported and fixed on the substrate support, and the surface of each bump and the surface of the insulating film are continuously flattened by cutting using the cutting tool. To do.

1A to 1D are schematic cross-sectional views showing a bump forming method according to the first embodiment in the order of steps.
2A and 2B are schematic cross-sectional views illustrating the bump forming method according to the first embodiment in the order of steps.
3A and 3B are diagrams showing the results of flattening by cutting.
4A and 4B are schematic cross-sectional views showing specific examples of flattening by cutting.
FIG. 5 is a schematic cross-sectional view showing a specific example of flattening by cutting.
FIG. 6 is a block diagram showing the configuration of the cutting apparatus.
FIG. 7 is a schematic configuration diagram of the cutting apparatus.
FIG. 8 is a flowchart of the cutting process.
9A to 9C are schematic plan views illustrating the method of manufacturing the semiconductor device according to the second embodiment in the order of steps.
10A to 10F are schematic cross-sectional views showing the bump forming method according to the second embodiment in the order of steps.
11A and 11B are schematic cross-sectional views illustrating the method of manufacturing a semiconductor device according to the third embodiment in the order of steps.
12A to 12C are schematic cross-sectional views illustrating a method of manufacturing a semiconductor device according to Modification 1 of the third embodiment in the order of steps.
13A to 13C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to Modification 2 of the third embodiment in the order of steps.
14A to 14F are schematic cross-sectional views illustrating the method of manufacturing a semiconductor device according to the fourth embodiment in the order of steps.
15A to 15D are diagrams illustrating a cutting end point detection method according to the fourth embodiment.
FIG. 16 is a schematic cross-sectional view showing the method for manufacturing the semiconductor device of the fifth embodiment.
FIG. 17 is a schematic cross-sectional view showing the method for manufacturing the semiconductor device of the fifth embodiment.
FIG. 18 is a schematic view showing a semiconductor manufacturing apparatus according to the sixth embodiment.

-Basic outline of the present invention-
First, the basic outline of the present invention will be described.
The present inventor has come up with the idea of applying cutting using a cutting tool as a technique for simultaneously flattening the surface of a large number of fine bumps formed on a substrate at a low cost and at a high speed instead of the CMP method. According to this cutting process, even when a bump is embedded in an insulating film on a semiconductor substrate, it does not depend on the polishing rate of the metal and the insulator as in the CMP method, and can be performed simultaneously on the substrate. In addition, the metal and the insulator can be continuously cut, and both can be uniformly flattened without causing dishing or the like. Metals such as copper, aluminum, and nickel, and insulating materials such as polyimide are materials that can be easily cut with a cutting tool. In the present invention, as the metal material and insulating material of the bump, it is preferable that the former is a ductile metal and the latter is a resin having a rigidity of, for example, 200 GPa or more.
In this case, in order to use the above-described cutting process for the flattening of the bump surface, it is preferable to perform the cutting on the basis of the back surface (back surface) of the substrate. In general, the TTV of a silicon substrate is in the range of 1 μm to 5 μm. In the LSI process, a TTV of about 5 μm does not affect photolithography and is usually not considered. However, in the case of cutting, it is greatly influenced by the value of TTV. Flatness accuracy by cutting does not fall below the TTV value. Therefore, when cutting is used for flattening a semiconductor substrate, it is first necessary to control the TTV of the substrate to a target cutting accuracy or less.
In consideration of the above circumstances, the present inventor, when using the above-described cutting process for the flattening of the bump surface, as a specific method for reliably performing the flattening, grinding the back surface with respect to the substrate surface, The present inventors have conceived that the TTV of the semiconductor substrate is kept below the target cutting accuracy. In this case, it is ideal that the TTV is made small and the thickness variation of each semiconductor substrate is suppressed to below the cutting accuracy. However, as long as the TTV can be reduced, the thickness of each semiconductor substrate can be detected during cutting. The amount of cutting can be controlled by detecting the thickness of each individual semiconductor substrate.
In addition to the bumps formed by plating, the bumps are formed by wire bonding, that is, bumps formed by melting the tip of the bonding wire on the electrode pad and tearing the wire. (Hereinafter referred to as a stud bump).
When the stud bump is formed, a pin-shaped protrusion is formed by tearing of the bonding wire, and it is necessary to flatten the protrusion. In the present invention, the above-described flattening method by cutting is also applied to the stud bump. In this case, when the wire is torn (pre-cut), the height of each projection is different and flattened to align with the lowest bump, but the higher the stud bump height, the less stress on the device, Since the device life can be extended, it is necessary to define the height of each protrusion. In the present invention, the height from the electrode pad of the protruding portion at the time of pre-cut is specified to be twice or more of the wire diameter, and the cutting surface diameter is equal to or more than the wire diameter for all stud bumps as the end point of the cutting process. It becomes the time when it became. As a result, the height of the stud bump after the flattening of cutting can be made 1.5 times or more compared to the case where the wire diameter is not specified, and the stress on the semiconductor element can be relaxed, and the device life Can be extended.
And after controlling TTV as mentioned above and planarizing the surface of a fine bump by cutting, each semiconductor chip used as a semiconductor component is cut out from a semiconductor substrate (wafer). Thereafter, the semiconductor substrate having a planarized surface and the semiconductor chip, or the semiconductor chips are electrically connected with the bumps facing each other and bonded. At this time, since the upper surfaces of the opposing bumps are both flattened with high precision, they can be easily joined without requiring high temperature and high pressure as in the prior art.
Here, the inventor further sought specific conditions and states for reliably realizing the bonding between the bumps facing each other. Considering that it is ideal to keep the bumps in the flattened state immediately after the cutting process even during the above-mentioned bonding, both the flattening process and the bonding process are performed in order to keep the flattened state immediately after the cutting process as much as possible. It was conceived to carry out in a cleaning atmosphere, specifically in an inert atmosphere. Although this point can be dealt with by adding a cleaning step using Ar plasma or the like immediately before the bonding step, there is a drawback that the number of steps increases. In the present invention, a planarized state that is extremely close to the ideal can be maintained relatively easily without causing an increase in the number of steps, and the bumps can be reliably bonded.
The inventor pays attention to the state of the semiconductor chip as another aspect of the present invention. In other words, at the wafer level, the TTV of the semiconductor substrate becomes a problem as described above. However, since the size of individual chips such as semiconductor chips is small, the TTV in the chip area is almost not at the time of cutting. Only a negligible influence is received.
Therefore, the present inventor has first conceived that after cutting each semiconductor chip from the semiconductor substrate, the surface of the fine bump is flattened by cutting using the above-described bump in the state of the semiconductor chip. Then, the semiconductor chips are joined by electrically connecting the bumps to each other. Thereby, the step of controlling the TTV can be omitted and the bump bonding can be easily performed.
In the present invention, the above-described cutting technique is also applied to a semiconductor device using a so-called TAB bonding method.
Normally, when the TAB connection is based on the plating bump method, a strip-shaped copper foil lead subjected to gold surface treatment directly on the gold plating bump is aligned and heated to 300 ° C. or higher, and 30 g or more per bump. Requires pressure bonding. On the other hand, in the case of the stud bump method, it is necessary to heat a semiconductor chip on which a stud bump has been formed in advance by pressing it against a glass plate or a metal plate and processing the tip of the stud bump flatly.
The plating end surface has irregularities and metallic and organic contamination peculiar to the surface. In addition, variations in the plating height within the chip occur at a level of several microns. When TAB bonding is performed on these plating end faces, high temperature and high load are required. When a high temperature is used during bonding, a difference in the thermal expansion coefficient between copper and silicon becomes large in connecting fine pitch leads, and thus misalignment is likely to occur. On the other hand, the stud bump has a large variation in height and the shape thereof is not constant, so that a higher temperature and a higher load are required, and it is difficult to connect fine pitches.
In order to reduce misalignment during TAB bonding, it is necessary to lower the temperature and simultaneously contact the copper lead terminals with the bumps. In the present invention, the surface of the plating bump and the stud bump is flattened by cutting using a cutting technique using a cutting tool, thereby reducing the temperature and load at the time of TAB bonding, and the fine pitch lead is not displaced. It becomes possible to connect.
-Specific embodiment of the present invention-
Hereinafter, specific embodiments of the present invention will be described in detail with reference to the drawings based on the basic outline described above.
[First Embodiment]
Here, a silicon semiconductor substrate is exemplified as the substrate, and a method of forming bumps provided on the semiconductor substrate for electrical connection with the outside, a semiconductor device using the method, and a method of manufacturing the same are disclosed. .
(Bump formation method)
1A to 1D, 2A, and 2B are schematic cross-sectional views illustrating the bump forming method according to the present embodiment in the order of steps.
First, a silicon semiconductor substrate 1 is prepared, and a desired LSI semiconductor element (not shown) is formed at an element formation site on the substrate surface 1a. Each step of the semiconductor substrate 1 on which the LSI semiconductor element or the like is formed in the element formation site will be described below.
As shown in FIG. 1A, normally, the silicon semiconductor substrate is not uniform in thickness as shown in the figure, but is in a state accompanied by waviness. Therefore, the back surface 1b is flattened as a pre-process for cutting the surface 1a of the semiconductor substrate 1 using a cutting tool which will be described later.
Specifically, a substrate support base (not shown) having a flat support surface is prepared, and the semiconductor substrate 1 is fixed to the substrate support base by adsorbing the surface 1a to the support surface by, for example, vacuum adsorption. At this time, the surface 1a is forcibly flattened by adsorption to the support surface, and thus the surface 1a becomes a reference surface for flattening the back surface 1b. In this state, the back surface 1b is machined, here, mechanically ground, and the convex portion 1c of the back surface 1b is removed by grinding and flattened. In this case, it is preferable to control the cutting amount of the back surface 1b by the distance from the front surface 1a. As a result, as shown in FIG. 1B, the thickness of the semiconductor substrate 1 is constant, specifically, TTV (specifically, the difference between the maximum thickness and the minimum thickness of the substrate) is a predetermined value or less. It is controlled to 1 μm or less.
Subsequently, as shown in FIG. 1C, the semiconductor substrate 1 is removed from the substrate support, a photosensitive resin, for example, a photoresist is applied onto the surface 1a of the semiconductor substrate 1, and the photoresist is processed by photolithography. A resist mask 12 having a predetermined bump pattern 12a is formed.
Subsequently, using the resist mask 12 as a mask, for example, a metal, for example, a copper film is formed by an evaporation method, and a plating electrode (not shown) is formed. Then, as shown in FIG. Gold (Au) is deposited so as to embed each bump pattern 12a of the resist mask 12, and Au protrusions 2 are formed. In addition, you may form a protrusion using Cu, Ag, Ni, Sn or these alloys other than Au.
Subsequently, the surface 1a of the semiconductor substrate 1 is subjected to a cutting process using a cutting tool and flattened.
Specifically, as shown in FIG. 2A, the back surface 1 b is adsorbed to the support surface 11 a of the substrate support table 11 by, for example, vacuum adsorption, and the semiconductor substrate 1 is fixed to the substrate support table 11. At this time, the thickness of the semiconductor substrate 1 is made constant by the flattening process of FIG. 1B on the back surface 1b, and the back surface 1b is not forcedly swelled by adsorption to the support surface 11a. Thus, the back surface 1b becomes a reference surface for flattening the front surface 1a. In this state, the surface layer of each Au protrusion 2 and the photoresist 12 on the surface 1a is machined, in this case using a cutting tool 10 made of diamond or the like, and the surface of each Au protrusion 2 and the resist mask 12 is continuously formed. A flattening process is performed so as to be flat. Thereby, the upper surface of the Au protrusion 2 is flattened into a mirror surface.
The results of planarization by this cutting process are shown in the micrographs and schematic diagrams of FIGS. 3A and 3B.
Before cutting, the surface of the Au protrusion was uneven as shown in FIG. 3A, whereas after cutting, the surface of the Au protrusion was flattened with high accuracy as shown in FIG. 3B. I know that.
Subsequently, as shown in FIG. 2B, the resist mask 12 is removed by ashing or the like. At this time, on the surface 1 a of the semiconductor substrate 1, bumps 3 having a uniform height, each Au protrusion 2 being cut, and the upper surface 3 a being uniformly flattened are formed. Using this semiconductor substrate 1, for example, after making it into a chip, it is electrically connected to another semiconductor substrate 4 by bumps 3.
In the present embodiment, a single semiconductor substrate has been described. However, it is preferable that the steps of the present embodiment be performed on a plurality of semiconductor substrates constituting a lot so that the thickness of each semiconductor substrate is made uniform. It is.
Further, in the planarization process of FIG. 2A, as shown in FIGS. 4A and 4B, the semiconductor substrate 1 is parallelized with reference to the back surface 1b, and the position of the front surface 1a is detected and shaved from the detected front surface 1a. Calculate and control the amount.
Specifically, as shown in FIG. 4A, when detecting the position of the surface 1a, a plurality of locations around the surface 1a of the semiconductor substrate 1, for example, three locations A, B, and C shown in FIG. It is preferable to irradiate the resist mask 12 with the laser beam 13 to heat and scatter these to expose a part of the surface 1a.
Further, in this case, as shown in FIG. 5, when detecting the position of the front surface 1a, the semiconductor substrate 1 is adsorbed and fixed to the substrate support 11 on which the opening 11b is formed, and infrared laser light is applied from the opening 11b to the back surface 1b. The reflected light from the surface 1a may be measured by, for example, the infrared laser measuring device 14.
(Configuration of cutting device)
Here, the specific apparatus structure for performing the cutting process mentioned above is demonstrated.
FIG. 6 is a block diagram showing the configuration of the cutting apparatus, and FIG. 7 is a similar schematic configuration diagram. The cutting apparatus includes a storage unit 101 for storing a semiconductor substrate, a hand unit 102 for transporting the semiconductor substrate 1 to each processing unit, a sensing unit 103 for positioning the semiconductor substrate 1, and a chuck for the semiconductor substrate 1 at the time of cutting. A chuck table 104, a cutting unit 105 for performing flattening cutting of the semiconductor substrate 1, a cleaning unit 106 for performing cleaning after cutting, and a control unit 107 for controlling them. As described above, the chuck table portion 104 constitutes the substrate support (chuck table) 11 on which the semiconductor substrate 1 is placed and fixed, and the cutting portion 105 has a hard bit 10 that is a cutting tool made of diamond or the like. is doing.
Next, the flow of the cutting process will be described with reference to FIGS.
First, the transport hand of the hand unit 102 takes out the semiconductor substrate 1 from the storage cassette 111 of the storage unit 101 in which the semiconductor substrate 1 is stored. The storage unit 101 has an elevator mechanism that moves up and down to the height at which the semiconductor substrate 1 of the transport hand is taken out. Next, the transport hand vacuum-sucks the semiconductor substrate and transports it to the sensing unit 103. The transport hand is a Θ3-axis and Z-axis scalar robot, and can be easily handled by each processing unit. The robot mechanism is not limited to this, and may be an XY axis orthogonal type.
In the sensing unit 103, the semiconductor substrate 1 is rotated 360 ° by the rotary table 112, the outer periphery of the semiconductor substrate 1 is imaged by the CCD camera 111, and the result is processed by the arithmetic unit of the control unit 107 and the center of the semiconductor substrate 1 is processed. Calculate the position.
Next, based on the result, the transport hand corrects the position and transports the semiconductor substrate 1 to the chuck table unit 104, and the chuck table 11 is fixed by vacuum. This chuck table 11 serves as a processing reference surface. Therefore, in order to maintain the flatness accuracy during fixing and processing, the chuck surface preferably has a structure in which the semiconductor substrate 1 is chucked over the entire surface using a multi-hole material. The material is metal, ceramic, or resin. An optical sensor unit that is a light projecting unit 114 is arranged to face the chucked semiconductor substrate 1, and the dimensions of the semiconductor substrate 1 are measured and calculated together with the camera unit that is the light receiving unit 115, and the result is calculated as X of the cutting unit 105. Feedback to the shaft drive unit and command the amount of movement for cutting.
When the cutting surface is a wiring forming surface, specifically, as shown in FIG. 4, it is preferable to irradiate a laser beam to heat and scatter the resist mask to expose the surface. And as shown in FIG. 5, a position is measured using the transmissive | pervious sensor using an infrared laser beam. Then, based on the result calculated there, the table on which the cutting tool 10 that actually performs cutting moves in the X direction and starts cutting. The cutting tool 10 used here is made of diamond or the like. In this way, the cutting to the set dimension is completed.
Next, the transport hand takes out the semiconductor substrate 1 from the chuck table 11 and transports it to the cleaning unit. In the cleaning unit 105, the semiconductor substrate 1 is vacuum fixed and rotated, and the processed surface residual foreign matter is washed away with cleaning water. After that, it is rotated at a high speed while blowing air, and is dried while blowing off cleaning water. When the drying is completed, the transport hand takes out the semiconductor substrate 1 again and finally stores it in the storage cassette 111 of the storage unit 101.
For each of the above steps, first, the back surface is cut on the basis of the bump and the surface on which the insulating film is formed between the bumps, and then the surface of each bump and the surface of the insulating film are cut on the back surface as a reference, Complete the planarization process.
(Semiconductor device and manufacturing method thereof)
Next, a method of manufacturing a semiconductor device using a semiconductor manufacturing apparatus that executes the above-described bump forming method will be described. Here, the configuration of the semiconductor device is described together with the manufacturing method thereof.
9A to 9C are schematic plan views showing the method for manufacturing the semiconductor device according to the present embodiment in the order of steps.
First, through each step described in FIGS. 1 and 2, an LSI element or the like is mounted, and a semiconductor substrate 1 having bumps 3 whose upper surface 3a is flattened by cutting using a cutting tool is shown in FIG. 9A. Then, each semiconductor chip 21 is cut out.
Subsequently, as shown in FIG. 9B, a semiconductor substrate 22 having bumps 3 whose upper surfaces are flattened by cutting using a cutting tool is prepared, and each semiconductor chip 21 is flattened on the semiconductor substrate 22. The formed upper surfaces 3a are electrically connected to each other. Specifically, the semiconductor substrate 22 and the semiconductor chip 21a are disposed so as to face each other on the upper surface 3a, and are bonded by pressure bonding at room temperature to 350 ° C., here about 170 ° C. Since each upper surface 3a is flattened with high accuracy, the semiconductor substrate 22 and the semiconductor chip 21 can be easily connected without requiring high temperature and high pressure as in the prior art.
Then, as shown in FIG. 9C, each semiconductor chip 23 is cut out from the semiconductor substrate 22 to which the semiconductor chip 21 is connected, and the semiconductor chip is formed on the substrate 24 through a process such as a wire bonding method (connection using the wire 25). 23 is mounted to complete the semiconductor device.
As described above, according to the present embodiment, instead of CMP, the surface of the fine bump 3 formed on the semiconductor substrate 1 is flattened at low speed and at high speed without causing inconvenience such as dishing. 3 can be connected easily and reliably. As a result, the bumps 3 can be connected to each other without requiring conditions such as high temperature and high pressure, and a highly reliable semiconductor device can be manufactured with high yield.
[Second Embodiment]
Next, a second embodiment will be described. In the first embodiment, Au is exemplified as the bump material. However, in this embodiment, a case where nickel (Ni) is used is illustrated.
10A to 10F are schematic cross-sectional views illustrating the bump forming method according to the present embodiment in the order of steps.
First, through the same steps as in FIGS. 1A and 1B of the first embodiment, the semiconductor substrate 1 is ground on the back surface, and the TTL is controlled to a predetermined value or less, specifically to 1 μm or less.
Using this semiconductor substrate 1, as shown in FIG. 10A, after patterning an electrode 31 made of an aluminum metal on the surface of the semiconductor substrate 1, a nickel phosphor plating film 32 is formed on the electrode 31 by an electroless plating method to a thickness of 5 μm. It is formed to about 10 μm.
The nickel phosphorous plating film 32 is formed using nickel-phosphorus, nickel-phosphorus-boron, nickel-boron or the like by a general electroless plating method. For example, a nickel-phosphorus alloy is formed in a hypophosphorous acid bath (sodium hypophosphite or potassium hypophosphite), and a nickel-boron alloy is used in a weakly acidic bath or medium using a sodium borohydride bath or dimethylaminoborane. The nickel-phosphorus-boron alloy is formed with a neutral bath.
Here, in nickel-phosphorus electroless plating, a phosphorus-enriched layer 33 that is a mechanical fragile layer is formed on the surface layer of the nickel-phosphorous plating film 32 regardless of which alloy system is selected. After the formation of the solder bump, the phosphorus concentrated layer causes the interface strength between the plating and the solder bump to decrease. The thickness of this phosphorus concentration layer is about 20 nm to 40 nm, and becomes thicker as the phosphorus content in the plating bath increases.
The phosphorus enriched layer is generated regardless of the underlying material (glass substrate, iron substrate, aluminum substrate) and regardless of the plating thickness. Further, even if nickel-based electroless plating as described in Patent Document 6, for example, is annealed to a temperature higher than the solder melting point, a phosphorus-enriched layer is always generated on the surface layer. Unless the phosphorus-enriched layer is removed, it is difficult to form a highly reliable plating film and solder bump.
Regarding these problems, there is a method in which a copper-nickel-tin compound layer is formed by adding copper to the solder material, and the formation of a phosphorus-enriched layer is suppressed by its barrier effect. However, when the Au plating thickness is 500 nm or more, there is a problem that the limitation of the Au plating thickness and the selectivity of the solder material are narrowed, such as the formation of a phosphorus concentrated layer.
Therefore, in this example, at the time of flattening the nickel phosphorus plating film 32 by cutting, the phosphorus concentrated layer 33 is removed at the same time.
Specifically, as shown in FIG. 10B, first, a liquid resist is coated as a protective film 34 so as to cover the substrate surface to form a physical impact mitigation layer by a cutting process described later. The protective film 34 is formed by applying and curing to a thickness of about 10 μm to 15 μm by spin coating or the like.
Thereafter, as in FIG. 2A, the back surface is adsorbed on the support surface of the substrate support table by, for example, vacuum suction, and the semiconductor substrate 1 is fixed to the substrate support table. At this time, the thickness of the semiconductor substrate 1 is made constant by the flattening process of FIG. 1B on the back surface 1b, and the back surface 1b is not forcedly swelled by adsorption to the support surface 11a. Thus, the back surface 1b becomes a reference surface for flattening the front surface 1a. In this state, as shown in FIG. 10C, the surface layers of the nickel phosphorous plating film 32 and the protective film 34 on the surface 1a are machined, and in this case, cutting is performed using a cutting tool made of diamond or the like. The phosphorus concentration layer 33 is removed, and a flattening process is performed so that the surfaces of the nickel phosphorus plating film 32 and the protective film 34 are continuously flat. The cutting amount is set to about 1 μm to 2 μm so that the phosphorus concentrated layer 33 can be reliably removed.
Subsequently, as shown in FIG. 10D, a gold plating film 35 is formed on the nickel phosphorous plating film 32 by an electroless plating method as necessary. The thickness of the gold plating film 35 is preferably about 30 nm to 50 nm.
Subsequently, as shown in FIG. 10E, the protective film 34 is removed by ashing or the like. At this time, on the surface 1 a of the semiconductor substrate 1, bumps 36 are formed which are uniform in height, are uniformly flattened by cutting, and are formed with a gold plating film 35.
Then, as necessary, solder bumps 37 are formed on the bumps 36 as shown in FIG. 10F. The solder bumps 37 are formed by screen printing, a solder ball method, melting, or the like. As a material for the solder, it is desirable to use a lead-free solder such as tin-silver or tin-zinc.
Thereafter, the semiconductor substrate 1 is divided by full-cut dicing to cut out a semiconductor chip, and the semiconductor device is completed as in the first embodiment.
As described above, according to the present embodiment, instead of CMP, the surface of the nickel bump 36 formed on the semiconductor substrate 1 is flattened at low speed and at high speed without causing inconvenience such as dishing. Therefore, it is possible to connect the bumps 36 without requiring conditions such as high temperature and high pressure, and a highly reliable semiconductor device can be manufactured with a high yield. In addition, since the phosphorus-enriched layer 34 that lowers the reliability at the joint portion between the bump 36 and the solder bump 37 can be completely removed at low cost, the solder bump 37 is reliably formed on the bump 36 whose upper surface is flattened. It becomes possible.
[Third Embodiment]
Next, a third embodiment will be described. In the first embodiment, the case where a large number of semiconductor chips are bonded to the semiconductor substrate is illustrated. However, in the present embodiment, the above-described planarization process is performed in the state of the semiconductor chip, and the semiconductor chips are bonded to each other. Disclose.
11A and 11B are schematic cross-sectional views showing the method of manufacturing the semiconductor device according to the present embodiment in the order of steps.
First, as shown in FIG. 11A, a plurality of bumps, which are mounted with LSI elements and have different heights (there are still variations in height), here Au bumps, without the back surface grinding of the first embodiment. Individual semiconductor chips 41 are cut out from the semiconductor substrate on which 42 is formed.
Subsequently, the surface layer of the semiconductor chip 41 is machined. Here, the surface of each Au bump 42 is flattened by cutting using a cutting tool made of diamond or the like as in the first embodiment. Process. Thereby, the height of each Au bump 42 is made uniform, and the upper surface is flattened into a mirror surface.
Subsequently, as shown in FIG. 11B, the pair of semiconductor chips 41 are opposed to each other, and the two flattened upper surfaces of the Au bumps 42 are electrically connected to each other. Specifically, a pair of semiconductor chips 41 are arranged so as to face each other, and are bonded by pressure bonding at room temperature to 350 ° C., here about 170 ° C. Since each upper surface is flattened with high accuracy, a pair of semiconductor chips 41 can be easily connected without requiring high temperature and high pressure as in the prior art.
As described above, according to the present embodiment, instead of CMP, the surface of the fine Au bump 42 formed on the semiconductor chip 41 is flattened at low speed and at high speed without causing inconvenience such as dishing. It becomes possible to connect the Au bumps 42 in the semiconductor chip 41 easily and reliably. Thereby, the Au bumps 42 can be connected to each other without requiring conditions such as high temperature and high pressure, and a highly reliable semiconductor device can be manufactured with high yield. In addition, since the above-described cutting process is performed after cutting into individual semiconductor chips 41 from the semiconductor substrate, the step of controlling the TTV can be omitted, which contributes to a reduction in the number of steps.
[Modification 1]
Here, the modification 1 of this embodiment is demonstrated.
12A to 12C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to Modification 1 in the order of steps.
First, as shown in FIG. 12A, a plurality of bumps, which are mounted with LSI elements and having different heights (there are still variations in height), here Au bumps, without grinding the back surface of the first embodiment. Individual semiconductor chips 41 are cut out from the semiconductor substrate on which 42 is formed.
Subsequently, a resin layer 43 made of an insulating material is formed so as to embed Au bumps 42 on the surface of the semiconductor chip 41. In addition, after forming the resin layer 43 so as to embed the Au bumps 42 in the state of the semiconductor substrate, the individual semiconductor chips 41 may be cut out.
Subsequently, as shown in FIG. 12B, the surface layer of the semiconductor chip 41 is machined, here, similarly to the first embodiment, cutting is performed using a cutting tool made of diamond or the like, and the surface of each Au bump 42 and the resin layer The surface of 43 is flattened so as to be continuously flat. Thereby, the height of each Au bump 42 is made uniform, and the upper surface is flattened into a mirror surface.
Subsequently, the pair of semiconductor chips 41 are made to face each other, and the Au bumps 42 and the resin layer 43 are electrically connected to each other on the flattened upper surfaces. Specifically, a pair of semiconductor chips 41 are arranged so as to face each other, and are bonded by pressure bonding at room temperature to 350 ° C., here about 170 ° C. Since each upper surface is flattened with high accuracy, a pair of semiconductor chips 41 can be easily connected without requiring high temperature and high pressure as in the prior art. Further, the resin film 43 ensures the bonding of the pair of semiconductor chips 41 and contributes as an underfill for protecting the electrodes 42 and the like.
As described above, according to the first modification, instead of CMP, the surface of the fine Au bump 42 formed on the semiconductor chip 41 is flattened at low speed and at high speed without causing inconvenience such as dishing. It becomes possible to connect the Au bumps 42 in the semiconductor chip 41 easily and reliably. Thereby, the Au bumps 42 can be connected to each other without requiring conditions such as high temperature and high pressure, and a highly reliable semiconductor device can be manufactured with high yield. In addition, since the above-described cutting process is performed after cutting into individual semiconductor chips 41 from the semiconductor substrate, the step of controlling the TTV can be omitted, which contributes to a reduction in the number of steps.
[Modification 2]
Next, a second modification of the present embodiment will be described.
13A to 13C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to Modification 2 in the order of steps.
First, as shown in FIG. 13A, a plurality of bumps having different heights (having variations in height) (here, Au bumps) mounted with LSI elements or the like without the back surface grinding of the first embodiment. Individual semiconductor chips 41 are cut out from the semiconductor substrate on which 42 is formed.
Subsequently, the surface layer of the semiconductor chip 41 is machined, here, as in the first embodiment, cutting is performed using a cutting tool made of diamond or the like so that the surface of each Au bump 42 is continuously flat. Perform flattening. Thereby, the height of each Au bump 42 is made uniform, and the upper surface is flattened into a mirror surface.
Subsequently, as shown in FIG. 13B, the planarized semiconductor chips 41 are paired into a pair of semiconductor chips 41, and the insulating bumps are formed so that the Au bumps 42 are completely embedded in the surface of one of the semiconductor chips 41. The resin layer 44 containing the conductive fine particles 45 is formed on the conductive resin.
Subsequently, the pair of semiconductor chips 41 are opposed to each other, and the planarized upper surfaces of the Au bumps 42 are electrically connected to each other. Specifically, the pair of semiconductor chips 41 are disposed so as to face each other on the upper surface, and are bonded at room temperature to 350 ° C., here about 170 ° C. Here, the opposing Au bumps 42 are brought into contact with each other through the conductive fine particles 45 by thermocompression bonding, and are electrically connected. Since each upper surface is flattened with high accuracy, a pair of semiconductor chips 41 can be easily connected without requiring high temperature and high pressure as in the prior art. Further, the resin of the resin layer 44 ensures adhesion and electrical connection between the pair of semiconductor chips 41 and contributes as an underfill for protecting the electrodes 42 and the like.
Thus, according to the second modification, instead of CMP, the surface of the fine Au bump 42 formed on the semiconductor chip 41 is flattened at low speed and at high speed without causing inconvenience such as dishing. It becomes possible to connect the Au bumps 42 in the semiconductor chip 41 easily and reliably. Thereby, the Au bumps 42 can be connected to each other without requiring conditions such as high temperature and high pressure, and a highly reliable semiconductor device can be manufactured with high yield. In addition, since the above-described cutting process is performed after cutting into individual semiconductor chips 41 from the semiconductor substrate, the step of controlling the TTV can be omitted, which contributes to a reduction in the number of steps.
[Fourth Embodiment]
Next, a fourth embodiment will be described. In the first embodiment, the case where bumps for external connection are formed on the semiconductor substrate is illustrated. However, in the present embodiment, the case where stud bumps using a wire bonding method are formed is disclosed.
14A to 14F are schematic cross-sectional views showing the method of manufacturing the semiconductor device according to the present embodiment in the order of steps.
First, as shown in FIGS. 14A and 14B, as in FIG. 1A, the back surface of the semiconductor substrate 51 on which the LSI semiconductor elements and electrode pads are formed at the element formation site is ground, and the thickness of the semiconductor substrate 51 is kept constant. Specifically, the TTV (difference between the maximum thickness and the minimum thickness of the substrate) is controlled to 1 μm or less.
Here, in the grinding step, after the back surface of the semiconductor substrate 51 is ground, a metal film, for example, an Al film is formed on the semiconductor substrate 51 by a sputtering method or the like, and this is patterned, so that the electrical connection locations The electrode pad 52 may be formed at a portion to be formed.
Subsequently, as shown in FIG. 14C, after a ball-shaped lump formed by melting the tip of an Au bonding wire having a diameter of 20 μm, for example, is bonded onto the electrode pad 52 by a wire bonding method using Au as a metal, The wire is torn off (pre-cut), and Au protrusions 53 are formed on the electrode pads 52. At this time, the height of each Au protrusion 53 from the electrode pad 52 is defined to be at least twice the diameter of the bonding wire, here about 60 μm. In this case, the height of the Au protrusion 53 actually varies, and it may be about 50 μm to 60 μm.
Subsequently, as shown in FIG. 14D, cutting is performed using a cutting tool 10 made of diamond or the like, and a flattening process is performed so that the upper surface of each Au protrusion 53 is continuously flat, thereby forming a stud bump 54. Here, the cutting position is set to a height of, for example, about 50 μm from the electrode pad 52. The cutting conditions are a cutting speed of 10 m / s, a feed per stroke of about 20 μm, and a 2 μm drive from the initial cutting position. As a result, as shown in FIG. 14E, the upper surface of the Au protrusion 53 is flattened into a mirror surface, and the stud bump 54 is formed.
This flattening method by cutting does not require a slurry or the like as compared with CMP, and the cutting tool, which is a cutting tool, is worn and polished so that it can be used repeatedly, so that the cost is low. The semiconductor substrate chucked on the chuck table is rotated at a high speed, and then the cutting tool is moved at a predetermined speed to cut an arbitrary cutting amount at a time. Therefore, it can be completed in 1 to 2 minutes per semiconductor substrate. There is a very high throughput method. When cutting with a bite, by making the cutting conditions appropriate, even when stud bump projections using Au bonding wire are cut at the tip of the projection, flattening without tilting or bending of the projection can be achieved. Is possible. However, if the hardness is 30 Hv or less, the protrusions may be inclined during cutting. Therefore, the hardness of the wire is preferably 30 Hv or more.
In the present embodiment, the end point of the cutting process is the time when the diameter of the cutting surface is equal to or greater than the wire diameter for all stud bumps. Normally, stud bumps vary greatly in height after pre-cutting, and it is difficult to confirm that the diameter of the cutting surface is equal to or greater than the wire diameter in all stud bumps. As a cutting method, it is appropriate to drive the cutting tool by 1 to 3 μm from the point where the cutting tool comes into contact with the highest bump and bring out the cutting surfaces of all the cutting tools. Is inefficient.
Therefore, in the present embodiment, as shown in FIG. 15A, as a method for detecting the end point, a detection apparatus including a laser transmitter 61 and a detector 62 is used to operate a laser beam on the upper surface of the stud bump 54 after cutting. A method of detecting the laser reflected by the upper surface with the detector 62 is adopted.
Then, as shown in FIG. 15B, the processing is repeated until the detected laser intensity reaches a predetermined intensity at all the Au protrusions 53. It is desirable that this detection device is installed behind the cutting tool in the traveling direction and proceeds in synchronization with the cutting tool. Since the upper surface (cutting surface) of the stud bump 54 is substantially a mirror surface, the laser beam or the like is totally reflected. When synchronized with the cutting tool, a delay is generated in proportion to the traveling speed of the cutting tool. Therefore, strictly speaking, not all reflected light is detected, but the cutting speed is 10 tens m / s at the fastest. Therefore, it can be considered that it is almost detected.
In the present embodiment, the laser transmitter 61 and the detector 62 moving in synchronization with the progress of the cutting tool from the rear part of the cutting tool are driven while measuring the intensity of the laser beam reflected from the upper surface of the flattened Au protrusion 53. For example, it was detected that the upper surfaces of all the Au protrusions 53 were exposed at a height of 46 μm, and the cutting was finished.
Here, as shown in FIG. 15C, when the cutting process is insufficient, or when the diameter of the cutting surface is equal to or less than the wire diameter, the laser light hitting a place other than the cutting surface is irregularly reflected, and the detector Not detected. Therefore, as shown in FIG. 15D, the detected laser light intensity is weaker than the surface cut to the same diameter as the bonding wire. When such a stud bump is confirmed even at one place, it is automatically driven further by about 1 μm to 2 μm and finally cut until a laser light intensity of a certain amount or more is detected in all the bumps. Thereby, connection failure due to uncut or insufficient cutting can be prevented, and the processing time can be greatly shortened.
Then, as shown in FIG. 14F, each semiconductor chip 55 is cut out from the semiconductor substrate 51, and the semiconductor chip 55 and the circuit board 56 are connected by, for example, a flip chip method. Specifically, the stud bump 54 whose surface is flattened on the semiconductor chip 55 and the electrode 57 formed on the surface of the circuit board 56 are brought into contact with each other, and both are bonded by pressure and heating. In this case, like the stud bump 54, the electrode 57 of the circuit board 56 is also preferably made to be flip-chip connected after being flattened by the above-described cutting process.
As described above, according to the present embodiment, instead of CMP, the surface of the fine stud bump 54 formed on the semiconductor substrate 51 is flattened at a low speed without causing any inconvenience such as dishing, The stud bump 54 can be easily and reliably connected. As a result, the bumps can be connected without requiring conditions such as high temperature and high pressure, and a highly reliable semiconductor device can be manufactured with high yield. Moreover, the height of the stud bump 54 after the flattening of the cutting can be made 1.5 times or more compared with the case where the wire diameter is not specified, and the stress on the semiconductor element can be relaxed, and the device life Can be extended. Furthermore, since the flat surface in cutting is equal to or greater than the wire diameter, it is possible to obtain a bonding strength that is twice or more even with the same wire diameter. In addition, when a bonding strength comparable to the conventional one is sufficient, the wire diameter can be reduced, so that the bump pitch can be reduced and the cost for the bonding wire can be reduced.
[Fifth Embodiment]
Next, a fifth embodiment will be described. Here, a semiconductor device by a so-called TAB bonding method is illustrated.
16 and 17 are schematic cross-sectional views illustrating the method for fabricating the semiconductor device according to the present embodiment.
In order to manufacture this semiconductor device, first, similarly to the first embodiment, the steps shown in FIGS. 1 and 2 are performed, and then on the electrode 71 of the semiconductor substrate 1 on which an LSI semiconductor element or the like is formed at the element formation site. In addition, bumps 3 having a uniform height and a flat top surface 3a are formed by cutting each Au protrusion 2 through the underlying metal film 72. Here, an insulating protective film 73 is formed around the bump 3 of the semiconductor substrate 1.
Subsequently, an electrical characteristic of the semiconductor element or the like of the semiconductor substrate 1 is inspected by bringing a probe into contact with the upper surface of the bump 3. Here, conventionally, since the probe is brought into contact with bump end surfaces and contaminated plating end surfaces at the time of the inspection, stable contact cannot be obtained, and the tip of the probe is caught and damaged at the uneven portion. There was also a trouble. On the other hand, in this embodiment, since the probe is brought into contact with the surface of the bump 3 highly flattened and cleaned by the above-described cutting process, the inspection can be performed in an extremely stable state.
Subsequently, after the individual semiconductor chips 21 are cut out from the semiconductor substrate 1, the semiconductor chips 21 are connected by the TAB bonding method as shown in FIG.
Specifically, the Au film 76 is formed of the copper foil 75 and is subjected to the surface treatment of Au, the portion located at one end corresponds to the connection site, and the resin layer 77 is provided at the other end. A TAB lead 74 is prepared. Then, the semiconductor chip 21 is placed and fixed on the bonding stage 80, and the Au film 76 at the connection portion of the TAB lead 74 is brought into contact with the flattened and cleaned upper surface of the bump 3 by the heater 78. Pressurize while heating to join them together. Here, the heating temperature may be a relatively low temperature of about 200 ° C., and the adhesion load can be reduced to about 2/3 of the conventional one, about 20 g. As a result, it is possible to connect TAB leads having a fine pitch of 40 μm or less without displacement.
Thereafter, as shown in FIG. 17, the semiconductor chip 21 is removed from the bonding stage 80, and a sealing resin 79 is formed so as to cover the surface of the semiconductor chip 21 including the connection portion between the bump 3 and the TAB lead 74. Complete the device.
In the present embodiment, the case where the plating bump is formed as the bump is exemplified, but the stud bump may be formed by a wire bonding method.
As described above, according to the present embodiment, instead of CMP, the surface of the fine bump 3 formed on the semiconductor substrate 1 is flattened at low speed and at high speed without causing inconvenience such as dishing. 3 can be connected easily and reliably. As a result, it is possible to reliably connect the bump and the lead terminal without requiring conditions such as high temperature and high pressure, and it is possible to manufacture a highly reliable TAB bonding type semiconductor device with a high yield.
[Sixth Embodiment]
Next, a sixth embodiment will be described. Here, when executing the above-described embodiments, an apparatus for executing the above-described cutting process and joining process for a pair of bases (here, a semiconductor chip and a circuit board by a flip chip method are illustrated). The configuration is disclosed.
FIG. 18 is a schematic diagram showing the semiconductor manufacturing apparatus according to the present embodiment.
This semiconductor manufacturing apparatus includes a chip introducing portion 81 for introducing a semiconductor chip having bumps formed on the surface, a circuit substrate introducing portion 82 for introducing a circuit substrate having electrodes formed on the surface, and the above-described bite. A cutting portion 83 for performing a step of flattening the bump surface of the semiconductor chip by cutting using a chip, and a bonding portion 84 for performing a step of bonding the semiconductor chip and the circuit board with the flattened bump and electrode. And a carry-out portion 85 for carrying out the joined and integrated semiconductor device, and further includes a cleaning holding portion 86 including the cutting portion 83 and the joint portion 84 in an inert atmosphere. Has been. Here, in the cutting part 83, not only the semiconductor chip but also the electrode surface of the circuit board may be flattened by cutting.
The cleaning holding portion 86 performs both the flattening process and the bonding process in a cleaning atmosphere, specifically in an inert atmosphere, for example, Ar or N ₂ It has a function of maintaining in a gas phase not containing oxygen, or in an atmosphere containing oxygen of 1 atm or less. This makes it possible to maintain a flat state that is very close to the ideal relatively easily without adding a cleaning process using Ar plasma or the like immediately before the bonding process, and enables reliable bonding of bumps and electrodes. It becomes.
In the present embodiment, the flip chip mounting is exemplified. However, the present invention is not limited to this, and the present invention is also suitable for joining a semiconductor chip and a semiconductor wafer, semiconductor chips, or the like.

  According to the present invention, instead of CMP, the surface of fine bumps formed on a substrate is flattened inexpensively and at high speed, and the bumps are connected easily and reliably without causing problems such as dishing. Is possible.

  The present invention relates to a method for forming fine bumps for electrical connection to the outside on the surface of a substrate, a semiconductor device and a manufacturing method thereof, and a substrate processing apparatus and a semiconductor manufacturing apparatus.

  Conventionally, gold (Au) bumps or the like are used for fine metal terminals in order to make electrical connection with the outside on the surface of a semiconductor substrate. The Au bump is formed by plating and has a large surface roughness. In order to planarize such a metal terminal, a chemical mechanical polishing (CMP) method is used. In this method, a metal and a resin to be processed are formed in a relatively flat state in advance, a flat polishing pad is pressed against the surface, and the surface is precisely and mechanically flattened using a slurry (chemical abrasive). To be processed. The hard resin or metal surface provided in advance serves as a stop layer, and CMP is completed. The CMP method is a method that does not depend on TTV (Total Thickness Variation) defined by the variation in the thickness of the semiconductor substrate or the difference between the maximum thickness and the minimum thickness of the semiconductor substrate.

  In addition, the conventional bonding of Au bumps or the like having a large surface roughness requires a mounting method in which a load is applied to the bumps by a load, heat, ultrasonic waves, or the like until the roughness is eliminated.

  In addition to CMP, for example, several planarization methods using a cutting tool have been devised (see, for example, Patent Documents 1 to 4). However, both are intended for flattening the SOG film in a partial region on the LSI, and, like CMP, are methods based on the surface to be cut and do not depend on the TTV of the semiconductor substrate. There is also a method of exposing the surface by cutting the bump (see Patent Document 4), but this is intended for flattening the bump portion formed on the LSI, and is a method of cutting based on the surface to be cut. Thus, it does not depend on the TTV of the semiconductor substrate.

JP 7-326614 A JP-A-8-11049 Japanese Patent Laid-Open No. 9-82616 Japanese Patent Application Laid-Open No. 2000-173954

  As described above, Au bumps are used for fine connection, but it is difficult to join the bumps due to the large roughness of the bump surface. In addition, when a metal such as Au and a resin are simultaneously planarized using CMP, a recess called dishing appears due to a difference in polishing rate between the metal and the resin. In order to obtain reliable bump bonding by this dishing, it is necessary to apply a large load such as a load, heat, or ultrasonic waves to the bump.

  The present invention has been made in view of the above problems, and instead of CMP, the surface of fine bumps formed on a substrate is flattened at low speed and at high speed, and the bumps are connected with each other with inconvenience such as dishing. It is an object of the present invention to provide a bump forming method, a highly reliable semiconductor device, a manufacturing method thereof, and a semiconductor manufacturing device that can be easily and reliably performed without being generated.

  The bump forming method of the present invention is a method of forming a bump for electrical connection to the outside on the surface of a substrate, and forming a plurality of the bumps and an insulating film between the bumps on the surface of the substrate A step of performing a flattening process so that the surface of each bump and the surface of the insulating film are continuously flattened by cutting using a cutting tool, and a step of removing the insulating film.

  Each of the semiconductor devices of the present invention has a pair of semiconductor substrates on which a plurality of bumps for electrical connection with the outside are formed, and the surface of each bump is cut using a cutting tool. Each of the semiconductor substrates is flattened continuously and uniformly by processing, and each of the semiconductor substrates is formed by connecting and planarizing the flattened surfaces of the bumps so as to be integrated. .

  The method for manufacturing a semiconductor device of the present invention includes a step of forming each bump so as to be embedded in an insulating film on each surface of a pair of semiconductor substrates, and a cutting process using a cutting tool. The step of planarizing the surface of the insulating film so as to be continuously flat, the step of removing the insulating film, and the respective semiconductor substrates, with the flattened surfaces of the respective bumps facing each other Connecting and integrating.

  The bump forming method of the present invention is a method for forming a bump for electrical connection to the outside on the surface of the substrate, wherein a plurality of bumps are formed on the surface of the substrate, and a cutting tool is used. And a step of flattening so that the surfaces of the plurality of bumps are continuously flat by cutting.

  According to the method of manufacturing a semiconductor device of the present invention, the surface of the plurality of bumps is continuously flat by a step of forming the plurality of bumps on each surface of a pair of semiconductor chips and a cutting process using a cutting tool. And a step of connecting and integrating the pair of semiconductor chips in which the surfaces of the plurality of bumps are flattened so that the bumps face each other.

  Each of the semiconductor devices of the present invention has a pair of semiconductor chips formed on the surface with a plurality of bumps for electrical connection with the outside, and the surface of each bump is cut using a cutting tool. Each of the semiconductor chips is flattened continuously and uniformly by processing, and the semiconductor chips are formed by connecting the flattened surfaces of the bumps facing each other and integrating them. .

  The bump forming method of the present invention is a bump for electrical connection to the surface of a semiconductor substrate, and is a method of forming a stud bump using a wire bonding method. Forming a plurality of protrusions using a bonding wire at a target connection location and cutting using a cutting tool so that the upper surfaces of the plurality of protrusions are continuously flattened, and the stud Forming a bump.

  The semiconductor device of the present invention is a bump for electrical connection with the outside, and has a semiconductor chip formed on the surface with a plurality of stud bumps using a wire bonding method. The upper surface is continuously flattened on the semiconductor chip by cutting using a cutting tool.

  The method for manufacturing a semiconductor device according to the present invention includes a step of forming a plurality of bumps on a surface of a semiconductor substrate and a cutting process using a cutting tool so that the surfaces of the plurality of bumps are continuously flattened. A step of cutting out each semiconductor chip from the semiconductor substrate on which the surfaces of the plurality of bumps are flattened, and a step of connecting the bumps of the semiconductor chip and one end of a lead terminal.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming a plurality of protrusions using a wire bonding method at an electrical connection location on the surface of a semiconductor substrate, and a cutting process using a cutting tool. A step of flattening the upper surface continuously to be flat and forming a stud bump, a step of cutting each semiconductor chip from the semiconductor substrate on which a plurality of stud bumps are formed, and the stud of the semiconductor chip Connecting the bump and one end of the lead terminal.

  The semiconductor device of the present invention has a semiconductor chip on which a plurality of bumps for electrical connection with the outside are formed, and the surface of each bump is continuously uniform on the semiconductor chip. The bumps of the semiconductor chip and one end of the lead terminal are connected and integrated.

  The semiconductor device of the present invention includes a plurality of bumps for electrical connection with the outside, and includes a semiconductor chip having a plurality of stud bumps formed on the surface using a wire bonding method. The surface of the bump is continuously flattened on the semiconductor chip, and the stud bump of the semiconductor chip and one end of the lead terminal are connected and integrated.

  According to the method for manufacturing a semiconductor device of the present invention, a semiconductor chip having a plurality of electrodes formed on a surface thereof is introduced into an inert atmosphere, and the surface of the plurality of electrodes is continuously flat by cutting using a cutting tool. A step of planarizing so that the surfaces of the planarized electrodes are kept clean in the inert atmosphere, and the circuit board is connected to the plurality of electrodes of the semiconductor chip. And integrating them.

  The semiconductor manufacturing apparatus of the present invention includes a cutting means having a cutting tool, a joining means for joining a pair of introduced substrates, and an inert atmosphere that maintains the environment of the cutting means and the joining means in an inert atmosphere. The cutting means includes, in the inert atmosphere, cutting the plurality of the plurality of electrodes, wherein the plurality of electrodes are formed on the surface by cutting using the cutting tool. The bonding means has a function of flattening so that the surfaces of the electrodes are continuously flat, and the bonding means is in a state where the surfaces of the flattened electrodes are kept clean in the inert atmosphere. The pair of substrates are connected by the plurality of electrodes and integrated.

  The substrate processing apparatus of the present invention is a substrate processing apparatus for forming bumps for electrical connection to the outside on the surface of the substrate, and has a flat support surface, and the substrate is disposed on the one surface thereof. A substrate support base that is adsorbed to a support surface and forcibly supports and fixes the one surface as a flat reference surface; and a cutting tool that cuts the other surface of the substrate. A substrate on which an insulating film is formed is supported and fixed on the substrate support, and the surface of each bump and the surface of the insulating film are continuously flattened by cutting using the cutting tool. To do.

  According to the present invention, instead of CMP, the surface of fine bumps formed on a substrate is flattened inexpensively and at high speed, and the bumps are connected easily and reliably without causing problems such as dishing. Is possible.

-Basic outline of the present invention-
First, the basic outline of the present invention will be described.
The present inventor has come up with the idea of applying cutting using a cutting tool as a technique for simultaneously flattening the surface of a large number of fine bumps formed on a substrate at a low cost and at a high speed instead of the CMP method. According to this cutting process, even when a bump is embedded in an insulating film on a semiconductor substrate, it does not depend on the polishing rate of the metal and the insulator as in the CMP method, and can be performed simultaneously on the substrate. In addition, the metal and the insulator can be continuously cut, and both can be uniformly flattened without causing dishing or the like. Metals such as copper, aluminum, and nickel, and insulating materials such as polyimide are materials that can be easily cut with a cutting tool. In the present invention, as the metal material and insulating material of the bump, it is preferable that the former is a ductile metal and the latter is a resin having a rigidity of, for example, 200 GPa or more.

  In this case, in order to use the above-described cutting process for the flattening of the bump surface, it is preferable to perform the cutting on the basis of the back surface (back surface) of the substrate. In general, the TTV of a silicon substrate is in the range of 1 μm to 5 μm. In the LSI process, a TTV of about 5 μm does not affect photolithography and is usually not considered. However, in the case of cutting, it is greatly influenced by the value of TTV. Flatness accuracy by cutting does not fall below the TTV value. Therefore, when cutting is used for flattening a semiconductor substrate, it is first necessary to control the TTV of the substrate to a target cutting accuracy or less.

  In consideration of the above circumstances, the present inventor, when using the above-described cutting process for the flattening of the bump surface, as a specific method for reliably performing the flattening, grinding the back surface with respect to the substrate surface, The present inventors have conceived that the TTV of the semiconductor substrate is kept below the target cutting accuracy. In this case, it is ideal that the TTV is made small and the thickness variation of each semiconductor substrate is suppressed to below the cutting accuracy. However, as long as the TTV can be reduced, the thickness of each semiconductor substrate can be detected during cutting. The amount of cutting can be controlled by detecting the thickness of each individual semiconductor substrate.

  In addition to the bumps formed by plating, the bumps are formed by wire bonding, that is, bumps formed by melting the tip of the bonding wire on the electrode pad and tearing the wire. (Hereinafter referred to as a stud bump).

  When the stud bump is formed, a pin-shaped protrusion is formed by tearing of the bonding wire, and it is necessary to flatten the protrusion. In the present invention, the above-described flattening method by cutting is also applied to the stud bump. In this case, when the wire is torn (pre-cut), the height of each projection is different and flattened to align with the lowest bump, but the higher the stud bump height, the less stress on the device, Since the device life can be extended, it is necessary to define the height of each protrusion. In the present invention, the height from the electrode pad of the protruding portion at the time of pre-cut is specified to be twice or more of the wire diameter, and the cutting surface diameter is equal to or more than the wire diameter for all stud bumps as the end point of the cutting process. It becomes the time when it became. As a result, the height of the stud bump after the flattening of cutting can be made 1.5 times or more compared to the case where the wire diameter is not specified, and the stress on the semiconductor element can be relaxed, and the device life Can be extended.

  And after controlling TTV as mentioned above and planarizing the surface of a fine bump by cutting, each semiconductor chip used as a semiconductor component is cut out from a semiconductor substrate (wafer). Thereafter, the semiconductor substrate having a planarized surface and the semiconductor chip, or the semiconductor chips are electrically connected with the bumps facing each other and bonded. At this time, since the upper surfaces of the opposing bumps are both flattened with high precision, they can be easily joined without requiring high temperature and high pressure as in the prior art.

  Here, the inventor further sought specific conditions and states for reliably realizing the bonding between the bumps facing each other. Considering that it is ideal to keep the bumps in the flattened state immediately after the cutting process even during the above-mentioned bonding, both the flattening process and the bonding process are performed in order to keep the flattened state immediately after the cutting process as much as possible. It was conceived to carry out in a cleaning atmosphere, specifically in an inert atmosphere. Although this point can be dealt with by adding a cleaning step using Ar plasma or the like immediately before the bonding step, there is a drawback that the number of steps increases. In the present invention, a planarized state that is extremely close to the ideal can be maintained relatively easily without causing an increase in the number of steps, and the bumps can be reliably bonded.

  The inventor pays attention to the state of the semiconductor chip as another aspect of the present invention. In other words, at the wafer level, the TTV of the semiconductor substrate becomes a problem as described above. However, since the size of individual chips such as semiconductor chips is small, the TTV in the chip area is almost not at the time of cutting. Only a negligible influence is received.

  Therefore, the present inventor has first conceived that after cutting each semiconductor chip from the semiconductor substrate, the surface of the fine bump is flattened by cutting using the above-described bump in the state of the semiconductor chip. Then, the semiconductor chips are joined by electrically connecting the bumps to each other. Thereby, the step of controlling the TTV can be omitted and the bump bonding can be easily performed.

In the present invention, the above-described cutting technique is also applied to a semiconductor device using a so-called TAB bonding method.
Normally, when the TAB connection is based on the plating bump method, a strip-shaped copper foil lead subjected to gold surface treatment directly on the gold plating bump is aligned and heated to 300 ° C. or higher, and 30 g or more per bump. Requires pressure bonding. On the other hand, in the case of the stud bump method, it is necessary to heat a semiconductor chip on which a stud bump has been formed in advance by pressing it against a glass plate or a metal plate and processing the tip of the stud bump flatly.

  The plating end surface has irregularities and metallic and organic contamination peculiar to the surface. In addition, variations in the plating height within the chip occur at a level of several microns. When TAB bonding is performed on these plating end faces, high temperature and high load are required. When a high temperature is used during bonding, a difference in the thermal expansion coefficient between copper and silicon becomes large in connecting fine pitch leads, and thus misalignment is likely to occur. On the other hand, the stud bump has a large variation in height and the shape thereof is not constant, so that a higher temperature and a higher load are required, and it is difficult to connect fine pitches.

  In order to reduce misalignment during TAB bonding, it is necessary to lower the temperature and simultaneously contact the copper lead terminals with the bumps. In the present invention, the surface of the plating bump and the stud bump is flattened by cutting using a cutting technique using a cutting tool, thereby reducing the temperature and load at the time of TAB bonding, and the fine pitch lead is not displaced. It becomes possible to connect.

-Specific embodiment of the present invention-
Hereinafter, specific embodiments of the present invention will be described in detail with reference to the drawings based on the basic outline described above.

[First Embodiment]
Here, a silicon semiconductor substrate is exemplified as the substrate, and a method of forming bumps provided on the semiconductor substrate for electrical connection with the outside, a semiconductor device using the method, and a method of manufacturing the same are disclosed. .

(Bump formation method)
1A to 1D, 2A, and 2B are schematic cross-sectional views illustrating the bump forming method according to the present embodiment in the order of steps.

  First, a silicon semiconductor substrate 1 is prepared, and a desired LSI semiconductor element (not shown) is formed at an element formation site on the substrate surface 1a. Each step of the semiconductor substrate 1 on which the LSI semiconductor element or the like is formed in the element formation site will be described below.

  As shown in FIG. 1A, normally, the silicon semiconductor substrate is not uniform in thickness as shown in the figure, but is in a state accompanied by waviness. Therefore, the back surface 1b is flattened as a pre-process for cutting the surface 1a of the semiconductor substrate 1 using a cutting tool which will be described later.

  Specifically, a substrate support base (not shown) having a flat support surface is prepared, and the semiconductor substrate 1 is fixed to the substrate support base by adsorbing the surface 1a to the support surface by, for example, vacuum adsorption. At this time, the surface 1a is forcibly flattened by adsorption to the support surface, and thus the surface 1a becomes a reference surface for flattening the back surface 1b. In this state, the back surface 1b is machined, here, mechanically ground, and the convex portion 1c of the back surface 1b is removed by grinding and flattened. In this case, it is preferable to control the cutting amount of the back surface 1b by the distance from the front surface 1a. As a result, as shown in FIG. 1B, the thickness of the semiconductor substrate 1 is constant, specifically, TTV (specifically, the difference between the maximum thickness and the minimum thickness of the substrate) is a predetermined value or less. It is controlled to 1 μm or less.

  Subsequently, as shown in FIG. 1C, the semiconductor substrate 1 is removed from the substrate support, a photosensitive resin, for example, a photoresist is applied onto the surface 1a of the semiconductor substrate 1, and the photoresist is processed by photolithography. A resist mask 12 having a predetermined bump pattern 12a is formed.

  Subsequently, using the resist mask 12 as a mask, for example, a metal, for example, a copper film is formed by an evaporation method, and a plating electrode (not shown) is formed. Then, as shown in FIG. Gold (Au) is deposited so as to embed each bump pattern 12a of the resist mask 12, and Au protrusions 2 are formed. In addition, you may form a protrusion using Cu, Ag, Ni, Sn or these alloys other than Au.

Subsequently, the surface 1a of the semiconductor substrate 1 is subjected to a cutting process using a cutting tool and flattened.
Specifically, as shown in FIG. 2A, the back surface 1 b is adsorbed to the support surface 11 a of the substrate support table 11 by, for example, vacuum adsorption, and the semiconductor substrate 1 is fixed to the substrate support table 11. At this time, the thickness of the semiconductor substrate 1 is made constant by the flattening process of FIG. 1B on the back surface 1b, and the back surface 1b is not forcedly swelled by adsorption to the support surface 11a. Thus, the back surface 1b becomes a reference surface for flattening the front surface 1a. In this state, the surface layer of each Au protrusion 2 and the photoresist 12 on the surface 1a is machined, in this case using a cutting tool 10 made of diamond or the like, and the surface of each Au protrusion 2 and the resist mask 12 is continuously formed. A flattening process is performed so as to be flat. Thereby, the upper surface of the Au protrusion 2 is flattened into a mirror surface.

The results of planarization by this cutting process are shown in the micrographs and schematic diagrams of FIGS. 3A and 3B.
Before cutting, the surface of the Au protrusion was uneven as shown in FIG. 3A, whereas after cutting, the surface of the Au protrusion was flattened with high accuracy as shown in FIG. 3B. I know that.

  Subsequently, as shown in FIG. 2B, the resist mask 12 is removed by ashing or the like. At this time, on the surface 1 a of the semiconductor substrate 1, bumps 3 having a uniform height, each Au protrusion 2 being cut, and the upper surface 3 a being uniformly flattened are formed. Using this semiconductor substrate 1, for example, after making it into a chip, it is electrically connected to another semiconductor substrate 4 by bumps 3.

  In the present embodiment, a single semiconductor substrate has been described. However, it is preferable that the steps of the present embodiment be performed on a plurality of semiconductor substrates constituting a lot so that the thickness of each semiconductor substrate is made uniform. It is.

  Further, in the planarization process of FIG. 2A, as shown in FIGS. 4A and 4B, the semiconductor substrate 1 is parallelized with reference to the back surface 1b, and the position of the front surface 1a is detected and shaved from the detected front surface 1a. Calculate and control the amount.

  Specifically, as shown in FIG. 4A, when detecting the position of the surface 1a, a plurality of locations around the surface 1a of the semiconductor substrate 1, for example, three locations A, B, and C shown in FIG. It is preferable to irradiate the resist mask 12 with the laser beam 13 to heat and scatter these to expose a part of the surface 1a.

  Further, in this case, as shown in FIG. 5, when detecting the position of the front surface 1a, the semiconductor substrate 1 is adsorbed and fixed to the substrate support 11 on which the opening 11b is formed, and infrared laser light is applied from the opening 11b to the back surface 1b. The reflected light from the surface 1a may be measured by, for example, the infrared laser measuring device 14.

(Configuration of cutting device)
Here, the specific apparatus structure for performing the cutting process mentioned above is demonstrated.
FIG. 6 is a block diagram showing the configuration of the cutting apparatus, and FIG. 7 is a similar schematic configuration diagram. The cutting apparatus includes a storage unit 101 for storing a semiconductor substrate, a hand unit 102 for transporting the semiconductor substrate 1 to each processing unit, a sensing unit 103 for positioning the semiconductor substrate 1, and a chuck for the semiconductor substrate 1 at the time of cutting. A chuck table 104, a cutting unit 105 for performing flattening cutting of the semiconductor substrate 1, a cleaning unit 106 for performing cleaning after cutting, and a control unit 107 for controlling them. As described above, the chuck table portion 104 constitutes the substrate support (chuck table) 11 on which the semiconductor substrate 1 is placed and fixed, and the cutting portion 105 has a hard bit 10 that is a cutting tool made of diamond or the like. is doing.

Next, the flow of the cutting process will be described with reference to FIGS.
First, the transport hand of the hand unit 102 takes out the semiconductor substrate 1 from the storage cassette 111 of the storage unit 101 in which the semiconductor substrate 1 is stored. The storage unit 101 has an elevator mechanism that moves up and down to the height at which the semiconductor substrate 1 of the transport hand is taken out. Next, the transport hand vacuum-sucks the semiconductor substrate and transports it to the sensing unit 103. The transport hand is a Θ3-axis and Z-axis scalar robot, and can be easily handled by each processing unit. The robot mechanism is not limited to this, and may be an XY axis orthogonal type.

  In the sensing unit 103, the semiconductor substrate 1 is rotated 360 ° by the rotary table 112, the outer periphery of the semiconductor substrate 1 is imaged by the CCD camera 111, and the result is processed by the arithmetic unit of the control unit 107 and the center of the semiconductor substrate 1 is processed. Calculate the position.

  Next, based on the result, the transport hand corrects the position and transports the semiconductor substrate 1 to the chuck table unit 104, and the chuck table 11 is fixed by vacuum. This chuck table 11 serves as a processing reference surface. Therefore, in order to maintain the flatness accuracy during fixing and processing, the chuck surface preferably has a structure in which the semiconductor substrate 1 is chucked over the entire surface using a multi-hole material. The material is metal, ceramic, or resin. An optical sensor unit that is a light projecting unit 114 is arranged to face the chucked semiconductor substrate 1, and the dimensions of the semiconductor substrate 1 are measured and calculated together with the camera unit that is the light receiving unit 115, and the result is calculated as X of the cutting unit 105. Feedback to the shaft drive unit and command the amount of movement for cutting.

  When the cutting surface is a wiring forming surface, specifically, as shown in FIG. 4, it is preferable to irradiate a laser beam to heat and scatter the resist mask to expose the surface. And as shown in FIG. 5, a position is measured using the transmissive | pervious sensor using an infrared laser beam. Then, based on the result calculated there, the table on which the cutting tool 10 that actually performs cutting moves in the X direction and starts cutting. The cutting tool 10 used here is made of diamond or the like. In this way, the cutting to the set dimension is completed.

  Next, the transport hand takes out the semiconductor substrate 1 from the chuck table 11 and transports it to the cleaning unit. In the cleaning unit 105, the semiconductor substrate 1 is vacuum fixed and rotated, and the processed surface residual foreign matter is washed away with cleaning water. After that, it is rotated at a high speed while blowing air, and is dried while blowing off cleaning water. When the drying is completed, the transport hand takes out the semiconductor substrate 1 again and finally stores it in the storage cassette 111 of the storage unit 101.

  For each of the above steps, first, the back surface is cut on the basis of the bump and the surface on which the insulating film is formed between the bumps, and then the surface of each bump and the surface of the insulating film are cut on the back surface as a reference, Complete the planarization process.

(Semiconductor device and manufacturing method thereof)
Next, a method of manufacturing a semiconductor device using a semiconductor manufacturing apparatus that executes the above-described bump forming method will be described. Here, the configuration of the semiconductor device is described together with the manufacturing method thereof.
9A to 9C are schematic plan views showing the method for manufacturing the semiconductor device according to the present embodiment in the order of steps.

  First, through each step described in FIGS. 1 and 2, an LSI element or the like is mounted, and a semiconductor substrate 1 having bumps 3 whose upper surface 3a is flattened by cutting using a cutting tool is shown in FIG. 9A. Then, each semiconductor chip 21 is cut out.

  Subsequently, as shown in FIG. 9B, a semiconductor substrate 22 having bumps 3 whose upper surfaces are flattened by cutting using a cutting tool is prepared, and each semiconductor chip 21 is flattened on the semiconductor substrate 22. The formed upper surfaces 3a are electrically connected to each other. Specifically, the semiconductor substrate 22 and the semiconductor chip 21a are disposed so as to face each other on the upper surface 3a, and are bonded by pressure bonding at room temperature to 350 ° C., here about 170 ° C. Since each upper surface 3a is flattened with high accuracy, the semiconductor substrate 22 and the semiconductor chip 21 can be easily connected without requiring high temperature and high pressure as in the prior art.

  Then, as shown in FIG. 9C, each semiconductor chip 23 is cut out from the semiconductor substrate 22 to which the semiconductor chip 21 is connected, and the semiconductor chip is formed on the substrate 24 through a process such as a wire bonding method (connection using the wire 25). 23 is mounted to complete the semiconductor device.

  As described above, according to the present embodiment, instead of CMP, the surface of the fine bump 3 formed on the semiconductor substrate 1 is flattened at low speed and at high speed without causing inconvenience such as dishing. 3 can be connected easily and reliably. As a result, the bumps 3 can be connected to each other without requiring conditions such as high temperature and high pressure, and a highly reliable semiconductor device can be manufactured with high yield.

[Second Embodiment]
Next, a second embodiment will be described. In the first embodiment, Au is exemplified as the bump material. However, in this embodiment, a case where nickel (Ni) is used is illustrated.
10A to 10F are schematic cross-sectional views illustrating the bump forming method according to the present embodiment in the order of steps.

First, through the same steps as in FIGS. 1A and 1B of the first embodiment, the semiconductor substrate 1 is ground on the back surface, and the TTL is controlled to a predetermined value or less, specifically to 1 μm or less.
Using this semiconductor substrate 1, as shown in FIG. 10A, after patterning an electrode 31 made of an aluminum metal on the surface of the semiconductor substrate 1, a nickel phosphor plating film 32 is formed on the electrode 31 by an electroless plating method to a thickness of 5 μm. It is formed to about 10 μm.

  The nickel phosphorous plating film 32 is formed using nickel-phosphorus, nickel-phosphorus-boron, nickel-boron or the like by a general electroless plating method. For example, a nickel-phosphorus alloy is formed with a hypophosphite bath (sodium hypophosphite or potassium hypophosphite), and a nickel-boron alloy is a weakly acidic bath or medium using a sodium borohydride bath or dimethylaminoborane. The nickel-phosphorus-boron alloy is formed with a neutral bath.

  Here, in nickel-phosphorus electroless plating, a phosphorus-enriched layer 33 that is a mechanical fragile layer is formed on the surface layer of the nickel-phosphorous plating film 32 regardless of which alloy system is selected. After the formation of the solder bump, the phosphorus concentrated layer causes the interface strength between the plating and the solder bump to decrease. The thickness of this phosphorus concentration layer is about 20 nm to 40 nm, and becomes thicker as the phosphorus content in the plating bath increases.

  In addition, this phosphorus-enriched layer is generated regardless of the underlying material (glass substrate, iron substrate, aluminum substrate) and regardless of the plating thickness. Further, even if nickel-based electroless plating as described in Patent Document 6, for example, is annealed to a temperature higher than the solder melting point, a phosphorus-enriched layer is always generated on the surface layer. Unless the phosphorus-enriched layer is removed, it is difficult to form a highly reliable plating film and solder bump.

  Regarding these problems, there is a method in which a copper-nickel-tin compound layer is formed by adding copper to the solder material, and the formation of a phosphorus-enriched layer is suppressed by its barrier effect. However, when the Au plating thickness is 500 nm or more, there is a problem that the limitation of the Au plating thickness and the selectivity of the solder material are narrowed, such as the formation of a phosphorus concentrated layer.

Therefore, in this example, at the time of flattening the nickel phosphorus plating film 32 by cutting, the phosphorus concentrated layer 33 is removed at the same time.
Specifically, as shown in FIG. 10B, first, a liquid resist is coated as a protective film 34 so as to cover the substrate surface to form a physical impact mitigation layer by a cutting process described later. The protective film 34 is formed by applying and curing to a thickness of about 10 μm to 15 μm by spin coating or the like.

  Thereafter, as in FIG. 2A, the back surface is adsorbed on the support surface of the substrate support table by, for example, vacuum suction, and the semiconductor substrate 1 is fixed to the substrate support table. At this time, the thickness of the semiconductor substrate 1 is made constant by the flattening process of FIG. 1B on the back surface 1b, and the back surface 1b is not forcedly swelled by adsorption to the support surface 11a. Thus, the back surface 1b becomes a reference surface for flattening the front surface 1a. In this state, as shown in FIG. 10C, the surface layers of the nickel phosphorous plating film 32 and the protective film 34 on the surface 1a are machined, and in this case, cutting is performed using a cutting tool made of diamond or the like. The phosphorus concentration layer 33 is removed, and a flattening process is performed so that the surfaces of the nickel phosphorus plating film 32 and the protective film 34 are continuously flat. The cutting amount is set to about 1 μm to 2 μm so that the phosphorus concentrated layer 33 can be reliably removed.

  Subsequently, as shown in FIG. 10D, a gold plating film 35 is formed on the nickel phosphorous plating film 32 by an electroless plating method as necessary. The thickness of the gold plating film 35 is preferably about 30 nm to 50 nm.

  Subsequently, as shown in FIG. 10E, the protective film 34 is removed by ashing or the like. At this time, on the surface 1 a of the semiconductor substrate 1, bumps 36 are formed which are uniform in height, are uniformly flattened by cutting, and are formed with a gold plating film 35.

  Then, as necessary, solder bumps 37 are formed on the bumps 36 as shown in FIG. 10F. The solder bumps 37 are formed by screen printing, a solder ball method, melting, or the like. As a material for the solder, it is desirable to use a lead-free solder such as tin-silver or tin-zinc.

  Thereafter, the semiconductor substrate 1 is divided by full-cut dicing to cut out a semiconductor chip, and the semiconductor device is completed as in the first embodiment.

  As described above, according to the present embodiment, instead of CMP, the surface of the nickel bump 36 formed on the semiconductor substrate 1 is flattened at low speed and at high speed without causing inconvenience such as dishing. Therefore, it is possible to connect the bumps 36 without requiring conditions such as high temperature and high pressure, and a highly reliable semiconductor device can be manufactured with a high yield. In addition, since the phosphorus-enriched layer 34 that lowers the reliability at the joint portion between the bump 36 and the solder bump 37 can be completely removed at low cost, the solder bump 37 is reliably formed on the bump 36 whose upper surface is flattened. It becomes possible.

[Third Embodiment]
Next, a third embodiment will be described. In the first embodiment, the case where a large number of semiconductor chips are bonded to the semiconductor substrate is illustrated. However, in the present embodiment, the above-described planarization process is performed in the state of the semiconductor chip, and the semiconductor chips are bonded to each other. Disclose.
11A and 11B are schematic cross-sectional views showing the method of manufacturing the semiconductor device according to the present embodiment in the order of steps.

  First, as shown in FIG. 11A, a plurality of bumps, which are mounted with LSI elements and have different heights (there are still variations in height), here Au bumps, without the back surface grinding of the first embodiment. Individual semiconductor chips 41 are cut out from the semiconductor substrate on which 42 is formed.

  Subsequently, the surface layer of the semiconductor chip 41 is machined. Here, the surface of each Au bump 42 is flattened by cutting using a cutting tool made of diamond or the like as in the first embodiment. Process. Thereby, the height of each Au bump 42 is made uniform, and the upper surface is flattened into a mirror surface.

  Subsequently, as shown in FIG. 11B, the pair of semiconductor chips 41 are opposed to each other, and the two flattened upper surfaces of the Au bumps 42 are electrically connected to each other. Specifically, a pair of semiconductor chips 41 are arranged so as to face each other, and are bonded by pressure bonding at room temperature to 350 ° C., here about 170 ° C. Since each upper surface is flattened with high accuracy, a pair of semiconductor chips 41 can be easily connected without requiring high temperature and high pressure as in the prior art.

  As described above, according to the present embodiment, instead of CMP, the surface of the fine Au bump 42 formed on the semiconductor chip 41 is flattened at low speed and at high speed without causing inconvenience such as dishing. It becomes possible to connect the Au bumps 42 in the semiconductor chip 41 easily and reliably. Thereby, the Au bumps 42 can be connected to each other without requiring conditions such as high temperature and high pressure, and a highly reliable semiconductor device can be manufactured with high yield. In addition, since the above-described cutting process is performed after cutting into individual semiconductor chips 41 from the semiconductor substrate, the step of controlling the TTV can be omitted, which contributes to a reduction in the number of steps.

[Modification 1]
Here, the modification 1 of this embodiment is demonstrated.
12A to 12C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to Modification 1 in the order of steps.

  First, as shown in FIG. 12A, a plurality of bumps, which are mounted with LSI elements and having different heights (there are still variations in height), here Au bumps, without grinding the back surface of the first embodiment. Individual semiconductor chips 41 are cut out from the semiconductor substrate on which 42 is formed.

  Subsequently, a resin layer 43 made of an insulating material is formed so as to embed Au bumps 42 on the surface of the semiconductor chip 41. In addition, after forming the resin layer 43 so as to embed the Au bumps 42 in the state of the semiconductor substrate, the individual semiconductor chips 41 may be cut out.

  Subsequently, as shown in FIG. 12B, the surface layer of the semiconductor chip 41 is machined, here, similarly to the first embodiment, cutting is performed using a cutting tool made of diamond or the like, and the surface of each Au bump 42 and the resin layer The surface of 43 is flattened so as to be continuously flat. Thereby, the height of each Au bump 42 is made uniform, and the upper surface is flattened into a mirror surface.

  Subsequently, the pair of semiconductor chips 41 are made to face each other, and the Au bumps 42 and the resin layer 43 are electrically connected to each other on the flattened upper surfaces. Specifically, a pair of semiconductor chips 41 are arranged so as to face each other, and are bonded by pressure bonding at room temperature to 350 ° C., here about 170 ° C. Since each upper surface is flattened with high accuracy, a pair of semiconductor chips 41 can be easily connected without requiring high temperature and high pressure as in the prior art. Further, the resin film 43 ensures the bonding of the pair of semiconductor chips 41 and contributes as an underfill for protecting the electrodes 42 and the like.

  As described above, according to the first modification, instead of CMP, the surface of the fine Au bump 42 formed on the semiconductor chip 41 is flattened at low speed and at high speed without causing inconvenience such as dishing. It becomes possible to connect the Au bumps 42 in the semiconductor chip 41 easily and reliably. Thereby, the Au bumps 42 can be connected to each other without requiring conditions such as high temperature and high pressure, and a highly reliable semiconductor device can be manufactured with high yield. In addition, since the above-described cutting process is performed after cutting into individual semiconductor chips 41 from the semiconductor substrate, the step of controlling the TTV can be omitted, which contributes to a reduction in the number of steps.

[Modification 2]
Next, a second modification of the present embodiment will be described.
13A to 13C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to Modification 2 in the order of steps.

  First, as shown in FIG. 13A, a plurality of bumps having different heights (having variations in height) (here, Au bumps) mounted with LSI elements or the like without the back surface grinding of the first embodiment. Individual semiconductor chips 41 are cut out from the semiconductor substrate on which 42 is formed.

Subsequently, the surface layer of the semiconductor chip 41 is machined, here, as in the first embodiment, cutting is performed using a cutting tool made of diamond or the like so that the surface of each Au bump 42 is continuously flat. Perform flattening. Thereby, the height of each Au bump 42 is made uniform, and the upper surface is flattened into a mirror surface.

Subsequently, as shown in FIG. 13B, the planarized semiconductor chips 41 are paired into a pair of semiconductor chips 41, and the insulating bumps are formed so that the Au bumps 42 are completely embedded in the surface of one of the semiconductor chips 41. The resin layer 44 containing the conductive fine particles 45 is formed on the conductive resin.

  Subsequently, the pair of semiconductor chips 41 are opposed to each other, and the planarized upper surfaces of the Au bumps 42 are electrically connected to each other. Specifically, the pair of semiconductor chips 41 are disposed so as to face each other on the upper surface, and are bonded at room temperature to 350 ° C., here about 170 ° C. Here, the opposing Au bumps 42 are brought into contact with each other through the conductive fine particles 45 by thermocompression bonding, and are electrically connected. Since each upper surface is flattened with high accuracy, a pair of semiconductor chips 41 can be easily connected without requiring high temperature and high pressure as in the prior art. Further, the resin of the resin layer 44 ensures adhesion and electrical connection between the pair of semiconductor chips 41 and contributes as an underfill for protecting the electrodes 42 and the like.

  Thus, according to the second modification, instead of CMP, the surface of the fine Au bump 42 formed on the semiconductor chip 41 is flattened at low speed and at high speed without causing inconvenience such as dishing. It becomes possible to connect the Au bumps 42 in the semiconductor chip 41 easily and reliably. Thereby, the Au bumps 42 can be connected to each other without requiring conditions such as high temperature and high pressure, and a highly reliable semiconductor device can be manufactured with high yield. In addition, since the above-described cutting process is performed after cutting into individual semiconductor chips 41 from the semiconductor substrate, the step of controlling the TTV can be omitted, which contributes to a reduction in the number of steps.

[Fourth Embodiment]
Next, a fourth embodiment will be described. In the first embodiment, the case where bumps for external connection are formed on the semiconductor substrate is illustrated. However, in the present embodiment, the case where stud bumps using a wire bonding method are formed is disclosed.
14A to 14F are schematic cross-sectional views showing the method of manufacturing the semiconductor device according to the present embodiment in the order of steps.

  First, as shown in FIGS. 14A and 14B, as in FIG. 1A, the back surface of the semiconductor substrate 51 on which the LSI semiconductor elements and electrode pads are formed at the element formation site is ground, and the thickness of the semiconductor substrate 51 is kept constant. Specifically, the TTV (difference between the maximum thickness and the minimum thickness of the substrate) is controlled to 1 μm or less.

  Here, in the grinding step, after grinding the back surface of the semiconductor substrate 51, a metal film, for example, an Al film, is formed on the semiconductor substrate 51 by a sputtering method or the like, and this is patterned. The electrode pad 52 may be formed at a portion to be formed.

  Subsequently, as shown in FIG. 14C, after a ball-shaped lump formed by melting the tip of an Au bonding wire having a diameter of 20 μm, for example, is bonded onto the electrode pad 52 by a wire bonding method using Au as a metal, The wire is torn off (pre-cut), and Au protrusions 53 are formed on the electrode pads 52. At this time, the height of each Au protrusion 53 from the electrode pad 52 is defined to be at least twice the diameter of the bonding wire, here about 60 μm. In this case, the height of the Au protrusion 53 actually varies, and it may be about 50 μm to 60 μm.

  Subsequently, as shown in FIG. 14D, cutting is performed using a cutting tool 10 made of diamond or the like, and a flattening process is performed so that the upper surface of each Au protrusion 53 is continuously flat, thereby forming a stud bump 54. Here, the cutting position is set to a height of, for example, about 50 μm from the electrode pad 52. The cutting conditions are a cutting speed of 10 m / s, a feed per stroke of about 20 μm, and a 2 μm drive from the initial cutting position. As a result, as shown in FIG. 14E, the upper surface of the Au protrusion 53 is flattened into a mirror surface, and the stud bump 54 is formed.

  This flattening method by cutting does not require a slurry or the like as compared with CMP, and the cutting tool, which is a cutting tool, is worn and polished so that it can be used repeatedly, so that the cost is low. The semiconductor substrate chucked on the chuck table is rotated at a high speed, and then the cutting tool is moved at a predetermined speed to cut an arbitrary cutting amount at a time. Therefore, it can be completed in 1 to 2 minutes per semiconductor substrate. There is a very high throughput method. When cutting with a bite, by making the cutting conditions appropriate, even when stud bump projections using Au bonding wire are cut at the tip of the projection, flattening without tilting or bending of the projection can be achieved. Is possible. However, if the hardness is 30 Hv or less, the protrusions may be inclined during cutting. Therefore, the hardness of the wire is preferably 30 Hv or more.

  In the present embodiment, the end point of the cutting process is the time when the diameter of the cutting surface is equal to or greater than the wire diameter for all stud bumps. Normally, stud bumps vary greatly in height after pre-cutting, and it is difficult to confirm that the diameter of the cutting surface is equal to or greater than the wire diameter in all stud bumps. As a cutting method, it is appropriate to drive the cutting tool by 1 to 3 μm from the point where the cutting tool comes into contact with the highest bump and bring out the cutting surfaces of all the cutting tools. Is inefficient.

  Therefore, in the present embodiment, as shown in FIG. 15A, as a method for detecting the end point, a detection apparatus including a laser transmitter 61 and a detector 62 is used to operate a laser beam on the upper surface of the stud bump 54 after cutting. A method of detecting the laser reflected by the upper surface with the detector 62 is adopted.

  Then, as shown in FIG. 15B, the processing is repeated until the detected laser intensity reaches a predetermined intensity at all the Au protrusions 53. It is desirable that this detection device is installed behind the cutting tool in the traveling direction and proceeds in synchronization with the cutting tool. Since the upper surface (cutting surface) of the stud bump 54 is substantially a mirror surface, the laser beam or the like is totally reflected. When synchronized with the cutting tool, a delay is generated in proportion to the traveling speed of the cutting tool. Therefore, strictly speaking, not all reflected light is detected, but the cutting speed is 10 tens m / s at the fastest. Therefore, it can be considered that it is almost detected.

  In the present embodiment, the laser transmitter 61 and the detector 62 moving in synchronization with the progress of the cutting tool from the rear part of the cutting tool are driven while measuring the intensity of the laser beam reflected from the upper surface of the flattened Au protrusion 53. For example, it was detected that the upper surfaces of all the Au protrusions 53 were exposed at a height of 46 μm, and the cutting was finished.

  Here, as shown in FIG. 15C, when the cutting process is insufficient, or when the diameter of the cutting surface is equal to or less than the wire diameter, the laser light hitting a place other than the cutting surface is irregularly reflected, and the detector Not detected. Therefore, as shown in FIG. 15D, the detected laser light intensity is weaker than the surface cut to the same diameter as the bonding wire. When such a stud bump is confirmed even at one place, it is automatically driven further by about 1 μm to 2 μm and finally cut until a laser light intensity of a certain amount or more is detected in all the bumps. Thereby, connection failure due to uncut or insufficient cutting can be prevented, and the processing time can be greatly shortened.

  Then, as shown in FIG. 14F, each semiconductor chip 55 is cut out from the semiconductor substrate 51, and the semiconductor chip 55 and the circuit board 56 are connected by, for example, a flip chip method. Specifically, the stud bump 54 whose surface is flattened on the semiconductor chip 55 and the electrode 57 formed on the surface of the circuit board 56 are brought into contact with each other, and both are bonded by pressure and heating. In this case, like the stud bump 54, the electrode 57 of the circuit board 56 is also preferably made to be flip-chip connected after being flattened by the above-described cutting process.

  As described above, according to the present embodiment, instead of CMP, the surface of the fine stud bump 54 formed on the semiconductor substrate 51 is flattened at low speed and without causing inconvenience such as dishing, The stud bump 54 can be easily and reliably connected. As a result, the bumps can be connected without requiring conditions such as high temperature and high pressure, and a highly reliable semiconductor device can be manufactured with high yield. Moreover, the height of the stud bump 54 after the flattening of the cutting can be made 1.5 times or more compared with the case where the wire diameter is not specified, and the stress on the semiconductor element can be relaxed, and the device life Can be extended. Furthermore, since the flat surface in cutting is equal to or greater than the wire diameter, it is possible to obtain a bonding strength that is twice or more even with the same wire diameter. In addition, when a bonding strength comparable to the conventional one is sufficient, the wire diameter can be reduced, so that the bump pitch can be reduced and the cost for the bonding wire can be reduced.

[Fifth Embodiment]
Next, a fifth embodiment will be described. Here, a semiconductor device by a so-called TAB bonding method is illustrated.
16 and 17 are schematic cross-sectional views illustrating the method for fabricating the semiconductor device according to the present embodiment.

  In order to manufacture this semiconductor device, first, similarly to the first embodiment, the steps shown in FIGS. 1 and 2 are performed, and then on the electrode 71 of the semiconductor substrate 1 on which an LSI semiconductor element or the like is formed at the element formation site. In addition, the bump 3 is formed through the base metal film 72, the height of which is uniform, and each Au protrusion 2 is cut and the upper surface 3a is uniformly flattened. Here, an insulating protective film 73 is formed around the bump 3 of the semiconductor substrate 1.

  Subsequently, an electrical characteristic of the semiconductor element or the like of the semiconductor substrate 1 is inspected by bringing a probe into contact with the upper surface of the bump 3. Here, conventionally, since the probe is in contact with the bump end surface and the plating end surface where the contamination exists during the inspection, a stable contact cannot be obtained, and the tip of the probe is caught and damaged at the uneven portion. There was also a trouble. On the other hand, in this embodiment, since the probe is brought into contact with the surface of the bump 3 that has been highly planarized and cleaned by the above-described cutting process, the inspection can be performed in an extremely stable state.

Subsequently, after the individual semiconductor chips 21 are cut out from the semiconductor substrate 1, the semiconductor chips 21 are connected by the TAB bonding method as shown in FIG.
Specifically, the Au film 76 is formed of the copper foil 75 and is subjected to the surface treatment of Au, the portion located at one end corresponds to the connection site, and the resin layer 77 is provided at the other end. A TAB lead 74 is prepared. Then, the semiconductor chip 21 is placed and fixed on the bonding stage 80, and the Au film 76 at the connection portion of the TAB lead 74 is brought into contact with the flattened and cleaned upper surface of the bump 3 by the heater 78. Pressurize while heating to join them together. Here, the heating temperature may be a relatively low temperature of about 200 ° C., and the adhesion load can be reduced to about 2/3 of the conventional one, about 20 g. As a result, it is possible to connect TAB leads having a fine pitch of 40 μm or less without displacement.

  Thereafter, as shown in FIG. 17, the semiconductor chip 21 is removed from the bonding stage 80, and a sealing resin 79 is formed so as to cover the surface of the semiconductor chip 21 including the connection portion between the bump 3 and the TAB lead 74. Complete the device.

  In the present embodiment, the case where the plating bump is formed as the bump is exemplified, but the stud bump may be formed by a wire bonding method.

  As described above, according to the present embodiment, instead of CMP, the surface of the fine bump 3 formed on the semiconductor substrate 1 is flattened at low speed and at high speed without causing inconvenience such as dishing. 3 can be connected easily and reliably. As a result, it is possible to reliably connect the bump and the lead terminal without requiring conditions such as high temperature and high pressure, and it is possible to manufacture a highly reliable TAB bonding type semiconductor device with a high yield.

[Sixth Embodiment]
Next, a sixth embodiment will be described. Here, when executing the above-described embodiments, an apparatus for executing the above-described cutting process and joining process for a pair of bases (here, a semiconductor chip and a circuit board by a flip chip method are illustrated). The configuration is disclosed.

FIG. 18 is a schematic diagram showing the semiconductor manufacturing apparatus according to the present embodiment.
This semiconductor manufacturing apparatus includes a chip introducing portion 81 for introducing a semiconductor chip having bumps formed on the surface, a circuit substrate introducing portion 82 for introducing a circuit substrate having electrodes formed on the surface, and the above-described bite. A cutting portion 83 for performing a step of flattening the bump surface of the semiconductor chip by cutting using a chip, and a bonding portion 84 for performing a step of bonding the semiconductor chip and the circuit board with the flattened bump and electrode. And a carry-out portion 85 for carrying out the joined and integrated semiconductor device, and further includes a cleaning holding portion 86 including the cutting portion 83 and the joint portion 84 in an inert atmosphere. Has been. Here, in the cutting part 83, not only the semiconductor chip but also the electrode surface of the circuit board may be flattened by cutting.

The cleaning holding unit 86 performs both the flattening process and the bonding process in a cleaning atmosphere, specifically, in an inert atmosphere, for example, in a gas phase not containing oxygen such as Ar or N _2, or in the oxygen atmosphere containing 1 atm or less. It has the function of holding in the atmosphere. This makes it possible to maintain a flat state that is very close to the ideal relatively easily without adding a cleaning process using Ar plasma or the like immediately before the bonding process, and enables reliable bonding of bumps and electrodes. It becomes.

  In the present embodiment, the flip chip mounting is exemplified. However, the present invention is not limited to this, and the present invention is also suitable for joining a semiconductor chip and a semiconductor wafer, semiconductor chips, or the like.

  According to the present invention, instead of CMP, the surface of fine bumps formed on a substrate is flattened inexpensively and at high speed, and the bumps are connected easily and reliably without causing problems such as dishing. Is possible.

FIG. 1A is a schematic cross-sectional view showing a bump forming method according to the first embodiment in the order of steps. FIG. 1B is a schematic cross-sectional view showing the bump forming method according to the first embodiment in the order of steps. FIG. 1C is a schematic cross-sectional view showing a bump forming method according to the first embodiment in the order of steps. FIG. 1D is a schematic cross-sectional view showing the bump forming method according to the first embodiment in the order of steps. FIG. 2A is a schematic cross-sectional view showing a bump forming method according to the first embodiment in the order of steps. FIG. 2B is a schematic cross-sectional view illustrating the bump forming method according to the first embodiment in the order of steps. FIG. 3A is a diagram illustrating a result of flattening by cutting. FIG. 3B is a diagram illustrating a result of flattening by cutting. FIG. 4A is a schematic cross-sectional view showing a specific example of flattening by cutting. FIG. 4B is a schematic cross-sectional view showing a specific example of flattening by cutting. FIG. 5 is a schematic cross-sectional view showing a specific example of flattening by cutting. FIG. 6 is a block diagram showing the configuration of the cutting apparatus. FIG. 7 is a schematic configuration diagram of the cutting apparatus. FIG. 8 is a flowchart of the cutting process. FIG. 9A is a schematic plan view illustrating the manufacturing method of the semiconductor device according to the second embodiment in the order of steps. FIG. 9B is a schematic plan view showing the method of manufacturing the semiconductor device according to the second embodiment in the order of steps. FIG. 9C is a schematic plan view showing the method of manufacturing the semiconductor device according to the second embodiment in the order of steps. FIG. 10A is a schematic cross-sectional view showing a bump forming method according to the second embodiment in the order of steps. FIG. 10B is a schematic cross-sectional view showing the bump forming method according to the second embodiment in the order of steps. FIG. 10C is a schematic cross-sectional view showing the bump forming method according to the second embodiment in the order of steps. FIG. 10D is a schematic cross-sectional view illustrating the bump forming method according to the second embodiment in the order of steps. FIG. 10E is a schematic cross-sectional view showing the bump forming method according to the second embodiment in the order of steps. FIG. 10F is a schematic cross-sectional view showing the bump forming method according to the second embodiment in the order of steps. FIG. 11A is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the third embodiment in the order of steps. FIG. 11B is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the third embodiment in the order of steps. FIG. 12A is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the first modification of the third embodiment in the order of steps. FIG. 12B is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the first modification of the third embodiment in the order of steps. FIG. 12C is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the first modification of the third embodiment in the order of steps. FIG. 13A is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the second modification of the third embodiment in the order of steps. FIG. 13B is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the second modification of the third embodiment in the order of steps. FIG. 13C is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the second modification of the third embodiment in the order of steps. FIG. 14A is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment in the order of steps. FIG. 14B is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment in the order of steps. FIG. 14C is a schematic cross-sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment in the order of steps. FIG. 14D is a schematic sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment in the order of steps. FIG. 14E is a schematic sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment in the order of steps. FIG. 14F is a schematic sectional view showing the method of manufacturing the semiconductor device according to the fourth embodiment in the order of steps. FIG. 15A is a diagram illustrating a cutting end point detection method according to a fourth embodiment. FIG. 15B is a diagram illustrating a cutting end point detection method according to the fourth embodiment. FIG. 15C is a diagram illustrating a cutting end point detection method according to the fourth embodiment. FIG. 15D is a diagram illustrating a cutting end point detection method according to the fourth embodiment. FIG. 16 is a schematic cross-sectional view showing the method for manufacturing the semiconductor device of the fifth embodiment. FIG. 17 is a schematic cross-sectional view showing the method for manufacturing the semiconductor device of the fifth embodiment. FIG. 18 is a schematic view showing a semiconductor manufacturing apparatus according to the sixth embodiment.

Claims (48)

A method of forming bumps for electrical connection to the outside on the surface of a substrate,
Forming a plurality of bumps and an insulating film between the bumps on the surface of the substrate;
A step of performing a flattening process so that the surface of each bump and the surface of the insulating film are continuously flat by cutting using a cutting tool,
And a step of removing the insulating film. In forming the bump,
The bump forming method according to claim 1, wherein after processing the insulating film to form a mask having a plurality of electrode-shaped openings, the openings of the mask are filled with a conductive material. The bump forming method according to claim 2, wherein the openings of the mask are filled with the conductive material by a plating method. The bump is formed by a nickel-based electroless plating method,
2. The bump forming method according to claim 1, wherein when the surface of the bump is cut, a high phosphorus concentration layer formed on a surface layer of the bump is removed. 3. The bump formation method according to claim 4, wherein the insulating film is formed so as to cover the bump after the bump is formed by a nickel-based electroless plating method. 2. The bump forming method according to claim 1, wherein the substrate is provided with an LSI element, and the bump is connected to the LSI element. The bump forming method according to claim 1, wherein the surface of the bump is cut so as to have the same height on the substrate. Further comprising a step of flattening the back surface of the substrate by machining on the basis of the surface of the substrate;
The bump forming method according to claim 7, wherein the planarization process is performed on the surface of the bump and the surface of the insulating film with the back surface of the substrate as a reference. The bump forming method according to claim 8, wherein the steps are performed on a plurality of the substrates, and the thicknesses of the substrates are made uniform. When flattening the surface of the bump and the surface of the insulating film,
9. The bump according to claim 8, wherein the semiconductor substrate is parallelized with respect to the back surface, the position of the surface is detected, and the amount of shaving is calculated and controlled from the detected surface. Forming method. When detecting the position of the surface of the substrate, the insulating film in a plurality of locations around the surface is irradiated with laser light to heat and dissipate the insulator, thereby exposing a part of the surface. The method for forming a bump according to claim 10. The wiring forming method according to claim 10, wherein when detecting the position of the front surface of the substrate, the back surface is irradiated with infrared laser light and reflected light from the front surface is measured. Each has a pair of semiconductor substrates formed on the surface with a plurality of bumps for electrical connection with the outside,
The surface of each bump is continuously and uniformly planarized on each semiconductor substrate,
Each semiconductor substrate is formed by connecting and planarizing the planarized surfaces of each bump so as to be integrated. 14. The semiconductor device according to claim 13, wherein each semiconductor substrate is provided with an LSI element, and each bump is connected to each LSI element on each semiconductor substrate. The semiconductor device according to claim 13, wherein the bumps have the same height on the semiconductor substrates. 16. The semiconductor device according to claim 15, wherein each of the semiconductor substrates is machined on the back side thereof with reference to the front surface so that the back surface is flattened and the thickness of the substrate is uniformed. . Forming each bump on each surface of a pair of semiconductor substrates so as to be embedded in an insulating film;
A step of performing a flattening process so that the surface of each bump and the surface of the insulating film are continuously flat by cutting using a cutting tool,
Removing the insulating film;
Connecting each semiconductor substrate with the flattened surfaces of the respective bumps facing each other, and integrating them. A method for manufacturing a semiconductor device, comprising: 18. The method of manufacturing a semiconductor device according to claim 17, wherein each semiconductor substrate is provided with an LSI element, and each bump is connected to each LSI element on each semiconductor substrate. . Further comprising a step of flattening the back surface of the substrate by machining on the basis of the surface of the substrate;
18. The method of manufacturing a semiconductor device according to claim 17, wherein the planarization process is performed on the surface of the bump and the surface of the insulating film with reference to the back surface of each semiconductor substrate. A method of forming bumps for electrical connection to the outside on the surface of a substrate,
Forming a plurality of the bumps on the surface of the substrate;
And a step of performing a flattening process so that the surfaces of the plurality of bumps are continuously flattened by cutting using a cutting tool. Forming a plurality of bumps on each surface of a pair of semiconductor chips;
A step of performing a flattening process so that the surfaces of the plurality of bumps are continuously flat by cutting using a cutting tool,
And a step of connecting and integrating the pair of semiconductor chips in which the surfaces of the plurality of bumps are flattened so that the bumps face each other. The method further includes a step of flattening each back surface by machining on the basis of each surface of the pair of semiconductor chips,
The method of manufacturing a semiconductor device according to claim 21, wherein the flattening process of the surface of the bump is performed by the cutting process with the back surface as a reference. After forming the bump, a resin film is formed so as to cover the bump, and the surface of each bump and the surface of the resin film are flattened by the cutting process so as to be continuously flat. The method for manufacturing a semiconductor device according to claim 21, wherein: Each has a pair of semiconductor chips formed on the surface with a plurality of bumps for electrical connection with the outside,
The surface of each bump is continuously flattened on each semiconductor chip,
Each of the semiconductor chips is formed by connecting and planarizing the flattened surfaces of the bumps so as to be integrated. 25. The semiconductor device according to claim 24, wherein each of the semiconductor chips is machined on the back side thereof with respect to the front surface to flatten the back surface and make the substrate thickness uniform. . 25. The semiconductor device according to claim 24, wherein a resin film is formed so as to cover the bumps, and a surface of each bump and a surface of the resin film are continuously and uniformly flattened. A bump for electrical connection to the surface of a semiconductor substrate, a method of forming a stud bump using a wire bonding method,
Forming a plurality of protrusions using bonding wires at electrical connection locations on the surface of the semiconductor substrate;
Forming a stud bump by performing a flattening process so that upper surfaces of the plurality of protrusions are continuously flattened by cutting using a cutting tool, and forming a stud bump. By using a detection device including a laser transmitter and a detector, operating a laser beam on the upper surface of the projection after the cutting, and detecting the laser beam reflected on the upper surface by the detector 28. The bump forming method according to claim 27, wherein the cutting process is repeatedly executed until the intensity of the detected laser beam reaches a predetermined value for all the protrusions. 29. The bump forming method according to claim 28, wherein the detector is installed behind the moving direction of the cutting tool, and the detector is moved so as to synchronize with the operation of the cutting tool. Forming a protective film so as to cover the plurality of protrusions;
And a step of removing the protective film after performing a flattening process so that the upper surfaces of the plurality of protrusions and the surface of the protective film are continuously flattened by the cutting. Item 28. The bump forming method according to Item 27. It is a bump for electrical connection with the outside, and has a semiconductor chip in which a plurality of stud bumps using a wire bonding method are formed on the surface,
A semiconductor device, wherein the upper surface of each stud bump is continuously flattened on the semiconductor chip. Forming a plurality of bumps on the surface of the semiconductor substrate;
A step of performing a flattening process so that the surfaces of the plurality of bumps are continuously flat by cutting using a cutting tool,
A step of cutting each semiconductor chip from the semiconductor substrate in which the surfaces of the plurality of bumps are planarized;
Connecting the bump of the semiconductor chip and one end of a lead terminal. A method for manufacturing a semiconductor device, comprising: The method further includes a step of planarizing the back surface by machining on the basis of the surface of the semiconductor substrate,
33. The method of manufacturing a semiconductor device according to claim 32, wherein the flattening process of the surface of the bump is performed by the cutting process with the back surface as a reference. Forming a plurality of protrusions using a wire bonding method at an electrical connection location on a surface of a semiconductor substrate;
By cutting using a cutting tool, a process of flattening so that the upper surfaces of the plurality of protrusions are continuously flat, and forming stud bumps;
A step of cutting each semiconductor chip from the semiconductor substrate on which a plurality of stud bumps are formed;
Connecting the stud bump of the semiconductor chip and one end of the lead terminal. A method for manufacturing a semiconductor device, comprising: The method further includes a step of planarizing the back surface by machining on the basis of the surface of the semiconductor substrate,
35. The method of manufacturing a semiconductor device according to claim 34, wherein the flattening process of the surface of the bump is performed by the cutting process with the back surface as a reference. 35. The semiconductor device according to claim 34, further comprising a step of inspecting a surface of the bump by bringing a test needle into contact with the surface of the bump before the connection with the lead terminal after the surface of the bump is flattened. Device manufacturing method. It has a semiconductor chip in which a plurality of bumps for electrical connection with the outside are formed on the surface,
The surface of each bump is continuously flattened on the semiconductor chip,
A semiconductor device, wherein the bump of the semiconductor chip and one end of a lead terminal are connected and integrated. 38. The semiconductor device according to claim 37, wherein the bump is made of gold and a surface treatment of gold or tin is applied to the one end portion of the lead terminal. It is a plurality of bumps for electrical connection with the outside, and has a semiconductor chip in which a plurality of stud bumps using a wire bonding method are formed on the surface,
The surface of each stud bump is continuously flattened on the semiconductor chip,
The semiconductor device, wherein the stud bump of the semiconductor chip and one end of the lead terminal are connected and integrated. 40. The semiconductor device according to claim 39, wherein the stud bump is made of gold, and the one end portion of the lead terminal is subjected to a surface treatment of gold or tin. Introducing a semiconductor chip having a plurality of electrodes formed on the surface thereof into an inert atmosphere and performing a flattening process so that the surfaces of the plurality of electrodes are continuously flat by cutting using a cutting tool;
Connecting and integrating the plurality of electrodes of the semiconductor chip and the circuit board in a state where the surfaces of the plurality of planarized electrodes are kept clean in the inert atmosphere. A method of manufacturing a semiconductor device. The plurality of electrodes formed on the circuit board are flattened so that the surface is continuously flat by cutting using a cutting tool,
42. The method of manufacturing a semiconductor device according to claim 41, wherein the semiconductor chip and the circuit board are connected and integrated so that the electrode surfaces face each other. Cutting means having a cutting tool;
A joining means for joining a pair of introduced substrates;
An inert atmosphere means for maintaining the environment of the cutting means and the joining means in an inert atmosphere state,
In the inert atmosphere, the cutting means continuously cuts the surfaces of the plurality of electrodes by cutting using the cutting tool on at least one of the pair of bases having a plurality of electrodes formed on the surface. And has a function of flattening so as to be flat,
The joining means has a function of connecting and integrating the pair of substrates with the plurality of electrodes in a state where the surfaces of the planarized electrodes are kept clean in the inert atmosphere. A semiconductor manufacturing apparatus. A substrate processing apparatus for forming bumps for electrical connection with the outside on the surface of a substrate,
A substrate support base that has a flat support surface, adsorbs the substrate to the support surface on one surface, and forcibly supports and fixes the one surface as a flat reference surface;
A cutting tool for cutting the other surface of the substrate,
A plurality of bumps on the surface and a substrate in which an insulating film is formed between the bumps are supported and fixed to the substrate support base, and the surface of each bump and the surface of the insulating film are formed by cutting using the cutting tool. A substrate processing apparatus which performs a planarization process so as to be continuously flat. After cutting the back surface of the substrate with the cutting tool using the substrate support table as the reference surface, the front surface of the substrate with the cutting tool using the substrate support table as the reference surface with the back surface of the substrate. 45. The substrate processing apparatus according to claim 44, wherein the surface of each bump and the surface of the insulating film are flattened so as to be continuously flat. 45. The method according to claim 44, wherein the semiconductor substrate is parallelized with respect to the back surface, the position of the wiring forming surface is detected, and a shaving amount is calculated from the detected wiring forming surface. The substrate processing apparatus as described. When detecting the position of the wiring formation surface, the insulating film in a plurality of locations around the wiring formation surface is irradiated with laser light to heat and dissipate the insulator to expose a part of the wiring formation surface. 47. The substrate processing apparatus according to claim 46, wherein: 47. The substrate processing apparatus according to claim 46, wherein when detecting the position of the wiring formation surface, the back surface is irradiated with infrared laser light and the reflected light from the wiring formation surface is measured.

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