JP2005166739A - Method of connecting metal bump and circuit component with metal bump - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of connecting metal bumps which enables high-density connection without causing defective connections and short-circuits, and to provide a circuit component with the metal bumps. <P>SOLUTION: On a substrate, solder thin-film patterns 104-1 to 104-8 are formed, and then these patterns are laminated by cold bonding on an electrode pad 204 of an integrated circuit chip 203 to form a solder bump 105 consisting of a laminated structure. Since the fine solder thin-film patterns 104-1 to 104-8 can be formed on the substrate by patterning, a minute solder bump having an excellent profile precision can be obtained by bonding and laminating them, resulting in enabling high-density connection without causing defective connections and short-circuits. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a metal bump connection method for connecting a metal bump such as a ball bump or a stud bump to a connection surface of a circuit component such as a circuit board or a circuit chip having a semiconductor integrated circuit, and a circuit component with a metal bump. The present invention relates to a metal bump connection method and a circuit component with metal bumps that enable higher density connection without causing a short circuit or a short circuit.

  In recent years, as the degree of integration of semiconductor integrated circuits has improved, the number of terminals taken out from integrated circuit chips has increased remarkably. For example, the number of connection pins of a semiconductor integrated circuit of several mm square has increased from the conventional several tens of pins to several hundreds or more than several thousand, and the number tends to further increase.

  In order to meet this requirement, a method of mounting metal bumps on the connection surface of a semiconductor integrated circuit has been put into practical use.

  As an example of such circuit mounting, an integrated circuit chip is connected and mounted on a ceramic wiring board by wire bonding or a flip chip using a solder ball, and the ceramic wiring board is composed of a large number of solder balls provided below the integrated circuit chip. It is mounted on a printed circuit board via a ball grid array (BGA). As a conventional method of connecting the solder balls, for example, a method of sucking the solder balls is known (for example, Patent Document 1).

  As another circuit mounting example, a gold stud bump protrusion is provided on an electrode pad of an integrated circuit chip, a gold electrode is used for an electrode to be connected, and solid-layer diffusion between metals is applied by pressing at a low temperature. To connect. As a conventional method for connecting the gold stud bump, a method using a gold wire is known (for example, Patent Document 2).

The solder ball connection method described in Patent Document 1 includes the following steps.
1) Formation of solder balls,
2) Adhesion formation of the ball on the substrate: Specifically, each ball is adsorbed without omission by a dedicated jig for adsorbing the ball, and aligned and pressed onto the substrate electrode coated with solder flux. Each ball is placed on the substrate electrode by dropping or jetting compressed air and heated and melted.
3) Melt mounting on a wiring board: Specifically, a board with solder balls is placed on an electrode pad of a larger wiring board, and the solder balls are heated and melted to be connected to the electrode pads.

The gold stud bump connection method described in Patent Document 2 includes the following steps.
1) Formation of gold stud bump: A gold stud bump is formed by wire bonding a gold wire to an electrode pad.
2) Mounting on the wiring board: The above chip is pressed against the wiring board, and solid-layer diffusion bonding is performed between the metal studs on the wiring board and the gold stud bumps are deformed.
JP 2001-156093 A JP-A-7-297227

However, according to the conventional solder ball connection method, the connection method using BGA requires a complicated process, and the resistance value increases due to a connection failure caused by a void or the like at the interface between the solder ball and the wiring electrode. Or, when the solder balls are melted, adjacent balls are fused to cause a short circuit. These problems increase with the increase in the number of connection pins, resulting in problems such as a decrease in yield in the mounting process.
Furthermore, since the ball size becomes smaller due to the increase in the number of connection terminals, problems such as the formation and mounting of balls for mounting become more difficult, and the size of the solder ball is substantially about 100 μm. It is the limit, and high-density mounting beyond that is impossible.

  According to the conventional gold stud bump connection method, since the gold stud bump is formed by wire bonding, the connection density is limited by the density of wire bonding, and the pitch is about 80 microns at most, which is a high density requirement. Can't be said to be enough. Moreover, since the bump shape also varies depending on wire cutting in wire bonding, a connection failure may be observed.

  Accordingly, an object of the present invention is to provide a metal bump connection method and a circuit component with metal bumps that enable a higher density connection without causing a connection failure or a short circuit.

  In order to achieve the above object, the present invention provides a metal bump connection method for connecting metal bumps to a connection surface of a circuit component, wherein a plurality of metal thin films corresponding to a cross-sectional shape of the metal bumps are formed on a substrate, The metal bump is formed by laminating the metal thin film on the connection surface by room temperature bonding.

  In order to achieve the above object, the present invention provides a circuit component with a metal bump in which a metal bump is connected to a connection surface of the circuit component. The metal bump is formed by laminating a plurality of metal thin films on the connection surface by room temperature bonding. Provided is a circuit component with metal bumps, which is characterized by being formed.

  According to the metal bump connection method and the circuit component with metal bumps of the present invention, a plurality of fine metal thin films can be formed on the substrate by patterning. In addition, a fine metal bump can be obtained, and a higher density connection can be achieved without causing a connection failure or a short circuit.

  In addition, by simultaneously connecting a plurality of metal bumps to a plurality of connection surfaces, the manufacturing process can be shortened and mass production becomes possible.

<First Embodiment>
FIG. 1 shows a solder ball as a metal bump according to a first embodiment of the present invention, FIG. 1 (a) shows a target solder ball 1, and FIG. The solder ball 1 shown in a) is divided into a plurality of layers 1-1 to 1-8. In the figure, reference numeral 204 denotes an electrode pad to be connected to the solder ball 1, and 204 a denotes a connection surface of the electrode pad 204. Further, here, in order to simplify the explanation, a case where one solder ball is formed will be described, but it goes without saying that a plurality of solder balls are actually formed simultaneously. In this embodiment, the diameter of the solder ball is about 10 μm and is divided into about 8 layers.

  Next, the solder ball connection method according to the first embodiment will be described with reference to the connection steps shown in FIGS.

(1) Formation of solder thin film pattern In this embodiment, a solder thin film is formed on a substrate, and the solder thin film is patterned by using a photolithography method to form a solder thin film pattern. First, as shown in FIG. 2A, polyimide is applied to the surface of the Si wafer substrate 100 to a thickness of 1 to 5 μm by spin coating, and subjected to curing treatment and fluorination treatment on the surface to release the layer 101. Form. Further, a resist pattern 102 having an opening 102a in a portion where a solder film is to be formed is formed on the release layer 101 using a photomask corresponding to the layers 1-1 to 1-8 of the pattern divided in FIG. It is formed with a thickness of about 1 μm.

  Subsequently, as shown in FIG. 2B, a solder thin film 103 is formed on the entire surface by a vapor deposition method or the like to a thickness of about 1 μm, and then the resist pattern 102 is removed to simultaneously remove the solder film thereon. As a result, as shown in FIG. 2C, the solder thin film patterns 104-1 to 104-4 corresponding to the layers 1-1 to 1-4 of the fine solder balls shown in FIG. can get.

  FIG. 3 shows a state in which the substrate 100 shown in FIG. The plurality of solder thin film patterns 104-1 to 104-8 are arranged vertically and horizontally at a constant pitch on the substrate 100.

(2) Lamination of Solder Thin Film Pattern Here, solder thin film patterns 104-1 to 104-8 are laminated by room temperature bonding to form solder balls. Here, “room temperature bonding” refers to bonding in a temperature environment including room temperature without heating or cooling. First, as shown in FIG. 4A, the substrate 100 on which the solder thin film patterns 104-1 to 104-8 are formed is introduced into the vacuum chamber 200. Here, for simplicity, only the first-layer solder thin film pattern 104-1 and the second-layer solder thin film pattern 104-2 are shown. On the other hand, in the vacuum chamber 200, the stage 201 that has attracted the integrated circuit chip 203 to be connected to the solder ball is disposed so as to face the substrate 100. In the figure, the electrode pads 204 and the passivation film 205 on the integrated circuit chip 203 are schematically shown.

Next, the inside of the vacuum chamber 200 is evacuated to about 10 ⁻⁵ Pa, and as shown in FIG. 4B, the surface of the first solder thin film pattern 104-1 and the electrode pads 204 of the integrated circuit chip 203 are removed. FAB (Fast Atom Beam) processing using Ar gas 206 as a source is performed on the front connection surface 204a. This is a process of accelerating Ar gas 206 at a voltage of about 1 kV and irradiating the surface of the solder thin film pattern 104-1 and the electrode pad 204 to remove oxides, impurities, etc. on these surfaces to form a normal surface. It is.

Next, as shown in FIG. 5A, the stage 201 is lowered to bring the clean connection surface 204a of the electrode pad 204 into contact with the clean surface of the solder thin film pattern 104-1, and 50 kgf / cm ² as a load. Is applied and pressed for 5 minutes to bond the solder thin film pattern 104-1 and the electrode pad 204 together.

  As shown in FIG. 5B, when the stage 201 is raised, the bonding force between the solder thin film pattern 104-1 and the electrode pad 204 is such that the solder thin film pattern 104-1 and the surface of the substrate 100 are separated. Since the adhesive strength with the layer 101 is greater, the solder thin film pattern 104-1 is transferred from the substrate 100 to the electrode pad 204.

  Subsequently, as shown in FIG. 6 (a), the stage 201 is moved in the horizontal direction, and the surfaces to be joined are similarly subjected to FAB treatment. In the example, FAB is irradiated to the surface of the second layer of solder thin film pattern 104-2 that is newly bonded to the lower surface of the first layer of solder thin film pattern 104-1 that has been in contact with the substrate 100 until then. Thereafter, the stage 201 is lowered, contacted, applied with a load, and lifted in the same manner as described above, so that the second solder thin film pattern 104-1 is followed by the second solder thin film pattern 104-1 as shown in FIG. The pattern 104-2 is transferred. By performing the above operation as many times as the number of layers of the solder thin film pattern, a solder ball made of a laminated structure can be obtained.

  FIG. 7 shows a solder ball 105 made of the laminated structure. Solder balls 105 made of solder thin film patterns 104-1 to 104-8 similar to the solder balls 1 shown in FIG. 1B are formed on the electrode pads 204 of the integrated circuit chip 203.

  According to the first embodiment, the solder ball 105 formed according to the present embodiment is formed by laminating metal thin films formed by photolithography etching of a deposited thin film by room temperature bonding. It is possible to form an extremely small size of 10 μm or less as a geometric dimension, and a geometrical shape such as a diameter of a large number of balls can be made uniform on the micron order, and adhesion to the electrode pad 204 can be improved. Excellent, very few defects such as voids, can be formed at the same time for many electrode pads, and can be formed at room temperature. It can be said that it is an epoch-making connection method having many excellent points, such as being capable of being formed into an organic device that dislikes processing. In addition, since the pitch of about 60 μm can be reduced to 10 μm or less, the mounting density can be improved to about 20 times or more.

<Second Embodiment>
FIG. 8 shows a gold stud bump as a metal bump according to the second embodiment of the present invention. FIG. 8 (a) shows a target gold stud bump 2, and FIG. 8 (b) shows the same figure. The gold stud bump 2 shown in (a) is divided into a plurality of layers 2-1, 2-2. In the figure, reference numeral 204 denotes an electrode pad to be connected to the gold stud bump 2, and 204 a denotes a connection surface of the electrode pad 204. Further, here, in order to simplify the description, a case where one gold stud bump is formed will be described, but it is needless to say that a plurality of gold stud bumps are actually formed simultaneously.

  Next, a method for connecting gold stud bumps according to the second embodiment will be described with reference to the connection steps shown in FIGS.

(1) Formation of gold plating film pattern In this embodiment, the gold plating film pattern is formed by electroforming. First, as shown in FIG. 9A, in addition to a metal material such as stainless steel or aluminum, polyimide is applied to the surface of a base substrate 300 made of an insulator such as Si, ceramic, or synthetic resin by spin coating to 1 to 5 μm. The release layer 301 is formed by coating with a thickness and performing a curing process and a surface fluorination process. Next, the conductive film 302 for imparting conductivity to the surface of the release layer 301 is preferably gold, but otherwise, silver, copper, nickel, or the like is formed by sputtering to a thickness of about 3000 mm.

  Next, using a photomask corresponding to the layers 2-1 and 2-2 of the pattern divided in FIG. 8B, a photoresist pattern 303 having an opening 303a in a portion where the gold plating film is to be formed is 5 to 25 μm. Form with thickness. The substrate 300 is placed in a gold electroplating solution layer, and a gold plating film 304 is formed in a portion not covered with the photoresist pattern 303 to a thickness equivalent to the photoresist pattern 303 as shown in FIG. 9B. After the gold plating, the photoresist 303 is removed, and the exposed portion of the conductive film 302 is removed by etching, whereby the substrate 300 on which the gold plating film patterns 304-1 and 304-2 are formed is obtained. In this case, when the material of the conductive film 302 is gold, the surface of the gold plating 304 is simultaneously etched, but the etching amount is 3000 mm corresponding to the thickness of the conductive film 302 and has almost no influence.

(2) Lamination of Gold Plating Film Pattern Next, as in the first embodiment, as shown in FIG. 10A, the substrate 300 on which the gold plating film patterns 304-1 and 304-2 are formed is placed in a vacuum chamber. 200. On the other hand, in the vacuum chamber 200, the stage 201 that has attracted the integrated circuit chip 203 to be connected to the gold stud bump is disposed so as to face the substrate 300. In this example, the gold plating film patterns 304-1 and 304-2 are transferred to the electrode pad 204.

  Thereafter, as in the first embodiment, after vacuum evacuation, the transfer by FAB, stage 201 lowering, load application, and stage 201 raising is repeated twice, as shown in FIG. A gold stud bump 305 is formed on the connection surface 204a. The gold stud bump 305 is formed by stacking the first gold plating film pattern 304-1 and the second gold plating film pattern 304-2.

  According to the second embodiment, the gold stud bump 305 formed according to the present embodiment is formed by laminating a plating thin film formed by electroforming by room temperature bonding. Minimal size of 10 μm or less can be formed as a geometric dimension, and the geometrical shapes such as the thickness and width of a large number of bumps can be made uniform on the order of microns, and the electrode pad 204 can be closely attached. Si crystal integrated circuit chip because of its excellent performance and extremely low occurrence of defects such as voids, and can be formed on a large number of electrode pads 204 at a time, and can be formed at room temperature. In addition to this, it can be said that it is an epoch-making mounting method having many excellent points, such as being capable of being formed into an organic device that dislikes high temperature processing. In addition, since the pitch of about 60 μm can be reduced to 10 μm or less, the mounting density can be improved to about 20 times or more.

<Third Embodiment>
FIG. 11 shows a circuit component with metal bumps according to the third embodiment of the present invention. In this circuit component with metal bumps, an integrated circuit chip 203 having a solder ball 105A made of a laminated structure connected to an electrode pad 204 is mounted on a high-density wiring board 400, and an electrode pad on the lower surface of the high-density wiring board 400 is mounted. A laminated structure 204 is connected to a solder ball 105B having a diameter larger than that of the solder ball 105A so that it can be mounted on a printed board (not shown). According to the third embodiment, since the solder ball 105 made of a laminated structure capable of high-density connection is used, it is possible to provide a circuit component with a high pin count.

<Fourth embodiment>
FIG. 12 shows a circuit component with metal bumps according to the fourth embodiment of the present invention. In this circuit component with metal bumps, an integrated circuit chip 203 having a stud bump 305 made of a laminated structure connected to an electrode pad 204 is mounted on a high-density wiring board 400, and the electrode pads on the lower surface of the high-density wiring board 400 are mounted. A solder ball 105B made of a laminated structure is connected to 204 so that it can be mounted on a printed circuit board (not shown). According to the fourth embodiment, similarly to the third embodiment, it is possible to provide a circuit component with an increased number of pins.

  In each of the above embodiments, solder and gold have been described as materials for the metal thin film. However, the present invention is not limited to these, and other single metals such as copper and aluminum, and alloys such as copper alloys and aluminum alloys may be used.

  In each of the above embodiments, the integrated circuit chip side is moved and the metal thin film is joined. However, if the relative movement is possible, the substrate side can be moved or both can be moved. Good.

1A is a cross-sectional view showing a target solder ball, and FIG. 2B is a diagram illustrating a solder ball divided into a plurality of layer films according to the first embodiment of the present invention. It is sectional drawing which shows a state. (A)-(c) is sectional drawing for demonstrating the connection method of the solder ball based on the 1st Embodiment of this invention. It is the figure which looked at the board | substrate shown in FIG.2 (c) from upper direction. (A), (b) is sectional drawing which shows the connection process of the solder ball based on the 1st Embodiment of this invention. (A), (b) is sectional drawing which shows the connection process of the solder ball based on the 1st Embodiment of this invention. (A), (b) is sectional drawing which shows the connection process of the solder ball based on the 1st Embodiment of this invention. 1 is a cross-sectional view of a solder ball according to a first embodiment of the present invention. The gold stud bump which concerns on the 2nd Embodiment of this invention is shown, (a) is sectional drawing which shows the gold stud bump used as a target, (b) is a gold stud bump shown to (a) in several layers It is sectional drawing which shows the state divided | segmented into. (A)-(c) is sectional drawing which shows the connection process of the gold stud bump which concerns on the 2nd Embodiment of this invention. (A), (b) is sectional drawing which shows the connection process of the gold stud bump which concerns on the 2nd Embodiment of this invention. It is sectional drawing of the circuit component with a metal bump which concerns on the 3rd Embodiment of this invention. It is sectional drawing of the circuit component with a metal bump which concerns on the 4th Embodiment of this invention.

Explanation of symbols

1 Solder ball 1-1 to 1-8 layer 2 Gold stud bump 2-1 and 2-2 layer 100 Si wafer substrate 101 Release layer 102 Resist pattern 102a Opening 103 Solder thin film 104-1 to 104-8 Solder thin film pattern 105 105A, 105B Solder ball 200 Vacuum chamber 201 Stage 203 Integrated circuit chip 204 Electrode pad 204a Connection surface 205 Passivation film 206 Ar gas 300 Base substrate 301 Release layer 302 Conductive film 303 Photoresist pattern 303a Opening 304 Gold plating film 304-1 304-2 Gold plated film pattern 305 Gold stud bump 400 High density wiring board

Claims (8)

In the metal bump connection method of connecting the metal bump to the connection surface of the circuit component,
A plurality of metal thin films corresponding to the cross-sectional shape of the metal bumps are formed on the substrate,
The metal bump connection method, wherein the metal bumps are formed by laminating the plurality of metal thin films on the connection surface by room temperature bonding.   2. The metal bump connection method according to claim 1, wherein the plurality of metal thin films are formed by forming a metal thin film on the substrate and patterning the metal thin film by a photolithography method.   The metal bump connection method according to claim 1, wherein the plurality of metal thin films are formed by electroforming. In a metal bump connection method for connecting a plurality of metal bumps to a plurality of connection surfaces of circuit components,
A plurality of metal thin films corresponding to the cross-sectional shape of the plurality of metal bumps are collectively formed on the substrate,
A metal bump connection method comprising: stacking the plurality of metal thin films on the connection surfaces by room temperature bonding to form the plurality of metal bumps simultaneously. In circuit components with metal bumps where metal bumps are connected to the connection surfaces of circuit components,
The metal bump is a circuit component with a metal bump, wherein the metal bump is formed by laminating a plurality of metal thin films on the connection surface by room temperature bonding. The metal thin film is a circular solder thin film,
6. The circuit component with metal bumps according to claim 5, wherein the metal bumps have a ball shape. The metal thin film is made of a gold plating film,
6. The circuit component with metal bumps according to claim 5, wherein the metal bumps have a stud bump shape. The circuit component has a plurality of connection surfaces,
6. The circuit component with metal bumps according to claim 5, wherein the metal bumps are a plurality of the metal bumps formed on the plurality of connection surfaces.

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