SE9803708L - Metod och anordning för kontroll/access av DRAM-minnen - Google Patents

Metod och anordning för kontroll/access av DRAM-minnen

Info

Publication number
SE9803708L
SE9803708L SE9803708A SE9803708A SE9803708L SE 9803708 L SE9803708 L SE 9803708L SE 9803708 A SE9803708 A SE 9803708A SE 9803708 A SE9803708 A SE 9803708A SE 9803708 L SE9803708 L SE 9803708L
Authority
SE
Sweden
Prior art keywords
dram
microcode
processor
memory
access
Prior art date
Application number
SE9803708A
Other languages
Unknown language ( )
English (en)
Other versions
SE9803708D0 (sv
SE512773C2 (sv
Inventor
Sven Stefan Blixt
Original Assignee
Imsys Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Imsys Ab filed Critical Imsys Ab
Priority to SE9803708A priority Critical patent/SE512773C2/sv
Publication of SE9803708D0 publication Critical patent/SE9803708D0/sv
Priority to EP99958554A priority patent/EP1125191A1/en
Priority to PCT/SE1999/001923 priority patent/WO2000025205A1/en
Priority to US09/830,094 priority patent/US6938118B1/en
Priority to AU15894/00A priority patent/AU1589400A/en
Publication of SE9803708L publication Critical patent/SE9803708L/sv
Publication of SE512773C2 publication Critical patent/SE512773C2/sv

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0215—Addressing or allocation; Relocation with look ahead addressing means

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Dram (AREA)
  • Executing Machine-Instructions (AREA)
  • Microcomputers (AREA)
SE9803708A 1998-10-28 1998-10-28 Metod och anordning för kontroll/access av DRAM-minnen SE512773C2 (sv)

Priority Applications (5)

Application Number Priority Date Filing Date Title
SE9803708A SE512773C2 (sv) 1998-10-28 1998-10-28 Metod och anordning för kontroll/access av DRAM-minnen
EP99958554A EP1125191A1 (en) 1998-10-28 1999-10-25 Controlling access to a primary memory
PCT/SE1999/001923 WO2000025205A1 (en) 1998-10-28 1999-10-25 Controlling access to a primary memory
US09/830,094 US6938118B1 (en) 1998-10-28 1999-10-25 Controlling access to a primary memory
AU15894/00A AU1589400A (en) 1998-10-28 1999-10-25 Controlling access to a primary memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9803708A SE512773C2 (sv) 1998-10-28 1998-10-28 Metod och anordning för kontroll/access av DRAM-minnen

Publications (3)

Publication Number Publication Date
SE9803708D0 SE9803708D0 (sv) 1998-10-28
SE9803708L true SE9803708L (sv) 2000-04-29
SE512773C2 SE512773C2 (sv) 2000-05-08

Family

ID=20413122

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9803708A SE512773C2 (sv) 1998-10-28 1998-10-28 Metod och anordning för kontroll/access av DRAM-minnen

Country Status (5)

Country Link
US (1) US6938118B1 (sv)
EP (1) EP1125191A1 (sv)
AU (1) AU1589400A (sv)
SE (1) SE512773C2 (sv)
WO (1) WO2000025205A1 (sv)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4451010B2 (ja) * 2001-04-09 2010-04-14 三菱電機株式会社 プログラマブルコントローラ
US7171505B2 (en) * 2002-05-02 2007-01-30 International Business Machines Corporation Universal network interface connection
US7277971B2 (en) * 2003-06-26 2007-10-02 The Boeing Company Method and apparatus for communicating data over a bus according to redefinable configurations
WO2007075134A2 (en) * 2005-12-27 2007-07-05 Imsys Technologies Ab Method and system for cost-efficient, high-resolution graphics/image display system
FR2913784A1 (fr) * 2007-03-14 2008-09-19 St Microelectronics Sa Gestion de donnees pour un traitement d'images
EP2449472A1 (en) * 2009-07-03 2012-05-09 Jantsch, Axel A programmable controller
CN111506531B (zh) * 2020-03-27 2023-06-02 上海赛昉科技有限公司 一种easy-master微码模块及其配置方法

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02210685A (ja) 1989-02-10 1990-08-22 Tokyo Electric Co Ltd Ｄｒａｍコントローラ
US5418924A (en) * 1992-08-31 1995-05-23 Hewlett-Packard Company Memory controller with programmable timing
US5278801A (en) * 1992-08-31 1994-01-11 Hewlett-Packard Company Flexible addressing for drams
JPH06150023A (ja) * 1992-11-06 1994-05-31 Hitachi Ltd マイクロコンピュータ及びマイクロコンピュータシステム
US5732236A (en) * 1993-05-28 1998-03-24 Texas Instruments Incorporated Circuit and method for controlling access to paged DRAM banks with request prioritization and improved precharge schedule
JPH07248963A (ja) * 1994-03-08 1995-09-26 Nec Corp Ｄｒａｍ制御装置
JPH07281948A (ja) 1994-04-06 1995-10-27 Mitsubishi Electric Corp メモリ制御装置
AU5368696A (en) 1995-03-22 1996-10-08 Ast Research, Inc. Rule-based dram controller
US5752269A (en) 1995-05-26 1998-05-12 National Semiconductor Corporation Pipelined microprocessor that pipelines memory requests to an external memory
JP3614956B2 (ja) 1995-12-20 2005-01-26 株式会社東芝 メモリ制御システム
US5636174A (en) * 1996-01-11 1997-06-03 Cirrus Logic, Inc. Fast cycle time-low latency dynamic random access memories and systems and methods using the same
GB2309559B (en) 1996-01-27 2000-01-26 Motorola Israel Ltd Microprocessor and system
JPH1049437A (ja) 1996-07-30 1998-02-20 Toshiba Corp ダイナミックｒａｍ制御装置
JPH10105457A (ja) 1996-09-30 1998-04-24 Nec Data Terminal Ltd メモリ制御システムおよびメモリ制御回路
JPH10134008A (ja) * 1996-11-05 1998-05-22 Mitsubishi Electric Corp 半導体装置およびコンピュータシステム
US5933855A (en) * 1997-03-21 1999-08-03 Rubinstein; Richard Shared, reconfigurable memory architectures for digital signal processing
JP3189727B2 (ja) * 1997-04-15 2001-07-16 日本電気株式会社 コプロセッサ内蔵パケット型メモリｌｓｉ、それを用いたメモリシステム及びそれらの制御方法
JP4246812B2 (ja) * 1997-06-12 2009-04-02 パナソニック株式会社 半導体回路及びその制御方法
US6192446B1 (en) * 1998-09-03 2001-02-20 Micron Technology, Inc. Memory device with command buffer

Also Published As

Publication number Publication date
SE9803708D0 (sv) 1998-10-28
US6938118B1 (en) 2005-08-30
SE512773C2 (sv) 2000-05-08
AU1589400A (en) 2000-05-15
WO2000025205A1 (en) 2000-05-04
EP1125191A1 (en) 2001-08-22

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