SE9603863D0 - Organ och förfarande vid montering av elektronik - Google Patents

Organ och förfarande vid montering av elektronik

Info

Publication number
SE9603863D0
SE9603863D0 SE9603863A SE9603863A SE9603863D0 SE 9603863 D0 SE9603863 D0 SE 9603863D0 SE 9603863 A SE9603863 A SE 9603863A SE 9603863 A SE9603863 A SE 9603863A SE 9603863 D0 SE9603863 D0 SE 9603863D0
Authority
SE
Sweden
Prior art keywords
temperature
carrier
linear expansion
compensated
coefficient
Prior art date
Application number
SE9603863A
Other languages
English (en)
Other versions
SE509570C2 (sv
SE9603863L (sv
Inventor
Leif Bergstedt
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Priority to SE9603863A priority Critical patent/SE509570C2/sv
Publication of SE9603863D0 publication Critical patent/SE9603863D0/sv
Priority to PCT/SE1997/001700 priority patent/WO1998018302A1/en
Priority to AU47314/97A priority patent/AU4731497A/en
Priority to JP51927698A priority patent/JP2001508235A/ja
Priority to EP97909792A priority patent/EP0956746A1/en
Priority to US08/953,916 priority patent/US6108205A/en
Publication of SE9603863L publication Critical patent/SE9603863L/sv
Publication of SE509570C2 publication Critical patent/SE509570C2/sv

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
    • H01L23/3735—Laminates or multilayers, e.g. direct bond copper ceramic substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49175—Parallel arrangements
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/05—Insulated conductive substrates, e.g. insulated metal substrate
    • H05K1/056—Insulated conductive substrates, e.g. insulated metal substrate the metal substrate being covered by an organic insulating layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/06—Thermal details
    • H05K2201/068—Thermal details wherein the coefficient of thermal expansion is important
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10227—Other objects, e.g. metallic pieces
    • H05K2201/10416—Metallic blocks or heatsinks completely inserted in a PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10674—Flip chip
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0058—Laminating printed circuit boards onto other substrates, e.g. metallic substrates
    • H05K3/0061—Laminating printed circuit boards onto other substrates, e.g. metallic substrates onto a metallic substrate, e.g. a heat sink

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Power Engineering (AREA)
  • Materials Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
SE9603863A 1996-10-21 1996-10-21 Temperaturkompenserande organ och förfarande vid montering av elektronik på ett mönsterkort SE509570C2 (sv)

Priority Applications (6)

Application Number Priority Date Filing Date Title
SE9603863A SE509570C2 (sv) 1996-10-21 1996-10-21 Temperaturkompenserande organ och förfarande vid montering av elektronik på ett mönsterkort
PCT/SE1997/001700 WO1998018302A1 (en) 1996-10-21 1997-10-10 Means and method for mounting electronics
AU47314/97A AU4731497A (en) 1996-10-21 1997-10-10 Means and method for mounting electronics
JP51927698A JP2001508235A (ja) 1996-10-21 1997-10-10 電子素子の実装手段及び実装方法
EP97909792A EP0956746A1 (en) 1996-10-21 1997-10-10 Means and method for mounting electronics
US08/953,916 US6108205A (en) 1996-10-21 1997-10-20 Means and method for mounting electronics

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
SE9603863A SE509570C2 (sv) 1996-10-21 1996-10-21 Temperaturkompenserande organ och förfarande vid montering av elektronik på ett mönsterkort

Publications (3)

Publication Number Publication Date
SE9603863D0 true SE9603863D0 (sv) 1996-10-21
SE9603863L SE9603863L (sv) 1998-04-22
SE509570C2 SE509570C2 (sv) 1999-02-08

Family

ID=20404336

Family Applications (1)

Application Number Title Priority Date Filing Date
SE9603863A SE509570C2 (sv) 1996-10-21 1996-10-21 Temperaturkompenserande organ och förfarande vid montering av elektronik på ett mönsterkort

Country Status (6)

Country Link
US (1) US6108205A (sv)
EP (1) EP0956746A1 (sv)
JP (1) JP2001508235A (sv)
AU (1) AU4731497A (sv)
SE (1) SE509570C2 (sv)
WO (1) WO1998018302A1 (sv)

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US6317331B1 (en) * 1998-08-19 2001-11-13 Kulicke & Soffa Holdings, Inc. Wiring substrate with thermal insert
CA2486451C (en) * 2002-05-31 2008-12-23 Thermo Finnigan Llc Mass spectrometer with improved mass accuracy
US20040216864A1 (en) * 2003-04-30 2004-11-04 Wong Marvin Glenn CTE matched application specific heat sink assembly
US20050057907A1 (en) * 2003-09-12 2005-03-17 Hewlett-Packard Development Company, L.P. Circuit board assembly
US6842341B1 (en) * 2003-10-02 2005-01-11 Motorola, Inc. Electrical circuit apparatus and method for assembling same
US7345891B2 (en) * 2003-10-07 2008-03-18 Hewlett-Packard Development Company, L.P. Circuit board assembly
US7061126B2 (en) * 2003-10-07 2006-06-13 Hewlett-Packard Development Company, L.P. Circuit board assembly
US7056144B2 (en) 2004-02-19 2006-06-06 Hewlett-Packard Development Company, L.P. Offset compensation system
FR2868987B1 (fr) * 2004-04-14 2007-02-16 Arjo Wiggins Secutity Sas Soc Structure comportant un dispositif electronique, notamment pour la fabrication d'un document de securite ou de valeur
GB2422249A (en) * 2005-01-15 2006-07-19 Robert John Morse Power substrate
JP2009502024A (ja) * 2005-06-27 2009-01-22 ラミナ ライティング インコーポレーテッド 発光ダイオードパッケージ及びその製造方法
US7742310B2 (en) * 2006-09-29 2010-06-22 Hewlett-Packard Development Company, L.P. Sequencer
US7397666B2 (en) * 2006-10-25 2008-07-08 Hewlett-Packard Development Company, L.P. Wedge lock
US8201325B2 (en) * 2007-11-22 2012-06-19 International Business Machines Corporation Method for producing an integrated device
TWI377653B (en) * 2009-02-16 2012-11-21 Unimicron Technology Corp Package substrate strucutre with cavity and method for making the same
CN101652027B (zh) * 2009-09-07 2011-05-04 皆利士多层线路版(中山)有限公司 一种带散热片的线路板制造工艺
JP6311026B2 (ja) * 2013-09-20 2018-04-11 ジーイー・インテリジェント・プラットフォームズ・インコーポレイテッド 可変熱伝導体
DE102014114096A1 (de) * 2014-09-29 2016-03-31 Danfoss Silicon Power Gmbh Sinterwerkzeug für den Unterstempel einer Sintervorrichtung
DE102014114097B4 (de) 2014-09-29 2017-06-01 Danfoss Silicon Power Gmbh Sinterwerkzeug und Verfahren zum Sintern einer elektronischen Baugruppe
DE102014114093B4 (de) 2014-09-29 2017-03-23 Danfoss Silicon Power Gmbh Verfahren zum Niedertemperatur-Drucksintern
DE102014114095B4 (de) 2014-09-29 2017-03-23 Danfoss Silicon Power Gmbh Sintervorrichtung
DE102015104956A1 (de) 2015-03-31 2016-10-06 Infineon Technologies Ag Gedruckte Leiterplatte mit einem Leiterrahmen mit eingefügten gehäusten Halbleiterchips

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Also Published As

Publication number Publication date
AU4731497A (en) 1998-05-15
EP0956746A1 (en) 1999-11-17
SE509570C2 (sv) 1999-02-08
US6108205A (en) 2000-08-22
WO1998018302A1 (en) 1998-04-30
SE9603863L (sv) 1998-04-22
JP2001508235A (ja) 2001-06-19

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