HK1041102A1 - 集成電路片、集成電路、印刷電路版及電子儀器 - Google Patents
集成電路片、集成電路、印刷電路版及電子儀器Info
- Publication number
- HK1041102A1 HK1041102A1 HK02101860.3A HK02101860A HK1041102A1 HK 1041102 A1 HK1041102 A1 HK 1041102A1 HK 02101860 A HK02101860 A HK 02101860A HK 1041102 A1 HK1041102 A1 HK 1041102A1
- Authority
- HK
- Hong Kong
- Prior art keywords
- integrated circuit
- printed
- electronic device
- chip
- circuit board
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
- H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3025—Electromagnetic shielding
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP33138498 | 1998-11-20 | ||
PCT/JP1999/006480 WO2000031799A1 (fr) | 1998-11-20 | 1999-11-19 | Microcircuit integre, circuit integre, carte a circuits imprimes et dispositif electronique |
Publications (1)
Publication Number | Publication Date |
---|---|
HK1041102A1 true HK1041102A1 (zh) | 2002-06-28 |
Family
ID=18243096
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
HK02101860.3A HK1041102A1 (zh) | 1998-11-20 | 2002-03-11 | 集成電路片、集成電路、印刷電路版及電子儀器 |
Country Status (10)
Country | Link |
---|---|
US (2) | US6469396B1 (zh) |
EP (1) | EP1150355A4 (zh) |
KR (1) | KR20010080509A (zh) |
CN (1) | CN1155089C (zh) |
AU (1) | AU1184400A (zh) |
BR (1) | BR9915509A (zh) |
CA (1) | CA2351417A1 (zh) |
HK (1) | HK1041102A1 (zh) |
TW (1) | TW442945B (zh) |
WO (1) | WO2000031799A1 (zh) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10123758B4 (de) * | 2001-05-16 | 2008-04-03 | Texas Instruments Deutschland Gmbh | Multi-Chip-Modul mit mehreren integrierten Halbleiterschaltungen |
JP2003098221A (ja) * | 2001-09-25 | 2003-04-03 | Mitsubishi Electric Corp | 半導体装置、半導体装置の試験方法及び半導体装置の試験装置 |
JP4034120B2 (ja) * | 2002-05-28 | 2008-01-16 | Necエレクトロニクス株式会社 | 半導体装置 |
US6781218B1 (en) * | 2003-03-04 | 2004-08-24 | Nptest, Inc. | Method and apparatus for accessing internal nodes of an integrated circuit using IC package substrate |
CN100485404C (zh) * | 2003-05-21 | 2009-05-06 | 爱德万测试株式会社 | 试验装置及测试模块 |
US7214886B2 (en) * | 2003-11-25 | 2007-05-08 | International Business Machines Corporation | High performance chip carrier substrate |
US20050248028A1 (en) * | 2004-05-05 | 2005-11-10 | Cheng-Yen Huang | Chip-packaging with bonding options connected to a package substrate |
US7531852B2 (en) * | 2004-06-14 | 2009-05-12 | Denso Corporation | Electronic unit with a substrate where an electronic circuit is fabricated |
CN100464413C (zh) * | 2004-12-24 | 2009-02-25 | 北京中星微电子有限公司 | 实现芯片管脚功能互换的电路及芯片 |
JP5264135B2 (ja) * | 2006-11-09 | 2013-08-14 | パナソニック株式会社 | 半導体集積回路及びマルチチップモジュール |
JP5141121B2 (ja) * | 2006-11-29 | 2013-02-13 | セイコーエプソン株式会社 | パターン形成方法、液滴吐出装置及び回路基板 |
US8197055B2 (en) * | 2006-11-29 | 2012-06-12 | Seiko Epson Corporation | Patterning method, droplet discharging device and circuit board |
CN101206179B (zh) * | 2006-12-22 | 2010-08-11 | 中芯国际集成电路制造(上海)有限公司 | 光发射显微镜样品 |
EP2242095B1 (en) * | 2007-12-28 | 2021-05-19 | Socionext Inc. | Semiconductor device and its manufacturing method |
JP5239766B2 (ja) * | 2008-11-14 | 2013-07-17 | 富士通セミコンダクター株式会社 | レイアウト設計方法 |
EP2421041A4 (en) * | 2009-04-15 | 2013-06-26 | Olympus Medical Systems Corp | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE |
KR101097247B1 (ko) * | 2009-10-26 | 2011-12-21 | 삼성에스디아이 주식회사 | 전자 회로 모듈 및 그 제조 방법 |
TW201134317A (en) * | 2010-03-29 | 2011-10-01 | Hon Hai Prec Ind Co Ltd | Pins assignment for circuit board |
US9500700B1 (en) * | 2013-11-15 | 2016-11-22 | Xilinx, Inc. | Circuits for and methods of testing the operation of an input/output port |
TWI639847B (zh) * | 2017-06-27 | 2018-11-01 | Powerchip Technology Corporation | 積體電路晶片及其檢查方法 |
JP6400795B1 (ja) * | 2017-06-29 | 2018-10-03 | タイコエレクトロニクスジャパン合同会社 | 印刷回路基板 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3905094A (en) * | 1972-01-10 | 1975-09-16 | Displaytek Corp | Thermal display module |
US4220917A (en) * | 1978-07-31 | 1980-09-02 | International Business Machines Corporation | Test circuitry for module interconnection network |
US4386389A (en) * | 1981-09-08 | 1983-05-31 | Mostek Corporation | Single layer burn-in tape for integrated circuit |
JPS58161336A (ja) * | 1982-03-19 | 1983-09-24 | Hitachi Ltd | 半導体集積回路装置 |
JPS6262552A (ja) | 1985-09-12 | 1987-03-19 | Nec Corp | 大規模集積回路 |
JPS63244853A (ja) * | 1987-03-31 | 1988-10-12 | Nec Corp | 半導体集積回路装置 |
JPS63310155A (ja) * | 1987-06-12 | 1988-12-19 | Seiko Instr & Electronics Ltd | 半導体集積回路装置 |
JPH01198051A (ja) | 1988-02-03 | 1989-08-09 | Tokyo Electron Ltd | 半導体集積回路 |
JP2901156B2 (ja) * | 1990-08-31 | 1999-06-07 | 三菱電機株式会社 | 半導体集積回路装置 |
JPH05198637A (ja) * | 1992-01-23 | 1993-08-06 | Mitsubishi Electric Corp | 半導体集積回路及びそのテスト方法 |
US5453991A (en) * | 1992-03-18 | 1995-09-26 | Kabushiki Kaisha Toshiba | Integrated circuit device with internal inspection circuitry |
JPH07122701A (ja) | 1993-10-21 | 1995-05-12 | Hitachi Ltd | 半導体装置およびその製造方法ならびにpga用リードフレーム |
US5969538A (en) * | 1996-10-31 | 1999-10-19 | Texas Instruments Incorporated | Semiconductor wafer with interconnect between dies for testing and a process of testing |
JP3565991B2 (ja) * | 1996-06-26 | 2004-09-15 | 株式会社ルネサステクノロジ | 半導体集積回路および半導体集積回路の製造方法 |
TW432669B (en) * | 1997-04-25 | 2001-05-01 | Sharp Kk | Semiconductor integrated circuit device capable of achieving reductions in chip area and consumption power |
JP2998702B2 (ja) | 1997-06-13 | 2000-01-11 | 日本電気株式会社 | 半導体集積回路 |
JP4014708B2 (ja) * | 1997-08-21 | 2007-11-28 | 株式会社ルネサステクノロジ | 半導体集積回路装置の設計方法 |
JP2001274323A (ja) * | 2000-03-24 | 2001-10-05 | Hitachi Ltd | 半導体装置とそれを搭載した半導体モジュール、および半導体装置の製造方法 |
-
1999
- 1999-11-15 TW TW088119880A patent/TW442945B/zh not_active IP Right Cessation
- 1999-11-18 US US09/442,700 patent/US6469396B1/en not_active Expired - Lifetime
- 1999-11-19 EP EP99972788A patent/EP1150355A4/en not_active Withdrawn
- 1999-11-19 AU AU11844/00A patent/AU1184400A/en not_active Abandoned
- 1999-11-19 WO PCT/JP1999/006480 patent/WO2000031799A1/ja not_active Application Discontinuation
- 1999-11-19 CA CA002351417A patent/CA2351417A1/en not_active Abandoned
- 1999-11-19 KR KR1020017006338A patent/KR20010080509A/ko not_active Application Discontinuation
- 1999-11-19 CN CNB998135275A patent/CN1155089C/zh not_active Expired - Lifetime
- 1999-11-19 BR BR9915509-5A patent/BR9915509A/pt not_active Application Discontinuation
-
2002
- 2002-03-11 HK HK02101860.3A patent/HK1041102A1/zh unknown
- 2002-06-24 US US10/178,110 patent/US6548910B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US20020153538A1 (en) | 2002-10-24 |
CN1155089C (zh) | 2004-06-23 |
EP1150355A4 (en) | 2003-09-10 |
US6469396B1 (en) | 2002-10-22 |
BR9915509A (pt) | 2001-11-13 |
TW442945B (en) | 2001-06-23 |
WO2000031799A1 (fr) | 2000-06-02 |
EP1150355A1 (en) | 2001-10-31 |
AU1184400A (en) | 2000-06-13 |
CA2351417A1 (en) | 2000-06-02 |
KR20010080509A (ko) | 2001-08-22 |
US6548910B2 (en) | 2003-04-15 |
CN1326592A (zh) | 2001-12-12 |
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