RU2523124C1 - Multi-differential operational amplifier - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: first (5) and second (8) output transistors used in a multi-differential operational amplifier are a first and a second junction field-effect transistor whose gates correspond to the base, the drains correspond to collectors and the sources correspond to emitters of the corresponding first (5) and second (8) output transistors. The collector of the first (1) input transistor is connected to a second (10) power supply bus, the drain of the second (8) output field-effect transistor is connected to a first power supply bus (7), the output of a second (9) current mirror is connected to the output of the device (11), the gate of the first (5) output field-effect transistor is connected to the second (12) non-inverting input of the device, and the gate of the second (8) output field-effect transistor is connected to the second (13) inverting input of the device.

EFFECT: high input impedance for differential and in-phase signals at two of the four inputs of the operational amplifier.

5 cl, 7 dwg

Description

The invention relates to the field of radio engineering and communication and can be used as a device for amplifying analog signals, in the structure of analog microcircuits for various functional purposes (for example, in photodetectors, solving amplifiers with small values of input conductivity).

In modern electronic equipment, differential operational amplifiers (op amps) with significant different parameters are used. A special place is occupied by op amps with complementary input stages [1–11]. Such op-amps have an extremely simple structure and are characterized by low power consumption.

The present invention relates to the class of OS based on complementary input stages [1-11].

The closest in essence to the claimed technical solution is the classical scheme of the op amp, figure 1, presented in ed. testimonial. USSR No. 603097, which is also present in a large number of other patents, for example [1-11]. The op-amp prototype, figure 1, contains the first 1 and second 2 input transistors, the base of the first 1 input transistor is connected to the first 3 inverting input of the device, the base of the second 2 input transistor is connected to the first 4 non-inverting input of the device, the first 5 output transistor, the emitter of which connected to the emitter of the first 1 input transistor, and the collector is connected to the input of the first 6 current mirror, matched with the first 7 bus of the power source, the second 8 output transistor, the emitter of which is connected to the emitter of the second 2 input transistor of the source, the second 9 current mirror, matched with the second 10 bus power source, the input of which is connected to the collector of the second 2 input transistor, and the output of the device 11 is connected to the output of the first 6 current mirror.

A significant drawback of the known op-amp, Fig. 1, is that it has only two inputs, which does not allow it to be used in the class of sufficiently promising active elements of a new generation of analog circuitry - multidifferential op-amps.

The main objective of the invention is to increase the number of inputs of the OS, i.e. in creating a multi-differential op-amp. An additional task is to increase the differential and common-mode input resistances at two of the four op amp inputs and create conditions for realizing small zero bias voltages.

The problem is achieved in that in a multidifferential operational amplifier containing the first 1 and second 2 input transistors, the base of the first 1 input transistor is connected to the first 3 inverting input of the device, the base of the second 2 input transistor is connected to the first 4 non-inverting input of the device, the first 5 output transistor whose emitter is connected to the emitter of the first 1 input transistor, and the collector is connected to the input of the first 6 current mirror, matched with the first 7 bus of the power source, the second 8 output a new transistor, the emitter of which is connected to the emitter of the second 2 input transistor, the second 9 current mirror, matched with the second 10 bus of the power source, the input of which is connected to the collector of the second 2 input transistor, and the output of the device 11 is connected to the output of the first 6 current mirror, new elements and communications - the first and second field-effect transistors with a control pn junction are used as the first 5 and second 8 output transistors, the gates of which correspond to the base, the drains to the collectors, and the sources to the emitter m of the corresponding first 5 and second 8 output transistors, the collector of the first 1 input transistor connected to the second 10 bus of the power source, the drain of the second 8 output field-effect transistor connected to the first 7 bus of the power source, the output of the second 9 current mirror is connected to the output of the device And, the shutter the first 5 output field-effect transistor is connected to the second 12 non-inverting input of the device, and the gate of the second 8 output field-effect transistor is connected to the second 13 inverting input of the device.

The amplifier circuit of the prototype is shown in figure 1.

Figure 2 presents a diagram of the inventive device in accordance with claim 2 of the claims.

The remote control scheme corresponding to claims 3 and 4 of the claims is shown in FIG. 3.

Figure 4 presents a diagram of the claimed op-amp in the PSpice environment on models of transistors of the analog base matrix crystal ABMK_1_3, corresponding to claim 5, and Fig. 5 shows the dependence of the voltage gain on the frequency of the op-amp of Fig. 4.

Figure 6 presents the frequency dependence of the voltage gain of the op-amp of Figure 4 with 100% negative feedback.

Figure 7 presents the dependence of the bias voltage of zero on the temperature of the op-amp of figure 4.

The multidifferential operational amplifier contains the first 1 and second 2 input transistors, the base of the first 1 input transistor is connected to the first 3 inverting input of the device, the base of the second 2 input transistor is connected to the first 4 non-inverting input of the device, the first 5 output transistor, the emitter of which is connected to the emitter of the first 1 input transistor, and the collector is connected to the input of the first 6 current mirror, consistent with the first 7 bus power supply, the second 8 output transistor, the emitter of which is connected with emi Intermediate location 2 of the second input transistor, a second current mirror 9, consistent with the second power supply bus 10, the input of which is connected to the collector of the second input transistor 2, the output device 11 connected to the output 6 of the first current mirror. As the first 5 and second 8 output transistors, the first and second field effect transistors with a pn junction control are used, the gates of which correspond to the base, the drains correspond to collectors, and the sources to the emitters of the corresponding first 5 and second 8 output transistors, and the collector of the first 1 input the transistor is connected to the second 10 bus of the power source, the drain of the second 8 output field-effect transistor is connected to the first 7 bus of the power source, the output of the second 9 current mirror is connected to the output of the device 11, the shutter of the first 5 output field the transistor is connected to the second 12 non-inverting input of the device, and the gate of the second 8 output field-effect transistor is connected to the second 13 inverting input of the device.

In Fig. 3, in accordance with claim 2, the first 4 non-inverting and second 13 inverting inputs of the device are connected, in a particular case, to a common bus 14 of power supplies.

In addition, in Fig. 3, in accordance with claim 3, the collector of the first 1 input transistor is connected to the second 10 bus of the power supply through the potential matching circuit 15, made in the form of an additional transistor 16, the emitter of which is connected to the collector of the first 1 input transistor, the base is connected to the input of the second 9 current mirror, and the collector is connected to the second 10 bus power sources.

It should also be noted that in Fig. 3, in accordance with claim 4, the output of the device 11 is connected to the input of an additional buffer amplifier 17, the output of which 18 is an additional output of the device. To balance the static mode of transistors 1 and 2, a voltage source 19 is included, for which a pn junction can be used.

In figure 4, in accordance with paragraph 5 of the claims, the corresponding first and second additional resistors are included in the emitters of the first 1 and second 2 input transistors.

Consider the work of the op amp, figure 2, which due to new connections has 4 inputs 3, 12 and 1, 13, and also determine the systematic component of its zero bias voltage U _see

The source and drain currents of field effect transistors 5 and 8 (I _and = I _c = I ₀ ) depend on the steepness of their gate-to-gate characteristics at U _{si 5} = U _si 8 ≈0.7 B. With identical emitter junctions of the first 1 and the second 2 input transistors, as well as identical field effect transistors 5 and 8, the collector current of the transistor 2 and the drain current of the transistor 5 will also be equal to the value of I ₀ . Consequently, the zero bias voltage of the opamp under consideration

$$U_{\mathrm{from}m}=U_{\mathrm{uh}b\mathrm{.one}}-U_{s\mathrm{and}.5}\approx 0\left(\mathrm{one}\right)$$

since U _eb. 1 = U _{zi. 5} , U _eb . ₂ = U _eb. 1 = U _A ^* _B ^* , U _zi . ₅ = U _zi . ₈ .

Thus, in the considered circuit, a small zero bias voltage is provided, which, due to the use of field effect transistors, has increased input resistances at the two inputs 12 and 13 for differential and common-mode signals.

The differential voltage gain of the claimed remote control, figure 2:

$${\mathrm{TO}}_{\mathrm{at}}=\frac{u_{\mathrm{at}sx\mathrm{.eleven}}}{u_{\mathrm{at}x\mathrm{.one}}-u_{\mathrm{at}x.2}}=\frac{u_{\mathrm{at}sx\mathrm{.eleven}}}{u_{\mathrm{at}x\mathrm{.1.2}}}\approx \frac{R_{n.\mathrm{uh}\mathrm{to}\mathrm{at}.}}{r_{\mathrm{uh}\mathrm{one}}+S_5^{-\mathrm{one}}},\left(2\right)$$

- сопротивление эмиттерного перехода транзистора 1;Where $$r_{\mathrm{uh}\mathrm{one}}\approx \frac{{\varphi }_t}{I_0}$$

- resistance of the emitter junction of transistor 1;

S ₁ - the steepness of the gate-gate characteristic of the field effect transistor 5;

φ _t = 26 mV - temperature potential;

R _n.eq - equivalent load resistance of the op-amp connected to output 11.

When the temperature (or radiation level) changes, the drain current of the transistor 5 changes, which enters the input, and then the output of the current mirror 6. However, in the same way (due to the symmetry of the source circuit), the source current of the transistor 8 and the collector current of the transistor 2, which arrives at the input and then the output of the current mirror 9. As a result, in the output circuit 11 there is a mutual compensation of these increments and therefore U _cm changes insignificantly.

Thus, in the inventive device decreases the systematic component of the bias voltage of zero U _cm and its drift.

The inventive device has significant advantages compared with the prototype in terms of the value of the static error of amplification of DC signals and can be used as IP modules of modern systems on a chip, implemented, for example, using the technology of analog base matrix crystals ABMK_1_3.

Literature

1. Patent US 5.789.949.

2. Patent US 3.660.773.

3. Patent US 4.074.205.

4. Patent application US 2010/0225392.

5. Patent GB 1543361.

6. Patent DE 2633952.

7. Patent US 4.059.808.

8. Patent RU 2.019.019.

9. Patent application US 2006/0091952.

10. Patent US 5.521.553.

11. Patent US 5.010.303.

Claims (5)

1. A multi-differential operational amplifier containing the first (1) and second (2) input transistors, the base of the first (1) input transistor is connected to the first (3) inverting input of the device, the base of the second (2) input transistor is connected to the first (4) non-inverting the input of the device, the first (5) output transistor, the emitter of which is connected to the emitter of the first (1) input transistor, and the collector is connected to the input of the first (6) current mirror, matched with the first (7) power supply bus, and the second (8) output transistor emitter which connected to the emitter of the second (2) input transistor, the second (9) current mirror, consistent with the second (10) bus of the power source, the input of which is connected to the collector of the second (2) input transistor, and the output of the device (11) is connected to the output of the first (6) a current mirror, characterized in that as the first (5) and second (8) output transistors, the first and second field effect transistors with a pn junction control are used, the gates of which correspond to the base, the drains to collectors, and the sources to the emitters of the corresponding first (5) and second (8) output transistors, the collector of the first (1) input transistor connected to the second (10) power supply bus, the drain of the second (8) output field-effect transistor connected to the first (7) power supply bus, the output of the second (9) current mirror connected to the output of the device (11), the shutter of the first (5) in Khodnev FET coupled to the second (12) non-inverting input of the device, and the second gate (8) of the output FET is coupled to a second (13) inverting input device. 2. A multi-differential operational amplifier according to claim 1, characterized in that the first (4) non-inverting and the second (13) inverting inputs of the device are connected to a common bus (14) of power sources. 3. The multidifferential operational amplifier according to claim 1, characterized in that the collector of the first (1) input transistor is connected to the second (10) bus of the power source through the potential matching circuit (15), made in the form of an additional transistor (16), the emitter of which is connected with the collector of the first (1) input transistor, the base is connected to the input of the second (9) current mirror, and the collector is connected to the second (10) bus of power supplies. 4. A multi-differential operational amplifier according to claim 1, characterized in that the output of the device (11) is connected to the input of an additional buffer amplifier (17), the output of which (18) is an additional output of the device. 5. The multidifferential operational amplifier according to claim 1, characterized in that the corresponding first (19) and second (20) additional resistors are included in the emitters of the first (1) and second (2) input transistors.

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