RU2452077C1 - Operational amplifier with paraphase output - Google Patents

Abstract

FIELD: radio engineering.

SUBSTANCE: operational amplifier with a paraphrase output comprises the first and second input three-terminal devices, the first and second matching three-terminal devices, the first and second output three-terminal devices, from the first to the fourth current-stabilising dipoles, the first and second feedback resistors.

EFFECT: development of conditions, under which the output static cophased voltage of an operational amplifier will have high stability and numerical value close to zero at zero input signals.

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Description

The invention relates to the field of radio engineering and communication and can be used as a device for amplifying analog signals, in the structure of analog microcircuits of various functional purposes (for example, bridge power amplifiers, drivers of differential communication lines, filters, comparators, etc.).

Known circuits of classical differential operational amplifiers (op amps) with a paraphase output based on the input cascode, which became the basis of many serial analog circuits (OPA177, RC4805, etc.). Op-amps of this class are widely used in the structure of microwave devices [1-18], implemented on the basis of SiGe technologies. This is due to the possibility of building on their basis active RC filters of the GHz range for modern and promising communication systems, drivers of differential communication lines between SF blocks A / d and D / a-classes, etc. [19-21].

The closest prototype (figure 1) of the claimed device is an operational amplifier described in patent US 5568092, fig.8. In addition, this architecture is present in many other patents [1-18]. It contains the first 1 input three-terminal with collector 2, emitter 3 and base 4 inputs, the second 5 input three-terminal with collector 6, emitter 7 and basic 8 inputs, the first 9 matching three-terminal with collector 10, emitter 11 and 12 basic inputs, the second 13 matching three-terminal with collector 14, emitter 15 and base 16 inputs, first 17 output three-terminal with collector 18, emitter 19 and basic 20 inputs, second 21 output three-terminal with collector 22, emitter 23 and basic 24 inputs, first 25 current-stabilizing two-pole a nickname connected between the collector input 10 of the first 9 matching three-terminal network connected to the base input 20 of the first 17 output three-terminal network and the first 26 bus of the power supply, a second 27 current-stabilizing two-terminal network connected between the collector input 14 of the second 13 matching three-terminal network connected to the base input 24 of the second 21 output three-terminal and the first 26 bus power supply, the first 28 feedback resistor connected between the emitter input 19 of the first 17 output three-terminal connected to the first 29 output device state, and the base input 16 of the second 13 matching three-terminal, the second 30 feedback resistor connected between the emitter input 23 of the second 21 output three-terminal connected to the second 31 output of the device and the basic input 12 of the first 9 matching three-terminal, and the first 29 output of the device is connected to the second 32 bus power supply through the third 33 current-stabilizing two-terminal network, the second 31 output of the device is connected to the second 32 bus power supply through the fourth 34 current-stabilizing two-terminal network, and the collector inputs 18, 22 ne The first 17 and the second 21 output three-terminal are connected to the first 26 bus power supply.

The main objective of the invention is to create conditions under which the output static common-mode voltage of the op-amp will have high stability and a numerical value close to zero at zero input signals. This greatly simplifies the matching of the op-amp output phases with the subsequent functional units of various multistage signal conversion devices, and allows for more efficient use of the op-amp supply voltages - in these circuits, the output alternating voltages change relative to the common bus.

The problem is solved in that in the operational amplifier with a paraphase output of Fig. 1, containing the first 1 input three-terminal with collector 2, emitter 3 and base 4 inputs, the second 5 input three-terminal with collector 6, emitter 7 and base 8 inputs, the first 9 matching three-terminal with collector 10, emitter 11 and base 12 inputs, second 13 matching three-terminal with collector 14, emitter 15 and basic 16 inputs, first 17 output three-terminal with collector 18, emitter 19 and basic 20 inputs, second 21 output three-terminal collector 22, emitter 23 and base 24 inputs, the first 25 current-stabilizing two-terminal connected between the collector input 10 of the first 9 matching three-terminal, connected to the main input 20 of the first 17 output three-terminal and the first 26 bus power supply, the second 27 current-stabilizing two-pole connected between the collector input 14 of the second 13 matching three-terminal connected to the base input 24 of the second 21 output three-terminal and the first 26 bus power supply, the first 28 feedback resistor included between the mitter input 19 of the first 17 output three-terminal connected to the first 29 output of the device and the base input 16 of the second 13 matching three-terminal, a second 30 feedback resistor connected between the emitter input 23 of the second 21 output three-terminal connected to the second 31 output of the device and the basic input 12 of the first 9 matching three-terminal, the first 29 output of the device connected to the second 32 bus power supply through the third 33 current-stabilizing two-terminal, the second 31 output of the device connected to the second 32 bus source power supply through the fourth 34 current-stabilizing two-terminal network, and the collector inputs 18, 22 of the first 17 and second 21 output three-terminal networks are connected to the first 26 bus power supply, new elements and communications are provided - the emitter input 3 of the first 1 input three-terminal network is connected to the emitter input 11 of the first 9 matching three-terminal network , the emitter input 7 of the second 5 input three-terminal network connected to the emitter input 15 of the second 13 matching two-terminal network, the collector inputs 2 and 6 of the first 1 and second 5 input three-terminal network connected to the second th 32 bus power supply, and the basic inputs 12 and 16 of the first 9 and second 13 matching three-terminal are connected to each other.

The drawing of figure 1 shows a diagram of an op-amp prototype.

The drawing of figure 2 shows a diagram of the inventive device in accordance with claim 1 for the case when the first 1 and second 5 input triples are implemented on the basis of field-effect transistors with a control pn junction, and the first 9 and second 13 matching triples, as well as the first 17 and 21 second output three-terminal are made in the form of bipolar transistors of the same type of conductivity.

In the drawing of FIG. 3, in accordance with claim 2, particular embodiments of the first 1 and second 5 input triples, the first 9 and second 13 matching triples, as well as the first 17 and second 21 output triples of the op amp of FIG. 2 are shown.

In the drawing of FIG. 4, in accordance with claim 3, examples of construction of the first 1 and second 5 input triples, the first 9 and second 13 matching triples, as well as the first 17 and second 21 output triples of the op amp 2 are shown.

The drawing of figure 5 is fully consistent with claim 3 of the claims.

The drawing of Fig.6 shows a diagram of the op-amp of Fig.5 in the environment of computer simulation PSpise on models of integrated transistors of the Federal State Institution NPP Pulsar.

The drawing of Fig.7 shows the frequency dependence of the gain on the voltage of the op-amp circuit of Fig.6.

The drawing of Fig. 8 characterizes the dependence of the output voltages of the op-amp of Fig. 6 with a sinusoidal input signal.

The drawing of Fig.9 shows a diagram of the opamp of Fig.2 in a computer simulation environment PSpise on models of integrated transistors of the analog base matrix crystal ABMK_1_3 (NPO Integral, Minsk).

The drawing of figure 10 shows the frequency dependence of the gain on the voltage of the op-amp circuit of Fig.9.

The drawing of Fig. 11 characterizes the dependence of the output voltages of the op-amp of Fig. 9 with a sinusoidal input signal.

The operational amplifier with a paraphase output of FIG. 2 contains the first 1 input three-terminal with collector 2, emitter 3 and base 4 inputs, the second 5 input three-terminal with collector 6, emitter 7 and base 8 inputs, the first 9 matching three-terminal with collector 10, emitter 11 and basic 12 inputs, second 13 matching three-terminal with collector 14, emitter 15 and basic 16 inputs, first 17 output three-terminal with collector 18, emitter 19 and basic 20 inputs, second 21 output three-terminal with collector 22, emitter 23 and basic 24 in the first 25 current-stabilizing two-terminal connected between the collector input 10 of the first 9 matching three-terminal connected to the base input 20 of the first 17 output three-terminal and the first 26 bus power supply, the second 27 current-stabilizing two-pole connected between the collector input 14 of the second 13 matching three-terminal the base input 24 of the second 21 output three-terminal and the first 26 bus power supply, the first 28 feedback resistor connected between the emitter input 19 of the first 17 output tr xpole connected to the first 29 output of the device and the base input 16 of the second 13 matching three-terminal, the second 30 feedback resistor connected between the emitter input 23 of the second 21 output three-terminal connected to the second 31 output of the device and the base input 12 of the first 9 matching three-terminal, moreover, the first 29 device output is connected to the second 32 bus power supply through the third 33 current-stabilizing two-terminal device, the second 31 device output is connected to the second 32 bus power supply through the fourth 34 current-stabilizing a bipolar, and the collector inputs 18, 22 of the first 17 and second 21 output three-terminal are connected to the first 26 bus power source. In this case, the emitter input 3 of the first 1 input three-terminal is connected to the emitter input 11 of the first 9 matching three-terminal, the emitter input 7 of the second 5 input three-terminal is connected to the emitter input 15 of the second 13 matching two-terminal, collector inputs 2 and 6 of the first 1 and second 5 input three-terminal the second 32 bus power source, and the basic inputs 12 and 16 of the first 9 and second 13 matching three-terminal network connected to each other.

In the drawings of FIG. 3 and FIG. 2, in accordance with claim 2, the first 1 and second 5 input triples are implemented based on field-effect transistors 35 and 36 with a control pn junction, and the first 9 and second 13 matching triples, as well as the first 17 and second 21 output triples are made in the form of bipolar transistors 37, 38, 39, 40 of the same type of conductivity.

In the drawing of figure 4, as well as figure 5, in accordance with claim 3 of the claims, the first 1 and second 5 input triples are made in the form of bipolar transistors 41, 42 of one type of conductivity, the first 9, second 13 matching transistors and the first 17 and the second 21 output three-terminal circuits are implemented on transistors 43, 44, 45, 46 of a different type of conductivity, the first 29 output of the device is connected to the second 32 bus of the power supply through the first 47 potential bias circuit and the third 33 current-stabilizing two-terminal, and the second 31 output of the device VA is connected to the second 32 bus of the power source through the second 48 potential bias circuit and the fourth 34 current-stabilizing two-terminal network, with the common node of the first 47 potential bias circuit and the third 33 current-stabilizing two-terminal network connected to the third 49 output of the device, and the common site of the second 48 potential bias circuit and the fourth 34 current-stabilizing two-terminal connected to the fourth 50 output of the device.

Consider the operation of the opamp 2.

The static current mode of the transistors of the proposed op-amp is set by current-stabilizing two-terminal 25, 27, 33 and 34:

where I ₂₅ , I ₂₇ , I ₃₃ , I ₃₄ are the currents of the current-stabilizing two-terminal networks 25, 27, 33, 34;

I _s1 , I _s5 are the currents of the sources of the transistors forming the input three-terminal 1 and 5;

I _k13 , I _k9 - collector currents of transistors forming matching three-terminal networks 9 and 13;

I _e17 , I _e21 - currents of the emitter of transistors forming the output three-terminal networks 17 and 21;

I ₀ - some set value of the reference current, for example, 1 mA.

In accordance with the second law of Kirgoff, the static voltage U ₂₉ , U ₃₁ at the outputs 29 and 31 of the op-amp of FIG. 2 at zero voltages at the inputs Vx.1, Vx.2 satisfy the conditions:

where U _eb . ₉ = U _{eb. 13} - emitter-base voltages of transistors forming matching three-terminal networks 9 and 13;

U _zi.1 , U _zi.5 - voltage gate source of transistors forming the input three-terminal 1 and 5;

R ₂₈ , R ₃₀ - resistance of the resistors 28 and 30;

I _b - the base current of the transistors forming the matching three-terminal networks 9 and 13.

The source current I _s field-effect transistors forming the input three-terminal 1 and 5, is determined in a first approximation by the formula:

where I _s is the source current of the field effect transistor;

I _c.max - maximum current of a field-effect transistor at U _zi = 0;

U _connection - gate-source voltage (0≤U _{communication} ≤U _UTS);

U _OT - cutoff voltage of the field effect transistor.

For _{communication} U = U = U _{eb.9 eb.13} ≈0,7 V, wherein U ₂₉ ≈0, U ₃₁ ≈0, it is necessary that the currents tokostabiliziruyuschih-ports 25 and 27 satisfy the condition

Or

, то выходные напряжения ОУ U₂₉=U₃₁ будут иметь положительное смещение относительно общей шины. Если

, то эти напряжения U₂₉≈U₃₁ смещаются к отрицательной шине питания.If these currents are greater than

, then the output voltage of the op-amp U ₂₉ = U ₃₁ will have a positive offset relative to the common bus. If

, then these voltages U ₂₉ ≈ U ₃₁ are shifted to the negative power bus.

, то теоретическое значение U₂₉=U₃₁ с высокой точностью будет соответствовать нулевому уровню:If in the circuit of FIG. 2, provide U _zi . ₅ = U _zi. 1 = U _eb . ₉ = U _eb. 13 ≈0.7 V due to the corresponding choice of currents

, then the theoretical value of U ₂₉ = U ₃₁ with high accuracy will correspond to the zero level:

Given the typical numerical values of I _b and R ₂₈ = R ₃₀ in practical schemes of the op-amp, from equation (6) we can conclude that in the claimed op-amp the static output voltages U ₂₉ = U ₃₁ are close to millivolts.

Depending on the circuitry of the three-terminal 1, 5, 9, 13, you can set other specified values of the static output common-mode voltage of the claimed op-amp.

The graphs of Fig. 8 and Fig. 11 show that in the op-amp circuits of Fig. 2 and Fig. 5, the sinusoidal output voltages have a zero level of static bias relative to the common bus.

Thus, the inventive operational amplifier has a small zero level of the output common mode voltage. This is very important for its coordination with the subsequent functional units of various systems on the chip, as well as for obtaining a wider range of output antiphase voltages.

BIBLIOGRAPHIC LIST

1. US patent No. 7.737.783.

2. Patent application US 2010/007419, fig. 3.

3. US patent No. 5.568.092, fig. 1.

4. US patent No. 6.100.759, fig. 3.

5. Patent application US 2002/0093380, fig. 1.

6. Patent application US 2009/0195312, fig. 1.

7. US patent No. 3,541.465, fig.3.

8. US patent No. 5.500.623, fig.6.

9. Patent application US 2005/0104661, fig. 3.

10. US patent No. 6.396.346, fig.3A.

11. US patent No. 5.440.271, fig. 1.

12. US patent No. 5.510.745, fig.25.

13. US patent No. 5.774.020, fig.2.

14. US patent No. 6.262.628, fig.14b.

15. US patent No. 6.011.431, fig.6.

16. GB Patent No. 1520085, fig. 2.

17. Patent application US 2006/0044064, fig.2.

18. Patent application US 2006/0181347, fig. 2.

19. Budyakov, A. Design of Fully Differential OpAmps for GHz Range Applications [Text] / Budyakov A., Schmalz K., Prokopenko N., Scheytt C., Ostrovskyy P. // Problems of modern analog microcircuitry: Sat. materials of the VI International scientific and practical seminar. In 3 hours, part 1. Functional nodes of analog integrated circuits and complex functional blocks / ed. N.N. Prokopenko. - Mines: Publishing house of SRSUE, 2007. - P.106-110.

20. S.P. Voinigescu et al., "Design Methodology and Applications of SiGe BiCMOS Cascode Opamps with up to 37-GHz Unity Gain Bandwidth," IEEE CSICS, Techn. Digest, pp. 283-286, Nov. 2005, FIG. 2.

21. S.P. Voinigescu et al., "SiGe BiCMOS for Analog, High-Speed Digital and Millimetre-Wave Applications Beyond 50 GHz," IEEE BCTM, pp. 1-8, Oct. 2006.

Claims (3)

1. An operational amplifier with a paraphase output, comprising the first (1) input three-terminal with collector (2), emitter (3) and base (4) inputs, the second (5) input three-terminal with collector (6), emitter (7) and basic (8) inputs, the first (9) matching three-terminal with collector (10), emitter (11) and base (12) inputs, the second (13) matching three-terminal with collector (14), emitter (15) and basic (16) inputs , the first (17) output three-terminal with collector (18), emitter (19) and basic (20) inputs, the second (21) output three-terminal with collector (22), em ytter (23) and base (24) inputs, the first (25) current-stabilizing two-terminal connected between the collector input (10) of the first (9) matching three-terminal connected to the basic input (20) of the first (17) output three-terminal and the first (26) by the power supply bus, the second (27) current-stabilizing two-terminal connected between the collector input (14) of the second (13) matching three-terminal connected to the base input (24) of the second (21) output three-terminal and the first (26) power supply bus, the first (28 ) feedback resistor included between amy tter input (19) of the first (17) output three-terminal connected to the first (29) output of the device and the base input (16) of the second (13) matching three-terminal, second (30) feedback resistor connected between the emitter input (23) of the second (21) the output of a three-terminal network connected to the second (31) output of the device and the base input (12) of the first (9) matching three-terminal network, and the first (29) output of the device is connected to the second (32) bus of the power source through the third (33) current-stabilizing bipolar, the second (31) output of the device is connected to the second (32) another power source through the fourth (34) current-stabilizing two-terminal device, and the collector inputs (18), (22) of the first (17) and second (21) output three-terminal devices are connected to the first (26) bus of the power source, characterized in that the emitter input (3 ) the first (1) input three-terminal connected to the emitter input (11) of the first (9) matching three-terminal, the emitter input (7) of the second (5) input three-terminal connected to the emitter input (15) of the second (13) matching two-terminal, collector inputs (2 ) and (6) of the first (1) and second (5) input triples with are connected to the second (32) bus of the power source, and the basic inputs (12) and (16) of the first (9) and second (13) matching three-terminal devices are connected to each other. 2. An operational amplifier with a paraphase output according to claim 1, characterized in that the first (1) and second (5) input three-terminal devices are implemented based on field-effect transistors with a pn junction, and the first (9) and second (13) matching three-terminal, as well as the first (17) and second (21) output three-terminal are made in the form of bipolar transistors of the same type of conductivity. 3. An operational amplifier with a paraphase output according to claim 1, characterized in that the first (1) and second (5) input three-terminal devices are made in the form of bipolar transistors of one type of conductivity, the first (9), second (13) matching transistors and the first ( 17) and the second (21) output three-terminal are implemented on transistors of a different type of conductivity, the first (29) output of the device is connected to the second (32) bus of the power source through the first (47) potential bias circuit and the third (33) current-stabilizing two-terminal, and second (31) mouth output The property is connected to the second (32) bus of the power source through the second (48) potential bias circuit and the fourth (34) current-stabilizing two-terminal network, and the common node of the first (47) potential bias circuit and the third (33) current-stabilizing two-terminal network is connected to the third (49) output devices, and the common node of the second (48) potential bias circuit and the fourth (34) current-stabilizing bipolar is connected to the fourth (50) output of the device.

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