RU2684489C1 - Buffer amplifier on complementary field-effect transistors with control p-n junction for operation at low temperatures - Google Patents

Abstract

FIELD: analogue microelectronics.

SUBSTANCE: invention relates to analogue microelectronics and can be used as two-stroke buffer and output power amplifiers of various analogue devices (operational amplifiers, communication line drivers, etc.), allowing operation in conditions of penetrating radiation and low temperatures. To achieve the result, a circuit design is proposed, which is characterized by using a single current-stabilizing bipolar (resistor), which determines current static mode of operation.

EFFECT: design of a radiation-resistant and low-temperature circuit-based solution of BA on complementary field-effect transistors, which ensures high stability of the static mode of transistors and low noise level, even during operation in the low-temperature range, with high linearity of the amplitude characteristic.

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Description

The invention relates to the field of analog microelectronics and can be used as push-pull buffer and output power amplifiers of various analog devices (operational amplifiers, communication line drivers, etc.) capable of operating under conditions of penetrating radiation and low temperatures.

There are a significant number of circuits of microelectronic push-pull buffer amplifiers (BU), which are implemented on complementary bipolar (BJT) or field (CMOS, SOI, KNS, etc.) transistors, as well as when they are turned on jointly [1-29]. Due to the high symmetry, simplicity, and low bias voltage, the abovementioned circuitry solutions of the control unit are most popular in both foreign and Russian analog microcircuits implemented on the basis of standard technological processes [1-29].

The closest prototype of the claimed device is a buffer amplifier on complementary field effect transistors, presented in US patent No. 7.764.123, fig. 3, 2010. This scheme is considered in other patents (US No. 5.351.012, 1994; US No. 6.215.357 fig. 3, 2001; US No. 5.973.534), as well as in a number of publications, for example [28. M. Djebbi, A. Assi and M. Sawan. An offset-compensated wide-bandwidth CMOS current-feedback operational amplifier // CCECE 2003 - Canadian Conference on Electrical and Computer Engineering. Toward a Caring and Humane Technology (Cat. No.03CH37436), 2003, pp. 73-76 vol. 1. DOI: 10.1109 / CCECE.2003.1226347]. Scheme BU-prototype of FIG. 1 contains potential input 1 and potential output 2 of the device, the first 3 current output of the device, matched with the first 4 bus of the power source, the second 5 current output of the device, matched with the second 6 bus of the power source, the first 7 input field-effect transistor, the gate of which is connected to the potential the input 1 of the device, the second 8 input field-effect transistor, the gate of which is connected to the potential input 1 of the device, the first 9 output field-effect transistor, the source of which is connected to the potential output 2 of the device, and the drain is connected 3 with the first current output device 10 output a second field effect transistor having its source connected to a potential output device 2, and the drain is connected to a second 5 current output device. BU prototype is the basis of various input and output stages of the op-amp with potential negative feedback [29. N.N. Prokopenko, A.S. Budyakov, J.M. Savchenko, S.V. Korneev. Maximum rating of Voltage Feedback and Current Feedback Operational Amplifiers in Linear and Nonlinear Modes // Proceeding of the Third International Conference on Circuits and Systems for Communications - ICCSC'06, Politehnica University, Bucharest, Romania: July 6-7, 2006, pp. 149-154], as well as an op amp with current negative feedback [28,29]. In addition, this control unit is produced by many companies in the form of serial chips.

A significant drawback of the known buffer amplifier is that the static mode of the transistors of its circuit is determined by two independent sources of the reference current (I1, I2, Fig. 1). This adversely affects the operation of the control unit at low temperatures, and also makes it difficult to control the load capacity of the control unit when changing the load resistance over a wide range. In practical control circuits (Fig. 1), high-quality reference current sources I1, I2, which significantly affect the control parameters, are implemented according to rather complex transistor circuits, which negatively affects the overall power consumption. Thus, the scheme of the control unit prototype has limited use.

The main objective of the proposed invention is to create a radiation-resistant and low-temperature circuitry of the control unit on complementary field-effect transistors, which provides (with high linearity of the amplitude characteristic) increased stability of the transistors static mode and low noise level, including when operating in the low temperature range.

The problem is achieved in that in the buffer amplifier of FIG. 1, containing potential input 1 and potential output 2 of the device, the first 3 current output of the device, matched with the first 4 bus power supply, the second 5 current output of the device, matched with the second 6 bus power source, the first 7 input field-effect transistor, the gate of which is connected to potential input 1 of the device, the second 8 input field-effect transistor, the gate of which is connected to the potential input 1 of the device, the first 9 output field-effect transistor, the source of which is connected to the potential output 2 of the device, and the drain is connected nen with the first 3 current output of the device, the second 10 output field-effect transistor, the source of which is connected to the potential output 2 of the device, and the drain is connected to the second 5 current output of the device, new elements and connections are provided - field effect transistors with a control are used as field-effect transistors of the control circuit pn junction, between the sources of the first 7 and second 8 input field-effect transistors, a current-stabilizing two-terminal 11 is connected, the drain of the first 7 input field-effect transistor is connected to the first 4 bus of the power supply, the drain of the second of the 8th input field-effect transistor is connected to the second 6th bus of the power source, the gate of the first 9th output field-effect transistor is connected to the source of the second 8th input field-effect transistor, and the gate of the second 10th output field-effect transistor is connected to the source of the first 7th field-effect transistor.

In the circuit of FIG. 2, load 12 can be connected to potential output 2. Capacitors 13 and 14 model stray capacitances in the gate circuit of the first 9 and second 10 output transistors.

In accordance with paragraph 2 of the claims, the first 3 current output of the device is connected to the first 4 bus of the power source, and the second 5 current output of the devices is connected to the second 6 bus of the power source.

In accordance with paragraph 3 of the claims, a correction capacitor 15 is included in parallel with the current-stabilizing two-terminal 11, which reduces the influence of stray capacitors 13 and 14 on the performance of the control unit in the large signal mode.

In the drawing of FIG. 1 shows a diagram of a control unit prototype, and in the drawing of FIG. 2 is a diagram of the inventive buffer amplifier in accordance with claim 1, claim 2, claim 3 of the claims.

In the drawing of FIG. 3 shows the static mode of the control unit of FIG. 2 in the LTSpice simulation environment on complementary field-effect transistors CJFET_2 of Integral OJSC (Minsk) at a temperature of -197ᵒС and a resistance of a current-stabilizing two-terminal 11 equal to 20 kOhm (R11 = R ₀ = R _var1 = 20 kOhm), as well as with a load resistance of 12 equal to infinity (R12 = R _n = R _var2 = ∞).

In the drawing of FIG. Figure 4 shows the dependences of the output voltage of the control unit (Fig. 3) on the input V3 in the temperature range t = -197 ÷ 27ᵒC with resistance of the current-stabilizing two-terminal 11 R11 = R ₀ = R _var1 = 5 kOhm and load 12 R12 = R _n = R _var2 = ∞. From these graphs it follows that the amplitude characteristic of the claimed control unit varies slightly.

In the drawing of FIG. Figure 5 shows a graph of the dependence of the zero bias voltage of the control unit (Fig. 3) on the temperature in the range of -197 ÷ 27ᵒС with the resistance of the resistors R11 = R ₀ = R _var1 = 220 kOhm and R12 = R _n = R _var2 = ∞. Thus, the error in the transmission of input signals with a frequency f _n = 0 in the declared control unit does not exceed 175 mV, which is sufficient for many applications.

In the drawing of FIG. 6 is a diagram of the inclusion of the inventive buffer amplifier (FIG. 2) in the so-called bridge differential cascade (MDC), which is assembled from two identical control units of FIG. 2. It should be noted that the MDK is the basic functional unit of modern analog circuitry.

In the drawing of FIG. 7 shows the static mode of the control unit of FIG. 6 in the LTSpice simulation environment on complementary field-effect transistors CJFET_2 at a temperature of 27 ° C and a load resistance of 12 R12 = R _n = 100 Ohms.

In the drawing of FIG. 8 shows graphs of the dependence of the output currents of the control unit of FIG. 7 for the first 3 (i _{output 1} ) and third 18 (i _{output 3} ) current outputs of the device from the input differential voltage for a different number of parallel-connected semiconductor devices in the structure of the first 9, second 10, third 23 and fourth 24 output transistors (N = 1-3).

In the drawing of FIG. 9 shows the dependence of the output currents of the control unit of FIG. 7 for the second 5 (i _{output 2} ) and fourth 19 (i _{output 4} ) current outputs from the input differential voltage for a different number of parallel-connected semiconductor devices in the structure of the first 9, second 10, third 23, and fourth 24 output transistors (N = 1-3).

A buffer amplifier on complementary field effect transistors with a control pn junction for operation at low temperatures, containing the potential input 1 and potential output 2 of the device, the first 3 current output of the device, matched with the first 4 bus of the power source, the second 5 current output of the device, matched with the second 6 bus power source, the first 7 input field-effect transistor, the gate of which is connected to the potential input 1 of the device, the second 8 input field-effect transistor, the gate of which is connected to the potential input 1 devices, the first 9 output field-effect transistor, the source of which is connected to the potential output 2 of the device, and the drain is connected to the first 3 current output of the device, the second 10 output field-effect transistor, the source of which is connected to the potential output 2 of the device, and the drain is connected to the second 5 current output devices. Field-effect transistors with a control pn junction are used as field-effect transistors of the control unit; between the sources of the first 7 and second 8 input field-effect transistors, a current-stabilizing two-terminal 11 is connected, the drain of the first 7 input field-effect transistor is connected to the first 4 bus of the power source, the drain of the second 8 input field-effect transistor with a second 6 power supply bus, the gate of the first 9 output field-effect transistor is connected to the source of the second 8 input field-effect transistor, and the gate of the second 10 output field-effect transistor connected to the source of the first 7 input field-effect transistor.

In the particular case of the drawing of FIG. 2, in accordance with paragraph 2 of the claims, the first 3 current output of the device is connected to the first 4 bus of the power source, and the second 5 current output of the devices is connected to the second 6 bus of the power source.

In the drawing of FIG. 2, in accordance with paragraph 3 of the claims, a correction capacitor 15 is included in parallel with the current-stabilizing two-terminal 11, which reduces the influence of stray capacitors 13 and 14 on the performance of the control unit in the large signal mode.

Consider the operation of the proposed control unit of FIG. 2.

A feature and uniqueness of the circuit of the claimed control unit is that the static mode of its current transistors is determined by one current-stabilizing two-terminal 11, which is recommended to use a resistor. The static current through the current-stabilizing two-terminal 11 (resistor) is determined by the equations based on the second Kirchhoff law:

, (1)

, (one)

, (2)

, (2)

– напряжение затвор-исток первого 7 и второго 8 входных полевых транзисторов при токе истока, равном I₀₁. Where

- gate-source voltage of the first 7 and second 8 input field-effect transistors at a source current equal to I ₀₁ .

Similarly, the static current of the first 9 and second 10 output field-effect transistors is determined by the equations

, (3)

, (3)

. (4)

. (four)

If the first 7 input and second 9 output field effect transistors, as well as the second 8 input and second 10 output field effect transistors are identical, then from equations (2) and (4) it follows that the source currents of all transistors of the control circuit of FIG. 2 are the same I ₀₁ = I ₀₂ , and are determined by the current through the current-stabilizing two-terminal 11.

Thus, in the claimed control unit there is only one element - the current-stabilizing two-terminal 11 (resistor), which determines the current static mode of the circuit. Other known control circuitry do not have this property.

If at a zero capacitance of the correction capacitor 15 (C ₁₅ = 0) a large positive pulse signal is supplied to the potential input 1 of the control unit (Fig. 2), then the second 8 input field-effect transistor is almost instantly “locked” and the current through the two-terminal 11, which can have a high resistance, begins to slowly charge the parasitic capacitor 14. As a result, the potential at the gate of the first 9 output field-effect transistor and, therefore, the output voltage of the control unit will slowly change linearly. In the absence of a correction capacitor 15, this negatively affects the dynamic error of the control unit in the large signal mode.

Let us further consider the operation of the control unit of FIG. 2 in accordance with paragraph 3 of the claims - for the case when the capacity of the correction capacitor 15 is not equal to zero and exceeds the stray capacitance 14. In this case, a large pulse signal at the potential input 1 of the control unit is transmitted through the first 7 input field-effect transistor to the source circuit locked second 8 input field effect transistor. Thanks to the capacitor 15, the voltage changes at the source of the second 8 input field-effect transistor contribute to faster recharging of the parasitic capacitor 14, which accelerates the transient process and reduces the dynamic error of the claimed control unit when working with pulsed signals of large amplitude.

The bridge amplifier circuit of FIG. 6, in which two of the same type of the claimed buffer amplifiers of FIG. 2, allows you to generate output currents proportional to the input differential voltage in a wide range of its changes (Fig. 8, Fig. 9). This is a prerequisite for the significant performance of operational amplifiers using the bridge amplifier of FIG. 6.

Thus, computer simulation (Fig. 4, Fig. 5, Fig. 8, Fig. 9) shows that the proposed buffer amplifier, the circuitry of which is adapted for use in the low temperature range and exposure to penetrating radiation [28], has significant advantages in Comparison with the well-known options for constructing a control unit during their implementation as part of the CMOS process.

BIBLIOGRAPHIC LIST

1. Patent US 6,215,357, fig. 3, 2001

2. Patent US 5.351.012, 1994

3. Patent US 5.973.534, 1999

4. Patent US 5.197.124, fig. 25, 1993

5. Patent US 7.764.123, fig. 3, 2010

6. US patent No. 6.268.769 fig.3, 2001

7. US patent No. 6.420.933, 2002

8. US patent No. 5.223.122, 1993

9. Patent application US No. 2004/0196101, 2004

10. Patent application US No. 2005/0264358 fig. 1, 2005

11. Patent application US No. 2002/0175759, 2002

12. US Patent No. 5.049.653 fig. 8, 1991.

13. US patent No. 4.837.523, 1989

14. US patent No. 5.179.355, 1993

15. Japan patent JP 10.163.763, 1991

16. Japan Patent JP 10.270.954, 1992.

17. US patent No. 5.170.134 fig.6, 1992

18. US Patent No. 4,540.950, 1985

19. US patent No. 4.424.493, 1984

20. Japan Patent JP 6310950, 2018.

21. US patent No. 5.378.938, 1995.

22. US patent No. 4.827.223, 1989

23. US patent No. 6.160.451, 2000

24. US patent No. 4.639.685, 1987

25. A. St. USSR 1506512, 1986

26. US patent No. 5.399.991, 1995

27. US patent No. 6.542.032, 2003.

28. M. Djebbi, A. Assi and M. Sawan. An offset-compensated wide-bandwidth CMOS current-feedback operational amplifier // CCECE 2003 - Canadian Conference on Electrical and Computer Engineering. Toward a Caring and Humane Technology (Cat. No.03CH37436), 2003, pp. 73-76 vol. 1. DOI: 10.1109 / CCECE.2003.1226347

29. N.N. Prokopenko, A.S. Budyakov, J.M. Savchenko, S.V. Korneev. Maximum rating of Voltage Feedback and Current Feedback Operational Amplifiers in Linear and Nonlinear Modes // Proceeding of the Third International Conference on Circuits and Systems for Communications - ICCSC'06, Politehnica University, Bucharest, Romania: July 6-7, 2006, pp. 149-154.

30. The element base of radiation-resistant information-measuring systems: monograph / N.N. Prokopenko, O.V. Dvornikov, S.G. Krutchinsky; under the general. ed. Doctor of Technical Sciences prof. N.N. Prokopenko; FSBEI HPE “South-Ros. state University of Economics and Service. ” - Mines: FSBEI HPE "URGUES", 2011. - 208 p.

31. O. V. Dvornikov, V. L. Dziatlau, N. N. Prokopenko, K. O. Petrosiants, N. V. Kozhukhov and V. A. Tchekhovski. The accounting of the simultaneous exposure of the low temperatures and the penetrating radiation at the circuit simulation of the BiJFET analog interfaces of the sensors // 2017 International Siberian Conference on Control and Communications (SIBCON), Astana, Kazakhstan, 2017, pp. 1-6. DOI: 10.1109 / SIBCON.2017.7998507.

Claims (3)

1. Buffer amplifier (BU) on complementary field-effect transistors with a control pn junction for operation at low temperatures, containing the potential input (1) and potential output (2) of the device, the first (3) current output of the device, matched with the first (4) bus power source, the second (5) current output of the device, consistent with the second (6) bus of the power source, the first (7) input field-effect transistor, the gate of which is connected to the potential input (1) of the device, the second (8) input field-effect transistor, the gate of which connected to potent the input input (1) of the device, the first (9) output field-effect transistor, the source of which is connected to the potential output (2) of the device, and the drain is connected to the first (3) current output of the device, the second (10) output field-effect transistor, the source of which is connected to potential output (2) of the device, and the drain is connected to the second (5) current output of the device, characterized in that field transistors with a control pn junction are used as field transistors of the control circuit between the sources of the first (7) and second (8) input field transistor turned on toko tabulating two-terminal device (11), the drain of the first (7) input field-effect transistor is connected to the first (4) power supply bus, the drain of the second (8) input field-effect transistor is connected to the second (6) power supply bus, the gate of the first (9) output field-effect transistor connected to the source of the second (8) input field-effect transistor, and the gate of the second (10) output field-effect transistor is connected to the source of the first (7) input field-effect transistor. 2. A buffer amplifier on complementary field-effect transistors with a control pn junction for operation at low temperatures according to claim 1, characterized in that the first (3) current output of the device is connected to the first (4) bus of the power source, and the second (5) current output the device is connected to a second (6) power supply bus. 3. A buffer amplifier based on complementary field-effect transistors with a p-n junction control for operation at low temperatures according to claim 1, characterized in that a correction capacitor (15) is connected in parallel with the current-stabilizing two-terminal network (11).

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