RU2688225C1 - Differential amplifier on complementary field-effect transistors with control p-n junction - Google Patents

Abstract

FIELD: radio engineering and communications.SUBSTANCE: invention relates to the field of radio engineering and communications and can be used as a device to amplify analog signals. Differential amplifier comprises field-effect transistor, gate of which is connected to first input of device, and drain is connected to first current output, matched with first bus of the power supply source, a second input field-effect transistor, gate of which is connected to the second input of the device, and drain is connected to the second current output of the device, matched with the first bus of the power supply source. Sources of the first and second input field-effect transistors are connected to each other through series-connected first and second additional resistors, sources of the third and fourth input field-effect transistors are connected to each other through series-connected third and fourth additional resistors.EFFECT: high stability of static mode of input field-effect transistors at negative temperatures, possibility of varying limiting voltage of DA driving characteristic.3 cl, 9 dwg

Description

The invention relates to the field of radio engineering and communications and can be used as a device for amplifying analog signals, in the structure of analog microcircuits of various functional purposes, for example, operational amplifiers (OA), voltage stabilizers, comparators, bridge power amplifiers, etc., t . h. operating at low temperatures and exposure to radiation [1].

The known schemes of classical differential amplifiers (DU) on complementary field-effect transistors [2-9], incl. on complementary CMOS field effect transistors [2–4] and complementary field effect transistors with a control p – n junction (JFet) [5], which became the basis of many serial analog microcircuits. In the literature on analog microelectronics, this class of remote control has a special designation - dual-input-stage [10].

The use of JFet field effect transistors [11–13] is promising for operation at low temperatures with severe restrictions on the level of noise. DCs of this class are actively used in the structure of low-noise analog interfaces for processing sensor signals [14-16].

The task of improving the quality indicators of classical remote control systems to attenuate input common-mode signals and to ensure the efficiency of remote control in paraphase-output circuits is solved today by introducing various common-mode feedbacks using the input-phase input signal in practical OU circuits [17]. For this purpose, in analog microelectronics there is a special subclass of circuits for isolating the input common-mode signal of the remote control, which are implemented as special differential amplifiers [6-7]. In the DU-prototype, such a task is not solved - in the circuit there is no output node, at which the input common-mode signal U _sf.in is allocated with rather high accuracy, i.e. the signal at the first 1 and second 2 inputs of the remote control of FIG. 1 U _sf.vh = (u _c1 + u _c2 ) / 2.

The closest prototype (Fig. 1) of the claimed device is a differential amplifier described in US Pat. No. 5,291,149, fig.4, 1994, which contains the first 1 and second 2 inputs that form the differential input of the device, the first 3 input field-effect transistor, the gate of which connected to the first 1 input of the device, and the drain is connected to the first 4 current output, coordinated with the first 5 bus power supply, the second 6 input field-effect transistor, the gate of which is connected to the second 2 input of the device, and the drain is connected to the second 7 current output of the device It is compatible with the first 5 bus power supply, and the sources of the first 3 and second 6 input field-effect transistors are connected to each other, the third 8 input field-effect transistor, the gate of which is connected to the first 1 input of the device, and the drain is connected to the third 9 current output, matched with the second 10 bus power supply, the fourth 11 input field-effect transistor, the gate of which is connected to the second 2 input of the device, and the drain is connected to the fourth 12 current output of the device matched with the second 10 bus of the power supply, The sources of the third 8 and fourth 11 input field-effect transistors are connected to each other.

The first significant disadvantage of the known control of FIG. 1 is that the static mode of its input transistors (3, 6, 8, 11) is determined by two sources of the reference current I ₁ (I ₂ ), which, as a rule, are not identical. This causes additional errors in the amplification of small signals. Secondly, in a known remote control with a fixed current consumption, it is difficult to change the limiting voltage (U _g ) of the pass characteristic i _out = f (u _in ), which has a significant effect on the maximum slew rate of the output voltage (SR) of the operational amplifier with the input control in FIG. 1 [17, 18]

, (1)

, (one)

where f ₁ is the unit amplification frequency of the corrected OU with the input control unit of FIG. 1, as a rule, weakly dependent on U _gr .

It is not possible to control the SR numerical values in specific OS schemes given the current consumption limits, phase stability margin, voltage gain, etc.

Third, in the prototype FIG of FIG. 1, there is no output node, at which the input common-mode signal is allocated with a sufficiently high accuracy for subsequent use in an opamp circuit to improve its precision.

The main objective of the proposed invention is to create conditions under which in the control of FIG. 1 provided by:

- higher stability of the static mode of the input field-effect transistors at negative temperatures (up to -197 ° C) and a change in the supply voltage (in comparison with the remote control of Fig. 1 based on the classical reference current sources I ₁ , I ₂ );

- the possibility of changing the voltage limits (U _gr ) pass characteristics i _out = f (u _in ) at the discretion of the developer (depending on the set values SR OU) at a fixed static current consumption;

- measurement of the level of the input common-mode signal DU U _sf.vh = (u _c1 + u _c2 ) / 2, which is formed at the additional output of the claimed device 17.

The problem is solved in that in the differential amplifier of FIG. 1, containing the first 1 and second 2 inputs forming the differential input of the device, the first 3 input field-effect transistor, the gate of which is connected to the first 1 input of the device, and the drain is connected to the first 4 current output matched to the first 5 power supply bus, the second 6 an input field-effect transistor, the gate of which is connected to the second 2 input of the device, and the drain is connected to the second 7 current output of the device, matched with the first 5 power supply bus, and the sources of the first 3 and second 6 input field-effect transistors are connected the third with the third, 8 input field-effect transistor, the gate of which is connected to the first 1 input of the device, and the drain is connected to the third 9 current output, matched with the second 10 bus power supply, the fourth 11 input field-effect transistor, the gate of which is connected to the second 2 input devices, and the drain is connected to the fourth 12 current output of the device, matched with the second 10 bus power supply, and the sources of the third 8 and fourth 11 input field-effect transistors are connected to each other, new elements and connections are provided - the source The first 3 and second 6 inputs of the input field-effect transistors are connected to each other through series-connected first 13 and second 14 additional resistors, the sources of the third 8 and fourth 11 input field-effect transistors are connected to each other through series-connected third 15 and fourth 16 additional resistors, the common the node of the first 13 and second 14 additional resistors is connected with the additional output of the device 17 for measuring the level of the input common-mode signal at the first 1 and second 2 inputs of the device, and the common node is the third 15 and 16 additional fourth resistors connected to an additional output of the device 17 for measuring the phase of the input signal level at the first 1 and second 2 of the device inputs.

In FIG. 1 is a diagram of a prototype remote control, and in FIG. 2 is a diagram of the claimed device in accordance with claim 1.

In FIG. 3 is a diagram of the inventive device in accordance with clause 2, and in FIG. 4 - in accordance with paragraph 3 of the claims.

In FIG. 5 shows a differential amplifier on complementary field-effect transistors with all variants of the input-mode common mode allocation circuit, corresponding to claim 1 - claim 3 of the claims.

In FIG. 6 shows the static control mode of FIG. 5 in the LTspice environment on the models of complementary field-effect transistors of JSC Integral (Minsk) at temperatures of 27 ° C (a) and -197 ° C (b). In this case, the node "A" corresponds to the additional output of the device 17 for measuring the level of the input common-mode signal at the first 1 and second 2 inputs of the claimed device.

In FIG. 7 shows the dependence of the output common-mode voltage of the control unit of FIG. 6 (voltage in node "A") from the input common-mode voltage V _in = V3 at different temperatures. This graph shows that the dependence u _sf = f (U _sf.vkh ) is linear.

In FIG. 8 shows the dependence of the voltage in the node "A" of the DN of FIG. 6 from temperature in the range -197 ÷ + 27 ° С at zero input common-mode voltage Vin = V3 = 0V.

In FIG. 9 shows the flow characteristics of the control of FIG. 6 with different resistances of resistor R5 ^* .

A differential amplifier on complementary field-effect transistors with a control p-n junction of FIG. 2 contains the first 1 and second 2 inputs forming the differential input of the device, the first 3 input field-effect transistor, the gate of which is connected to the first 1 input of the device, and the drain is connected to the first 4 current output matched to the first 5 power supply bus, the second 6 input a field-effect transistor, the gate of which is connected to the second 2 input of the device, and the drain is connected to the second 7 current output of the device matched with the first 5 power supply bus, with the sources of the first 3 and second 6 input field-effect transistors connected to each other on the other hand, the third 8 input field-effect transistor, the gate of which is connected to the first 1 input of the device, and the drain is connected to the third 9 current output, matched with the second 10 bus power supply, the fourth 11 input field-effect transistor, the gate of which is connected to the second 2 input of the device and the drain is connected with the fourth 12 current output of the device, matched with the second 10 bus of the power supply, and the sources of the third 8 and fourth 11 input field-effect transistors are connected to each other. The sources of the first 3 and second 6 input field-effect transistors are connected to each other through series-connected first 13 and second 14 additional resistors, sources of the third 8 and fourth 11 input field-effect transistors are connected to each other through series-connected third 15 and fourth 16 additional resistors, the common the node of the first 13 and second 14 additional resistors is connected with the additional output of the device 17 for measuring the level of the input common-mode signal at the first 1 and second 2 inputs of the device, and the common node is 15 rd and fourth additional resistors 16 associated with the additional output device 17 for measuring the phase of the input signal level at the first 1 and second 2 of the device inputs.

In FIG. 3, in accordance with clause 2 of the claims, the common node of the first 13 and second 14 additional resistors connected in series is connected with an additional output of the device 17 for measuring the level of the input common-mode signal at the first 1 and second 2 inputs of the device through the fifth 22 additional resistor.

In FIG. 4, in accordance with clause 3 of the claims, the common node of the third 15 and fourth 16 additional resistors connected in series is connected with an additional output of the device 17 for measuring the level of the input common-mode signal at the first 1 and second 2 inputs of the device through the sixth 23 additional resistor.

Consider the operation of the control of FIG. 2

In static mode, when connecting the first 1 and second 2 inputs of the remote control of FIG. 2 to the common power supply bus (5 and 10) for the remote control circuit of FIG. 2 the following equations are true:

, (2)

, (2)

, (3)

, (3)

, (4)

, (four)

, (5)

, (five)

, (6)

, (6)

where I _сi is the drain current of the i-th input field-effect transistor (3, 6, 8, 11);

U _{zi. I} - gate-source voltage of the corresponding input field-effect transistors 3, 6, 8, 11 at the operating point at a source current equal to the specified value I ₀ ;

u _SF - output voltage at the additional output of the device 17 for measuring the level of the input common-mode signal at the first 1 and second 2 inputs of the proposed device.

If U _zi.3 = U _zi.6 = U _zi.8 = U _z.11 , then the output common mode voltage at the auxiliary output of the device 17 is equal to the input common mode voltage of the remote control of FIG. 2: u _SF ≈ (u _c1 + u _c2 ) / 2.

Thus, by choosing the resistances of the first 13, second 14, third 15, and fourth 16 additional resistors in the control unit of FIG. 2 provides the identical specified static current mode of all field-effect transistors 3, 6, 8, 11. The voltage at the additional output of the device 17 for measuring the level of the input common-mode signal at the first 1 and second 2 inputs of the device is close to zero (Fig. 7, Fig . eight).

In cases where the drain-gate characteristics of the first 3 and second 6 input field-effect transistors differ from the gate-gate characteristics of the third 8 and fourth 11 input field-effect transistors to obtain a zero level of output voltage _uf at the additional output of the device 17, the circuits of FIG. 3 or FIG. 4. In these schemes, the introduction of the fifth 22 additional resistor (Fig. 3) or the sixth 23 additional resistor (Fig. 4) allows to obtain a zero value of the output voltage u _sf at the additional output of the device 17 at zero input common-mode signal (u _c1 + u _c2 ) / 2 = 0.

It should be noted that the static mode of the remote control current of FIG. 2 is almost independent of the magnitude of the input common-mode signal (u _c1 + u _c2 ) / 2 and variations in the supply voltages on the first 5 and second 10 buses. This allows you to exclude from the scheme of the remote control of FIG. 2 traditional reference current sources (I ₁ , I ₂ , Fig. 1) with their simplest construction, negatively affecting the attenuation coefficient of the input common-mode remote control signal and the interference suppression factor for the first 5 and second 10 power buses.

If the input terminal 1 is supplied a positive input voltage with respect to input u _Rin 2, this causes an increase in the first current source 11 3 and fourth input FETs. In the limit, the source current of the first 3 input field-effect transistor can take twice the value relative to its static level when u _in = 0. The numerical values of the resistances of the first 13, second 14, third 15, and fourth 16 additional resistors determine the voltage limiting the pass-through characteristic of the remote control in FIG. 2: the greater the resistance of the additional resistors R13, R14, R15, R16, the higher the input voltage u _in = U _g will be the limitation of the output current of the remote control for the first 4 current output. This is evidenced by the graphs of FIG. 9, obtained for the circuit of FIG. 2

Thus, the first 13, second 14, third 15 and fourth 16 additional resistors determine the numerical values of the limiting voltage U _{gr of the} proposed differential amplifier for all its current outputs 4, 7, 9, 12.

The results of computer simulation in the LTspice DC environment of FIG. 3 and FIG. 8 show that, on the basis of the proposed DC, a wide range of pass-through characteristics is implemented with different numerical values of the limiting voltage _Ug for the first 4 and second 7 current outputs matched with the first 6 power supply bus, as well as the third 9 and fourth 12 current outputs coordinated with second 10 bus power supply. As a result, this allows to design differential and multidifferential operational amplifiers with remote control with given speed (see formula (1)).

The plots of FIG. 8 characterize the weak temperature dependence of the output voltage DN of FIG. 6 at the additional output of the device 17 for measuring the level of the input common-mode signal at the first 1 and second 2 inputs of the device.

Thus, the claimed device has significant advantages in comparison with the known dual-input-stage remote control circuit design solutions [2-28], which allows recommending it for practical use in the OS and building low-temperature and radiation-resistant analog chips using BiJFet and CJFet technical processes JSC Integral (Minsk), as well as the complementary field technological process of NPP Pulsar JSC (Moscow).

Bibliographic list

1. OV Dvornikov, VL Dziatlau, NN Prokopenko, KO Petrosiants, NV Kozhukhov and VA Tchekhovski, “BiJFET,” International Siberian Conference on Control and Communications (SIBCON), Astana, 2017, pp. 1-6. DOI: 10.1109 / SIBCON.2017.7998507

2. US patent 4,377,789, fig. 1, 1983

3. Patent application US 2006/0125522, 2006

4. Patent US 7.907.011, 2011

5. US patent 5,291,149 fig. 4, 1991

6. Patent US 6.750.515, 2004

7. Patent US 4,573.020, 1986

8. Ashley Ingmire. Differential amplification and common mode feedback. https://slideplayer.com/slide/1496714/

9. Patent US 6.556.081, fig. 1, 2003

10. NN Prokopenko, NV Butyrlagin, AV Bugakova and AA Ignashin, "Method for speeding the micropower CMOS operational amplifiers with dual-input-stages," 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Batumi, 2017, pp. 78-81.

11. KO Petrosyants, MR Ismail-zade, LM Sambursky, OV Dvornikov, BG Lvov and IA Kharitonov, "Automation of the JFET model in the −200 ... + 110 ° C temperature range," 2018 Moscow Workshop on Electronic and Networking Technologies (MWENT), Moscow, 2018, pp. 1-5. DOI: 10.1109 / MWENT.2018.8337212

12. Creation of low-temperature analog ICs for processing pulse signals from sensors. Part 2 / O. Dvornikov, V. Chekhovsky, V. Dyatlov, N. Prokopenko // Modern Electronics, 2015, No. 5. P. 24-28

13. OV Dvornikov, NN Prokopenko, NV Butyrlagin and IV Pakhomov, AGAMC, 2016, International Syndicate, Moscow, 2016 , pp. 1-6. DOI: 10.1109 / SIBCON.2016.7491792

14. Dvornikov O.V., Chekhovsky V.A., Dyatlov V.L., Prokopenko N.N. "Low-noise electronic module for processing avalanche photodiode signals" Instruments and methods of measurement, no. 2 (7), 2013, pp. 42-46.

15. Dvornikov O. Chekhovsky V., Dyatlov V., Prokopenko N. The Use of Structural Crystals for Creating Sensor Interfaces // Modern Electronics. - 2014. - №. 1. - p. 32-37.

16. OV Dvornikov, AV Bugakova, NN Prokopenko, VL Dziatlau and IV Pakhomov, "The microcircuits MH2XA010-02 / 03 for the signal processing of optoelectronic sensors," 2017 18th International Conference of Young Specialists on Micro / Nanotechnologies and Electron Devices (EDM) , Erlagol, 2017, pp. 396-402. DOI: 10.1109 / EDM.2017.7981781

17. Operational amplifiers with direct connection of cascades: monograph / Anisimov V.I., Kapitonov M.V., Prokopenko N.N., Sokolov Yu.M. - L .: "Energy", 1979. - 148 p.

18. N.N. Prokopenko Nonlinear active correction in precision analog microcircuits (monograph) // Rostov-on-Don: Publishing House of the North-Caucasus Research Center for Higher Education, 2000. 222с.

Claims (3)

1. Differential amplifier on complementary field-effect transistors with a control pn junction, containing the first (1) and second (2) inputs forming the differential input of the device, the first (3) input field-effect transistor, the gate of which is connected to the first (1) input of the device, and the drain is connected to the first (4) current output matched to the first (5) power supply bus, the second (6) input field-effect transistor, the gate of which is connected to the second (2) input of the device, and the drain is connected to the second (7) current output of the device agreed with the first (5) bus power supply, the sources of the first (3) and second (6) input field-effect transistors are connected to each other, the third (8) input field-effect transistor, the gate of which is connected to the first (1) device input, and the drain is connected to the third (9) current output, matched with the second (10) power supply bus, the fourth (11) input field-effect transistor, the gate of which is connected to the second (2) input of the device, and the drain is connected to the fourth (12) current output of the device, coordinated with the second (10) bus power supply, and the sources of the third (8) and the fourth (11) input field-effect transistors are connected to each other, characterized in that the sources of the first (3) and second (6) input field-effect transistors are connected to each other through series-connected first (13) and second (14) additional resistors, sources the third (8) and fourth (11) input field-effect transistors are connected to each other through series-connected third (15) and fourth (16) additional resistors, the common node of the first (13) and second (14) additional resistors being connected to the additional output of the device (17) for measure the input common-mode signal at the first (1) and second (2) inputs of the device, and the common node of the third (15) and fourth (16) additional resistors is connected with an additional output of the device (17) for measuring the level of the input common-mode signal at the first (1 ) and the second (2) inputs of the device. 2. Differential amplifier according to claim 1, characterized in that the common node of the series-connected first (13) and second (14) additional resistors is connected to an additional output of the device (17) for measuring the level of the input common mode signal on the first (1) and second ( 2) device inputs through the fifth (22) additional resistor. 3. Differential amplifier according to claim 1, characterized in that the common node of the third (15) and fourth (16) additional resistors connected in series is connected with an additional output of the device (17) for measuring the input common-mode signal at the first (1) and second ( 2) the inputs of the device through the sixth (23) additional resistor.

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