CN111551878B - Hall sensor temperature drift compensation circuit - Google Patents

Hall sensor temperature drift compensation circuit Download PDF

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CN111551878B
CN111551878B CN202010446483.3A CN202010446483A CN111551878B CN 111551878 B CN111551878 B CN 111551878B CN 202010446483 A CN202010446483 A CN 202010446483A CN 111551878 B CN111551878 B CN 111551878B
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calibration
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CN111551878A (en
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蒋磊
徐跃
宋福明
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Nanjing University of Posts and Telecommunications
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Nanjing University of Posts and Telecommunications
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R33/00—Arrangements or instruments for measuring magnetic variables
    • G01R33/007—Environmental aspects, e.g. temperature variations, radiation, stray fields
    • G01R33/0082—Compensation, e.g. compensating for temperature changes
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R33/00—Arrangements or instruments for measuring magnetic variables
    • G01R33/0023—Electronic aspects, e.g. circuits for stimulation, evaluation, control; Treating the measured signals; calibration
    • G01R33/0029—Treating the measured signals, e.g. removing offset or noise
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R33/00—Arrangements or instruments for measuring magnetic variables
    • G01R33/02—Measuring direction or magnitude of magnetic fields or magnetic flux
    • G01R33/06—Measuring direction or magnitude of magnetic fields or magnetic flux using galvano-magnetic devices
    • G01R33/07—Hall effect devices

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Abstract

The invention discloses a temperature drift compensation circuit of a Hall sensor, which is used for compensating the temperature drift of the Hall sensor in real time when the temperature of the working environment of the Hall sensor changes, and increasing or decreasing the Hall voltage by increasing or decreasing the bias current of a Hall device, thereby realizing the compensation of the temperature drift of the Hall sensor. Simulation results show that the temperature drift coefficient of the compensated Hall sensor is 45 ppm/DEG C within the temperature range of-40-120 ℃.

Description

Hall sensor temperature drift compensation circuit
Technical Field
The invention provides a Hall sensor temperature drift compensation circuit, and belongs to the technical field of magnetic sensors.
Background
A hall sensor is a sensor made using the hall effect, which converts a magnetic field signal into a corresponding electrical signal. As a third sensor product demanded worldwide, hall sensors are widely used in the fields of industrial control systems, automobiles, intelligent instruments and meters, and the like. Due to the important role and huge market demand of hall sensors in the sensor field, developed countries such as the united states, the english, the japanese and the law are in vigorous development of hall sensor technology and compete for the high point of the hall sensor technology.
The Hall device in the Hall sensor is made of semiconductor materials, and when the temperature of the external environment changes, the mobility and the impurity concentration of the Hall device change, so that the sensitivity of the Hall device changes, the linearity of the Hall sensor is seriously influenced, and the application of the Hall sensor in high-precision measurement occasions is limited. In addition, the aging of the device and the stress generated during the packaging process also affect the sensitivity of the hall sensor. The test result shows that the sensitivity of the Hall device is nonlinear along with the change of temperature, and the traditional first-order temperature drift compensation can not meet the high-precision requirement of the Hall sensor. In order to improve the measurement accuracy of the hall sensor, a second-order temperature drift compensation circuit is required to perform temperature drift compensation on the hall sensor.
Chinese patent CN201910456718 discloses a hall current sensor circuit with a dual hall element structure, but it only uses an analog circuit to perform simple first-order temperature drift compensation on the hall sensor, and is different from the circuit proposed by the present invention. The invention adopts a method of combining an analog circuit and a digital circuit to carry out second-order temperature drift compensation on the Hall sensor, has high circuit integration level, good compensation effect and large compensation range, and not only can compensate the sensitivity drift caused by temperature change, but also can compensate the sensitivity drift caused by packaging stress and device aging.
Disclosure of Invention
The purpose of the invention is as follows: in order to overcome the defects in the prior art, the invention provides a Hall sensor temperature drift compensation circuit, which is used for carrying out second-order temperature compensation on the temperature drift of a Hall sensor, greatly reducing the temperature drift and improving the measurement precision of the Hall sensor.
The technical scheme is as follows: in order to achieve the purpose, the invention adopts the technical scheme that:
a temperature drift compensation circuit of a Hall sensor is used for compensating the temperature drift of the Hall sensor and comprises two calibrated Hall devices, two integrated coils, a first offset voltage elimination circuit, a second offset voltage elimination circuit, a subtracter, a comparator, a digital calibration circuit, a digital-to-analog converter and a voltage-to-current conversion circuit. The two calibration Hall devices are marked as a first calibration Hall device and a second calibration Hall device, the two integrated coils are respectively marked as a first integrated coil and a second integrated coil, the first integrated coil is integrated above the first calibration Hall device, the second integrated coil is integrated above the second calibration Hall device, and a port B of the first calibration Hall device is connected with a bias current source IbiasThe port D is grounded, and the port A and the port C are connected with the input port of the offset voltage elimination circuit I. A port B of the second calibration Hall device is connected with a bias current source IbiasThe port D is grounded, and the port A and the port C are connected with the input port of the offset voltage eliminating circuit II. The subtracter comprises a resistor R1Resistance two R2Resistance three R3Resistance three R4And an amplifier one, wherein a resistor one R1The input port is connected with the output port of the offset voltage eliminating circuit I and the resistor R1The output port is connected with the inverting input port of the first amplifier and the second resistor R2Input port phase ofA resistor two R2The output port of the first amplifier is connected with the output port of the first amplifier. Resistance three R3The input port of the voltage-offset eliminating circuit is connected with the output port of the offset voltage eliminating circuit II and the resistor III R3The output port is connected with the positive phase input port of the first amplifier and the resistor IV4One port of the resistor is connected with the resistor four R4The other port of the subtractor is connected to the ground, and the output port of the subtractor is connected to the inverting input port of the comparator. The subtracter subtracts the output signals of the offset voltage elimination circuit I and the offset voltage elimination circuit II, two Hall voltage signals with the same size and the same polarity, which are generated by an external magnetic field, are removed, and double Hall reference voltage signals are output. The positive input port of the comparator is connected with a Hall reference voltage reference value V at 25 DEG Cref. The output port of the comparator is connected with the input port of the digital calibration circuit. The output port of the digital calibration circuit is connected with the input port of the digital-to-analog converter. The output port of the digital-to-analog converter is connected with the input port of the voltage-to-current circuit. Output port I of voltage-to-current circuit and bias current source I of calibration Hall device IbiasThe output port of the voltage-to-current circuit is connected with a port B of the first calibration Hall device, an output port II of the voltage-to-current circuit and a bias current source I of the second calibration Hall devicebiasThe output port of the voltage-to-current circuit is connected with the output port B of the second calibration Hall device, the output port III of the voltage-to-current circuit and the bias current source I of the working Hall devicebiasThe output ports of the Hall devices are connected with the port B of the working Hall device together.
Two identical integrated coils I and II are respectively introduced with two currents with the same magnitude and opposite polarity, the two currents with the same magnitude and opposite polarity generate two reference magnetic fields with the same magnitude and opposite polarity, the two reference magnetic fields with the same magnitude and opposite polarity respectively generate two Hall reference voltages with the same magnitude and opposite polarity in two calibrated Hall devices, and meanwhile the two calibrated Hall devices respectively generate two Hall voltages with the same magnitude and same polarity generated by an external magnetic field.
Preferably: the structures of the first calibration Hall device, the second calibration Hall device and the working Hall device are the same.
Preferably: the integrated coil is made of metal interconnection lines in a CMOS manufacturing process.
Preferably: the comparator is a reverse comparator, the reverse input port of the comparator is connected with the output port of the subtracter, and the normal input port of the comparator is connected with the Hall reference voltage reference value V at 25 DEG CrefWhen the Hall reference voltage value at the temperature is larger than the Hall reference voltage reference value VrefThe comparator outputs "0". When the Hall reference voltage value at the temperature is smaller than the Hall reference voltage reference value VrefThe comparator outputs "1".
Preferably: the digital calibration circuit comprises 12D flip-flops, AND gates and NOR gates, which are respectively marked as the ith D flip-flop, the ith AND gate and the ith NOR gate, wherein i is 1, 2, 3, … and 12, a port CK of the ith D flip-flop is connected with a clock input signal I CLK1, and a port RN of the ith D flip-flop is connected with a clock input signal II CLK 2. The port D of the 1 st D flip-flop is connected with a clock input signal three CLK3, and the port Q of the 1 st D flip-flop is connected with the port D of the 2 nd D flip-flop. The port Q of the jth D flip-flop is connected to the port D of the j +1 th D flip-flop, j being 2, 3, 4, …, 11. One input port of the ith AND gate is connected with a clock input signal four CLK4, and the other input port of the ith AND gate is respectively connected with a port Q of the ith D flip-flop. One input port of the ith NOR gate is connected with the clock input signal five CLK5, and the other input port of the ith NOR gate is respectively connected with the output port of the ith AND gate. The output port of the ith NOR gate is connected with the ith bit of the input port of the digital-to-analog converter. The digital calibration circuit implements the logic functions of: first, the digital calibration circuit outputs zero, that is, the digital value output by the digital calibration circuit is "0". Then the digital output value is converted into voltage through a digital-to-analog converter and further converted into compensation current through a voltage-to-current circuit, the injection of the compensation current enables the Hall reference voltage to be increased, and the Hall reference voltage value and the Hall reference voltage reference value V at the moment are obtainedrefComparing, if the Hall reference voltage value is larger than the Hall reference voltage reference value VrefLarge, then the comparator outputsGo out "0", the first position "0" outputted by the digital calibration circuit, if the Hall reference voltage value at this moment is larger than the Hall reference voltage reference value VrefSmall, the comparator outputs a "1", and the "1" of the first bit of the digital calibration circuit output remains. After the first bit comparison is completed, the digital calibration circuit outputs a second position "1" to the digital calibration circuit, and then repeats the above steps until the last bit comparison is completed. In the compensation process, the Hall reference voltage value output by the Hall device is calibrated to gradually approach the Hall reference voltage reference value VrefThe compensation current is simultaneously injected into the bias port of the working Hall device without an integrated coil, namely a detection magnetic field, so that the product of the sensitivity and the bias current is kept unchanged when the temperature is changed, even if the Hall voltage output by the device is kept unchanged when the temperature is changed.
Preferably: the digital-to-analog converter adopts a 12-bit weighted capacitance digital-to-analog converter, the digital-to-analog converter is divided into a high 7 bit and a low 5 bit by adopting a segmentation method, and the reference voltage value applied to the digital-to-analog converter is 1V.
Preferably: the voltage-to-current circuit comprises a second amplifier, a resistor R and a current mirror, wherein the current mirror comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube and a fifth NMOS (N-channel metal oxide semiconductor) tube, a positive phase input port of the second amplifier is connected with an output port of the digital-to-analog converter, a reverse phase input port is connected with one port of the resistor R and is connected with a source electrode of the fifth NMOS tube, and the other port of the resistor R is grounded. The drain electrode of the fifth NMOS tube is connected with the drain electrode of the first PMOS tube, the first PMOS tube is connected with the source electrodes of the second, third and fourth PMOS tubes, the source electrodes of the first to fourth PMOS tubes are connected with VDD, and the grid electrodes are interconnected. The drain electrode of the fourth PMOS tube is connected with the port B of the first calibration Hall device, the drain electrode of the third PMOS tube is connected with the port B of the second calibration Hall device, and the drain electrode of the second PMOS tube is connected with the port B of the working Hall device. The voltage value output by the digital-to-analog converter is converted into compensation current through a voltage-to-current circuit, and the compensation current is copied into the first calibration Hall device, the second calibration Hall device and the working Hall device through the current mirror 1: 1.
Compared with the prior art, the temperature drift compensation circuit of the Hall sensor has the following advantages:
1. the temperature drift compensation circuit of the Hall sensor provided by the invention adopts an integrated CMOS technology, and utilizes the metal interconnection layer integrated coil in the manufacturing process to generate the reference magnetic field.
2. The temperature drift compensation circuit of the Hall sensor provided by the invention adopts a method of combining an analog circuit and a digital circuit to carry out second-order compensation on the temperature drift of the Hall sensor, the compensation effect is good, and a simulation result shows that the temperature drift coefficient of the Hall sensor after compensation is as low as 45 ppm/DEG C.
3. The temperature drift compensation circuit of the Hall sensor has a large temperature compensation range, the compensation range is-40-120 ℃, and the use requirement of the industrial Hall sensor is met.
4. The Hall sensor temperature drift compensation circuit provided by the invention can compensate the sensitivity drift caused by temperature change and can also compensate the sensitivity drift caused by packaging stress and device aging.
Drawings
FIG. 1 is a circuit diagram of the Hall sensor temperature drift compensation of the present invention;
FIG. 2 is a diagram of an integrated coil of the present invention;
FIG. 3 is a digital calibration circuit diagram of the present invention;
FIG. 4 is a voltage to current circuit diagram of the present invention;
FIG. 5 is a graph of simulation results for the present invention.
Detailed Description
The present invention is further illustrated by the following description in conjunction with the accompanying drawings and the specific embodiments, it is to be understood that these examples are given solely for the purpose of illustration and are not intended as a definition of the limits of the invention, since various equivalent modifications will occur to those skilled in the art upon reading the present invention and fall within the limits of the appended claims.
A temperature drift compensation circuit of a Hall sensor is disclosed, as shown in figure 1, when the temperature of the working environment of the Hall sensor changes, the temperature drift of a magnetic field detection circuit of the Hall sensor is compensated in real time through the temperature drift compensation circuit, and the Hall voltage is increased or reduced by increasing or reducing the bias current of a Hall device, so that the temperature drift compensation of the Hall sensor is realized.
The magnetic field detection circuit comprises a working Hall device, a current rotation circuit, an instrumentation amplifier, a related double sampling/holding unit, a low-pass filter and a buffer, wherein a port B of the working Hall device is connected with a bias current source IbiasThe port D is grounded, and the port A and the port C are connected with the input port of the current rotating circuit. The output port of the current rotation circuit is connected with the input port of the instrumentation amplifier. The output port of the instrumentation amplifier is connected with the input port of the correlated double sampling/holding device. The output port of the correlated double sample/holder is connected with the input port of the low-pass filter. The output port of the low-pass filter is connected with the input port of the buffer. The output port of the buffer outputs the hall voltage. The current rotation circuit modulates the polarity of the Hall signal, the Hall signal is respectively amplified and subtracted through the instrumentation amplifier and the related double sampling/holding device, the Hall signal is recovered through the low-pass filter, and finally the Hall voltage signal subjected to temperature drift compensation is output through the buffer.
The temperature drift compensation circuit comprises two calibration Hall devices, two integrated coils, a first offset voltage elimination circuit, a second offset voltage elimination circuit, a subtracter, a comparator, a digital calibration circuit, a digital-to-analog converter and a voltage-to-current circuit. The two calibration Hall devices are marked as a first calibration Hall device and a second calibration Hall device, the first calibration Hall device and the second calibration Hall device are identical in structure, the integrated coils are respectively integrated above the first calibration Hall device and the second calibration Hall device, the two integrated coils are respectively marked as a first integrated coil and a second integrated coil, the first integrated coil is integrated above the first calibration Hall device, the second integrated coil is integrated above the second calibration Hall device, and a port B of the first calibration Hall device is connected with a bias current source IbiasThe port D is grounded, and the port A and the port C are connected with offset voltageAnd the input port of the first elimination circuit. A port B of the second calibration Hall device is connected with a bias current source IbiasThe port D is grounded, and the port A and the port C are connected with the input port of the offset voltage eliminating circuit II. The subtracter comprises a resistor R1Resistance two R2Resistance three R3Resistance three R4And an amplifier one, wherein a resistor one R1The input port is connected with the output port of the offset voltage eliminating circuit I and the resistor R1The output port is connected with the inverting input port of the first amplifier and the second resistor R2Is connected with the input port of the resistor II R2The output port of the first amplifier is connected with the output port of the first amplifier. Resistance three R3The input port of the voltage-offset eliminating circuit is connected with the output port of the offset voltage eliminating circuit II and the resistor III R3The output port is connected with the positive phase input port of the first amplifier and the resistor IV4One port of the resistor is connected with the resistor four R4The other port of the subtractor is connected to the ground, and the output port of the subtractor is connected to the inverting input port of the comparator. The subtracter subtracts the output signals of the offset voltage elimination circuit I and the offset voltage elimination circuit II, two Hall voltage signals with the same size and the same polarity, which are generated by an external magnetic field, are removed, and double Hall reference voltage signals are output. The subtracter subtracts the output signals of the offset voltage elimination circuit I and the offset voltage elimination circuit II, two Hall voltage signals with the same size and the same polarity, which are generated by an external magnetic field, are removed, and double Hall reference voltage signals are output. The output port of the subtracter is connected with the reverse input port of the comparator, and the positive input port of the comparator is connected with the Hall reference voltage reference value V at 25 DEG Cref. The output port of the comparator is connected with the input port of the digital calibration circuit. The output port of the digital calibration circuit is connected with the input port of the digital-to-analog converter. The output port of the digital-to-analog converter is connected with the input port of the voltage-to-current circuit. Output port I of voltage-to-current circuit and bias current source I of calibration Hall device IbiasThe output port of the voltage-to-current circuit is connected with a port B of the first calibration Hall device, an output port II of the voltage-to-current circuit and a bias current source I of the second calibration Hall devicebiasThe output ports of the Hall device II are connected with the output port of the Hall device IIPort B, output port III of voltage-to-current circuit and bias current source I of working Hall devicebiasThe output ports of the Hall devices are connected with the port B of the working Hall device together.
As shown in fig. 2, the integrated coil is made of metal interconnection lines in a CMOS manufacturing process, two identical integrated coils are integrated above the first calibration hall device and the second calibration hall device, the first integrated coil has 19 turns, wherein the first turn to the sixth turn of the integrated coil are made of the second metal; the seventh to twelfth turns of the coil are made of metal III; the thirteenth to nineteenth turns of the coil are made of metal four. Two identical integrated coils are respectively introduced with two currents with the same magnitude and opposite polarity, the two currents with the same magnitude and opposite polarity generate two reference magnetic fields with the same magnitude and opposite polarity, the two reference magnetic fields with the same magnitude and opposite polarity respectively generate two Hall reference voltages with the same magnitude and opposite polarity in two calibrated Hall devices, and meanwhile the two calibrated Hall devices respectively generate two Hall voltages with the same magnitude and same polarity generated by an external magnetic field.
The comparator is a reverse comparator, the reverse input port of the comparator is connected with the output port of the subtracter, and the normal input port of the comparator is connected with the Hall reference voltage reference value V at 25 DEG CrefWhen the Hall reference voltage value at the temperature is larger than the Hall reference voltage reference value VrefThe comparator outputs "0". When the Hall reference voltage value at the temperature is smaller than the Hall reference voltage reference value VrefThe comparator outputs "1".
As shown in fig. 3, the digital calibration circuit includes 12D flip-flops, and gates and nor gates, which are respectively denoted as the ith D flip-flop, the ith and gate and the ith nor gate, where i is 1, 2, 3, …, 12, a port CK of the ith D flip-flop is connected to a clock input signal CLK1, and a port RN of the ith D flip-flop is connected to a clock input signal CLK 2. The port D of the 1 st D flip-flop is connected with a clock input signal three CLK3, and the port Q of the 1 st D flip-flop is connected with the port D of the 2 nd D flip-flop. The port Q of the jth D flip-flop is connected to the port D of the j +1 th D flip-flop, j being 2, 3, 4, …, 11. One input port of ith AND gate is connected with clock outputThe input signal four CLK4, the other input port of the ith AND gate is connected to the port Q of the ith D flip-flop. One input port of the ith NOR gate is connected with the clock input signal five CLK5, and the other input port of the ith NOR gate is respectively connected with the output port of the ith AND gate. The output port of the ith NOR gate is connected with the ith bit of the input port of the digital-to-analog converter. The digital calibration circuit implements the logic functions of: first, the digital calibration circuit outputs zero, that is, the digital value output by the digital calibration circuit is "0". Then the digital calibration circuit outputs a first position '1' and the other positions '0', the digital output value is converted into voltage through a digital-to-analog converter and further converted into compensation current through a voltage-to-current circuit, the injection of the compensation current increases the Hall reference voltage, and the Hall reference voltage value and V at the momentrefComparing the Hall reference voltage value with VrefIf the voltage is larger than the reference voltage value, the comparator outputs 0, the first position 0 output by the digital calibration circuit is 0, and the Hall reference voltage value at the moment is more than VrefSmall, the comparator outputs a "1", and the "1" of the first bit of the digital calibration circuit output remains. After the first bit comparison is completed, the digital calibration circuit outputs a second position "1" to the digital calibration circuit, and then repeats the above steps until the last bit comparison is completed. In the compensation process, the Hall reference voltage value output by the Hall device is calibrated to gradually approach VrefThe compensation current is simultaneously injected into the bias port of the working Hall device without an integrated coil, namely a detection magnetic field, so that the product of the sensitivity and the bias current is kept unchanged when the temperature is changed, even if the Hall voltage output by the device is kept unchanged when the temperature is changed.
The digital-to-analog converter adopts a 12-bit weighted capacitance digital-to-analog converter, the digital-to-analog converter is divided into a high 7 bit and a low 5 bit by adopting a segmentation method, and the reference voltage value applied to the digital-to-analog converter is 1V.
As shown in fig. 4, the voltage-to-current circuit includes a second amplifier, a resistor R, and a current mirror, where the current mirror includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, and a fifth NMOS transistor, a positive phase input port of the second amplifier is connected to an output port of the digital-to-analog converter, a negative phase input port is connected to one port of the resistor R and to a source of the fifth NMOS transistor, and another port of the resistor R is grounded. The drain electrode of the fifth NMOS tube is connected with the drain electrode of the first PMOS tube, the first PMOS tube is connected with the source electrodes of the second, third and fourth PMOS tubes, the source electrodes of the first to fourth PMOS tubes are connected with VDD, and the grid electrodes are interconnected. The drain electrode of the fourth PMOS tube is connected with the port B of the first calibration Hall device, the drain electrode of the third PMOS tube is connected with the port B of the second calibration Hall device, and the drain electrode of the second PMOS tube is connected with the port B of the working Hall device. The voltage value output by the digital-to-analog converter is converted into compensation current through a voltage-to-current circuit, the compensation current is copied into three identical Hall devices through a current mirror 1:1, and the three identical Hall devices refer to a first calibration Hall device, a second calibration Hall device and a working Hall device.
The working principle is as follows: two identical integrated coils in the temperature drift compensation circuit are respectively introduced with two currents with the same magnitude and opposite polarities, so that the two integrated coils respectively generate two reference magnetic fields with the same magnitude and opposite polarities, the two reference magnetic fields with the same magnitude and opposite polarities enable two ends of two identical calibration Hall devices to respectively induce two Hall reference voltages with the same magnitude and opposite polarities, and meanwhile, an external magnetic field enables two ends of the two calibration Hall devices to induce two Hall voltages with the same magnitude and same polarity; two identical offset voltage elimination circuits eliminate the offset voltages of two calibrated Hall devices; the subtracter subtracts the voltages output by the two offset voltage elimination circuits, and two Hall voltages with the same size and polarity, which are generated by an external magnetic field, are removed, so that twice Hall reference voltages are left; the comparator compares the Hall reference voltage value at the moment with a Hall reference voltage reference value at the temperature of 25 ℃, and outputs a comparison result of '0' or '1'; the digital calibration circuit increases or decreases the digital input quantity of the digital-to-analog converter according to the output result of the comparator; the digital-to-analog converter converts the digital input quantity into voltage output; the voltage-to-current circuit converts the voltage into a current as a compensation current IcompAnd a bias current IbiasSimultaneously into the bias ports B of three identical hall devices. According to the invention, the output Hall voltage value is increased or reduced by increasing or reducing the bias current value of the Hall device, and finally the Hall voltage subjected to temperature drift compensation is output through the magnetic field detection circuit, so that the temperature drift compensation of the Hall sensor is realized.
Simulation (Emulation)
The invention designs and simulates the Hall sensor temperature drift compensation circuit based on a standard integrated CMOS process. The integrated coil I has 19 turns, wherein the coils from the first turn to the sixth turn are made of metal II; the seventh to twelfth turns of the coil are made of metal III; the thirteenth to nineteenth turns of the coil are made of metal four. The line width of each turn of coil is 1.2 μm, the distance between the coils is 2.3 μm, and the distance from the center point of the first turn of coil is 8 μm. Two 10mA currents with the same size and opposite polarities are respectively introduced into the two integrated coils, the direction of a magnetic field generated by the first integrated coil is perpendicular to the Hall device and faces inwards, and the direction of a magnetic field generated by the second integrated coil is perpendicular to the Hall device and faces outwards. The clock input signal CLK1 in the digital calibration circuit is set to: the period is 7 mus, the pulse width is 3.5 mus, and the delay is 600 ns; the clock input signal two CLK2 is set to: pulse width 200ns, delay 0 s; the clock input signal triclk 3 is set to: pulse width 7 mus, delay 500 ns; the clock input signal four CLK4 is set to: the period is 7 mus, the pulse width is 6.7 mus, and the delay is 700 ns; the clock input signal five CLK5 is set to: the period is 7 mus, the pulse width is 1.6 mus and the delay is 5.7 mus. The simulation temperature range of this embodiment is-40 ℃ to 120 ℃, the simulation is performed every 10 ℃, the simulation time is 100 μ s each time, and the simulation result is shown in fig. 5: in the diagram, the abscissa represents temperature, and the ordinate represents the final output hall voltage value of the working hall device. It can be seen that the change in hall voltage is very small when the temperature is varied from-40 ℃ to 120 ℃, and the calculated temperature drift coefficient is 45 ppm/DEG C between the temperature ranges of-40 ℃ to 120 ℃, which is much lower than that in some current reports.
When the temperature of the working environment of the Hall sensor changes, the temperature drift compensation circuit compensates the temperature drift of the Hall voltage in real time, and the Hall voltage is increased or decreased by increasing or decreasing the bias current of the Hall device, so that the temperature drift of the Hall sensor is compensated. Simulation results show that the temperature drift coefficient of the compensated Hall sensor is 45 ppm/DEG C within the temperature range of-40-120 ℃.
The above description is only of the preferred embodiments of the present invention, and it should be noted that: it will be apparent to those skilled in the art that various modifications and adaptations can be made without departing from the principles of the invention and these are intended to be within the scope of the invention.

Claims (7)

1. The utility model provides a hall sensor temperature drift compensation circuit which characterized in that: the device comprises two calibration Hall devices, two integrated coils, a first offset voltage elimination circuit, a second offset voltage elimination circuit, a subtracter, a comparator, a digital calibration circuit, a digital-to-analog converter and a voltage-to-current circuit; the two calibration Hall devices are marked as a first calibration Hall device and a second calibration Hall device, the two integrated coils are respectively marked as a first integrated coil and a second integrated coil, the first integrated coil is integrated above the first calibration Hall device, the second integrated coil is integrated above the second calibration Hall device, and a port B of the first calibration Hall device is connected with a bias current source IbiasThe port D is grounded, and the port A and the port C are connected with the input port of the offset voltage elimination circuit I; a port B of the second calibration Hall device is connected with a bias current source IbiasThe port D is grounded, and the port A and the port C are connected with the input port of the offset voltage eliminating circuit II; the subtracter comprises a resistor R1Resistance two R2Resistance three R3Resistance three R4And an amplifier one, wherein a resistor one R1The input port is connected with the output port of the offset voltage eliminating circuit I and the resistor R1The output port is connected with the inverting input port of the first amplifier and the second resistor R2Is connected with the input port of the resistor II R2The output port of the first amplifier is connected with the output port of the first amplifier; resistance three R3The input port of the voltage-offset eliminating circuit is connected with the output port of the offset voltage eliminating circuit II and the resistor III R3The output port is connected with the positive phase input port of the first amplifier and the resistor IV4One port of the resistor is connected with the resistor four R4The other port of the subtractor is grounded, and the output port of the subtractor is connected with the inverted input port of the comparator; the subtracter subtracts the output signals of the offset voltage elimination circuit I and the offset voltage elimination circuit II, two Hall voltage signals with the same size and the same polarity, which are generated by an external magnetic field, are removed, and double Hall reference voltage signals are output; the positive input port of the comparator is connected with a Hall reference voltage reference value V at 25 DEG Cref(ii) a The output port of the comparator is connected with the input port of the digital calibration circuit; the output port of the digital calibration circuit is connected with the input port of the digital-to-analog converter; the output port of the digital-to-analog converter is connected with the input port of the voltage-to-current circuit; output port I of voltage-to-current circuit and bias current source I of calibration Hall device IbiasThe output port of the voltage-to-current circuit is connected with a port B of the first calibration Hall device, an output port II of the voltage-to-current circuit and a bias current source I of the second calibration Hall devicebiasThe output port of the voltage-to-current circuit is connected with the output port B of the second calibration Hall device, the output port III of the voltage-to-current circuit and the bias current source I of the working Hall devicebiasThe output ports of the Hall sensor are jointly connected with a port B of the working Hall device;
two identical integrated coils I and II are respectively introduced with two currents with the same magnitude and opposite polarity, the two currents with the same magnitude and opposite polarity generate two reference magnetic fields with the same magnitude and opposite polarity, the two reference magnetic fields with the same magnitude and opposite polarity respectively generate two Hall reference voltages with the same magnitude and opposite polarity in two calibrated Hall devices, and meanwhile the two calibrated Hall devices respectively generate two Hall voltages with the same magnitude and same polarity generated by an external magnetic field.
2. The hall sensor temperature drift compensation circuit of claim 1 wherein: the structures of the first calibration Hall device, the second calibration Hall device and the working Hall device are the same.
3. The hall sensor temperature drift compensation circuit of claim 1 wherein: the integrated coil is made of metal interconnection lines in a CMOS manufacturing process.
4. The hall sensor temperature drift compensation circuit of claim 1 wherein: the comparator is a reverse comparator, the reverse input port of the comparator is connected with the output port of the subtracter, and the normal input port of the comparator is connected with the Hall reference voltage reference value V at 25 DEG CrefWhen the Hall reference voltage value at the temperature is larger than the Hall reference voltage reference value VrefWhen, the comparator outputs "0"; when the Hall reference voltage value at the temperature is smaller than the Hall reference voltage reference value VrefThe comparator outputs "1".
5. The hall sensor temperature drift compensation circuit of claim 1 wherein: the digital calibration circuit comprises 12D flip-flops, AND gates and NOR gates, which are respectively marked as the ith D flip-flop, the ith AND gate and the ith NOR gate, wherein i is 1, 2, 3, … and 12, a port CK of the ith D flip-flop is connected with a clock input signal I CLK1, and a port RN of the ith D flip-flop is connected with a clock input signal II CLK 2; the port D of the 1 st D flip-flop is connected with a clock input signal three CLK3, and the port Q of the 1 st D flip-flop is connected with the port D of the 2 nd D flip-flop; the port Q of the jth D flip-flop is connected with the port D of the jth + 1D flip-flop, j is 2, 3, 4, …, 11; one input port of the ith AND gate is connected with a clock input signal four CLK4, and the other input port of the ith AND gate is respectively connected with a port Q of the ith D flip-flop; one input port of the ith NOR gate is connected with a clock input signal five CLK5, and the other input port of the ith NOR gate is respectively connected with the output port of the ith AND gate; the output port of the ith NOR gate is connected with the ith bit of the input port of the digital-to-analog converter; the digital calibration circuit implements the logic functions of: firstly, the output of the digital calibration circuit is cleared, namely the digital value output by the digital calibration circuit is 0; then the digital calibration circuit outputs the first position '1' and the rest position '0', the digital value is converted into the digital value by the digital-to-analog converterThe voltage is further converted into a compensation current through a voltage-to-current circuit, the Hall reference voltage is increased by injecting the compensation current, and the Hall reference voltage value and the Hall reference voltage reference value V at the momentrefComparing, if the Hall reference voltage value is larger than the Hall reference voltage reference value VrefIf the voltage value is larger than the reference voltage value V, the comparator outputs 0, the first position output by the digital calibration circuit is 0, and if the Hall reference voltage value at the moment is larger than the reference voltage value V of the Hall reference voltagerefIf the output voltage is small, the comparator outputs 1, and 1 of the first bit output by the digital calibration circuit is reserved; after the first bit comparison is completed, the digital calibration circuit outputs a second position '1' to the digital calibration circuit, and then the steps are repeated until the last bit comparison is completed; in the compensation process, the Hall reference voltage value output by the Hall device is calibrated to gradually approach the Hall reference voltage reference value VrefThe compensation current is simultaneously injected into the bias port of the working Hall device without an integrated coil, namely a detection magnetic field, so that the product of the sensitivity and the bias current is kept unchanged when the temperature is changed, even if the Hall voltage output by the device is kept unchanged when the temperature is changed.
6. The hall sensor temperature drift compensation circuit of claim 1 wherein: the digital-to-analog converter adopts a 12-bit weighted capacitance digital-to-analog converter, the digital-to-analog converter is divided into a high 7 bit and a low 5 bit by adopting a segmentation method, and the reference voltage value applied to the digital-to-analog converter is 1V.
7. The hall sensor temperature drift compensation circuit of claim 1 wherein: the voltage-to-current circuit comprises a second amplifier, a resistor R and a current mirror, wherein the current mirror comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube and a fifth NMOS (N-channel metal oxide semiconductor) tube; the drain electrode of a fifth NMOS tube is connected with the drain electrode of the first PMOS tube, the first PMOS tube is connected with the source electrodes of the second, third and fourth PMOS tubes, the source electrodes of the first to fourth PMOS tubes are connected with VDD, and the grid electrodes are interconnected; the drain electrode of the fourth PMOS tube is connected with the port B of the first calibration Hall device, the drain electrode of the third PMOS tube is connected with the port B of the second calibration Hall device, and the drain electrode of the second PMOS tube is connected with the port B of the working Hall device; the voltage value output by the digital-to-analog converter is converted into compensation current through a voltage-to-current circuit, and the compensation current is copied into the first calibration Hall device, the second calibration Hall device and the working Hall device through the current mirror 1: 1.
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