RU2721943C1 - Low-temperature input stage of operational amplifier with high attenuation of input common-mode signal on complementary field-effect transistors with control p-n junction - Google Patents

Abstract

FIELD: radio engineering; analogue microelectronics.

SUBSTANCE: low-temperature input cascade comprises power supply busbars, input field-effect transistors with integrated sources, reference current sources, additional field-effect transistors, wherein said transistors are field-effect transistors with control p-n junction.

EFFECT: technical result consists in improvement of attenuation factor of input common-mode signals, having a significant effect on errors of various analogue interfaces with the claimed device.

3 cl, 13 dwg

Description

The invention relates to the field of radio engineering and analog microelectronics and can be used in analog and analog-to-digital interfaces for processing sensor signals.

In modern electronic equipment, differential operational amplifiers (op amps) with significant different parameters are used. A special place is occupied by op amps based on complementary input stages (the so-called dual-input-stage) [1-31]. Input cascades (VK) of this class are implemented both on bipolar [1-16] and on CMOS transistors [17-30]. The architecture of the op-amp with such VK [1-31] is the basis of more than 50 serial microcircuits produced by leading microelectronic companies in the world.

The closest prototype (Fig. 1) of the claimed device is an input stage in the structure of an operational amplifier based on current mirrors PT1, PT2 according to patent application US 2006/0125522, fig. 1a, fig. 3, 2006. It contains (Fig. 1) the first 1 and second 2 inputs of the device, the first 3 current output of the device, matched with the first 4 bus of the power source, the second 5 current output of the device, matched with the second 6 bus of the power source, first 7 and the second 8 input field-effect transistors with combined sources, the third 9 and fourth 10 input field-effect transistors with combined sources, the first 11 source of reference current associated with the combined sources of the first 7 and second 8 input field-effect transistors with combined sources, the second 12 source of reference current, connected to the combined sources of the third 9 and fourth 10 input field-effect transistors with combined sources, the first 1 input of the device connected to the gates of the first 7 and third 9 input field-effect transistors, the second 2 input of the device connected to the gates of the second 8 and fourth 10 input field-effect transistors, drain the second 8 input field-effect transistor is connected to the first 3 current output of the device, stock the fourth 10 input field-effect transistor is connected to the second 5 current output of the device, the drain of the first 7 input field-effect transistor is connected to the third 13 current output of the device, matched with the first 4 bus of the power source, and the drain of the third 9 input field-effect transistor is connected to the fourth 14 current output of the device, consistent with the second 6 bus power source.

A significant drawback of the well-known op amp input stage is that, when implemented on the basis of complementary field-effect transistors with a pn junction, it provides small attenuation coefficients for input common-mode signals (K_os.sf) This is due to the fact that in the scheme of the VK prototype on its K_os.sf the output resistance of the first 11 (r_i11) and the second 12 (r_i12) reference current sources that create “spurious” transmission channels of the input common-mode signal u_c= u_c1= u_c2 to the first 3 and second 5 current outputs of the device.

The main objective of the proposed invention is to increase the attenuation coefficient of the input common-mode signals when implementing VCs on complementary field-effect transistors with a pn junction, which has a significant effect on the errors of various analog interfaces with the claimed device.

The problem is solved in that in the input stage of the operational amplifier of FIG. 2, containing the first 1 and second 2 inputs of the device, the first 3 current output of the device, matched with the first 4 bus power source, the second 5 current output of the device, matched with the second 6 bus power source, the first 7 and second 8 input field-effect transistors with combined sources , the third 9 and fourth 10 input field-effect transistors with combined sources, the first 11 reference current source connected to the combined sources of the first 7 and second 8 input field effect transistors with combined sources, the second 12 reference current source connected to the combined sources of the third 9 and fourth 10 input field-effect transistors with combined sources, the first 1 input of the device connected to the gates of the first 7 and third 9 input field-effect transistors, the second 2 input of the device connected to the gates of the second 8 and fourth 10 input field-effect transistors, the drain of the second 8 input field-effect transistor is connected to the first 3 the current output of the device, the fourth stock 10 input field transistor is connected to the second 5 current output of the device, the drain of the first 7 input field-effect transistor is connected to the third 13 current output of the device, matched with the first 4 bus of the power source, and the drain of the third 9 input field-effect transistor is connected to the fourth 14 current output of the device, matched with second 6 power supply bus, new elements and communications are provided - the first 11 reference current source is based on the first 15 and second 16 additional field effect transistors, the gates of which are connected to the combined sources of the first 7 and second 8 input field effect transistors, and the sources are connected to the combined sources the first 7 and second 8 input field-effect transistors, and the drain of the first 15 additional field-effect transistor is connected to the second 5 current output of the device, and the drain of the second 16 additional field-effect transistor is matched to the second 6 bus of the power source, the second 12 reference current source is based on the third 17 and a quarter 18 additional field-effect transistors, the gates of which are connected to the combined sources of the third 9 and fourth 10 input field-effect transistors, and the sources are connected to the combined sources of the third 9 and fourth 10 input field-effect transistors, and the drain of the third 17 additional field-effect transistor is connected to the first 3 current output devices, and the drain of the fourth 18 additional field-effect transistors is matched with the first 4 bus of the power supply, and field-effect transistors with a control pn junction are used as the field-effect transistors mentioned above.

In the drawing of FIG. 1 shows the input cascade prototype in the structure of a typical operational amplifier based on current mirrors PT1, PT2.

In the drawing of FIG. 2 is a diagram of the inventive device in accordance with claim 1, and in the drawing of FIG. 3 - scheme VK in accordance with claim 2 of the claims.

In the drawing of FIG. 4 shows a wiring diagram of the inventive input stage of FIG. 3 in the structure of the op-amp on current mirrors 21 and 22.

In the drawing of FIG. 5 shows a diagram of the inclusion of the inventive input stage of FIG. 3 in the structure of the op-amp on “kinked” cascodes (elements 25-28).

In the drawing of FIG. 6 is a diagram of the inclusion of the inventive input stage of FIG. 3 in the structure of an op-amp with a paraphase output, the output stages of which are implemented on “kinked” cascodes (elements 25-28 and 31-34).

In the drawing of FIG. 7 shows a diagram of the inclusion of the inventive input cascade according to claim 3 of the claims in the structure of the op-amp on the “inverted” cascodes (elements 25-28).

In the drawing of FIG. 8 shows the static mode of the input stage - the prototype of FIG. 1 in the structure of an op-amp based on current mirrors in the LTSpice simulation environment on integrated transistor models of Integral OJSC (Minsk) at t = 27 ° C.

In the drawing of FIG. 9 shows the static mode of the input stage, the prototype of FIG. 1 in the structure of an op-amp based on current mirrors in the LTSpice simulation environment on integrated transistor models of Integral OJSC (Minsk) at a temperature t = -197 ° C.

In the drawing of FIG. 10 shows the frequency dependence of the slope g _cm = i _n / u _c transmitting the input common-mode signal u _c = u _c1 = u _c2 in a typical op-amp with an input cascade of the prototype of FIG. 8 at temperatures of 27 ° C and -197 ° C.

In the drawing of FIG. 11 shows the static mode of the inventive input stage of FIG. 4 in the structure of op-amps on current mirrors in the LTSpice simulation environment on models of integrated transistors of Integral OJSC (Minsk) at t = 27 ° С.

In the drawing of FIG. 12 shows the static mode of the inventive input stage of FIG. 4 in the structure of op-amps on current mirrors in the LTSpice simulation environment on models of integrated transistors of Integral OJSC (Minsk) at t = -197 ° С.

In the drawing of FIG. 13 shows the frequency dependence of the slope g _{cm of} transmitting the input common-mode signal u _c = u _c1 = u _c2 in a typical op-amp with the claimed input stage of FIG. 11 at temperatures of 27 ° C and -197 ° C.

The low-temperature input stage of the operational amplifier with increased attenuation of the input common-mode signal on complementary field-effect transistors with a p-n junction control of FIG. 2 contains the first 1 and second 2 inputs of the device, the first 3 current output of the device, matched with the first 4 bus power source, the second 5 current output of the device, matched with the second 6 bus power source, the first 7 and second 8 input field-effect transistors with combined sources, the third 9 and fourth 10 input field-effect transistors with combined sources, the first 11 reference current source connected to the combined sources of the first 7 and second 8 input field effect transistors with combined sources, the second 12 reference current source connected to the combined sources of the third 9 and fourth 10 input field-effect transistors with combined sources, the first 1 input of the device connected to the gates of the first 7 and third 9 input field-effect transistors, the second 2 input of the device connected to the gates of the second 8 and fourth 10 input field-effect transistors, the drain of the second 8 input field-effect transistor is connected to the first 3 current the output of the device, the stock of the fourth 10 input the field-effect transistor is connected to the second 5 current output of the device, the drain of the first 7 input field-effect transistor is connected to the third 13 current output of the device matched with the first 4 bus of the power supply, and the drain of the third 9 input field-effect transistor is connected to the fourth 14 current output of the device matched to the second 6 bus power supply. The first 11 reference current source is based on the first 15 and second 16 additional field-effect transistors, the gates of which are connected to the combined sources of the first 7 and second 8 input field-effect transistors, and the sources are connected to the combined sources of the first 7 and second 8 input field-effect transistors, and the drain of the first 15 additional field-effect transistor is connected to the second 5 current output of the device, and the drain of the second 16 additional field-effect transistor is matched with the second 6 bus of the power source, the second 12 reference current source is based on the third 17 and fourth 18 additional field-effect transistors, the gates of which are connected to the combined sources third 9 and fourth 10 input field-effect transistors, and the sources are connected to the combined sources of the third 9 and fourth 10 input field-effect transistors, moreover, the drain of the third 17 additional field-effect transistor is connected to the first 3 current output of the device, and the drain of the fourth 18 additional field-effect the transistor is matched to the first 4 bus of the power source, and field transistors with a p-n junction control are used as the field-effect transistors mentioned above.

In the drawing of FIG. 3, in accordance with paragraph 2 of the claims, the sources of the first 15 and second 16 additional field effect transistors are connected to the combined sources of the first 7 and second 8 input field effect transistors through the first 19 additional resistor, and the sources of the third 17 and fourth 18 additional field effect transistors the combined sources of the third 9 and fourth 10 input field-effect transistors through the second 20 additional resistor.

In the drawing of FIG. 4, the claimed input stage of FIG. 3 is used in the structure of an operational amplifier based on current mirrors 21 and 22, the outputs of which are connected to the output of device 23. The two-terminal network 24 models the op amp load properties.

In the drawing of FIG. 5, the claimed input stage of FIG. 3 is used in the structure of an operational amplifier, the output stage of which is implemented on “bent” cascodes and includes auxiliary resistors 25, 26 and output field-effect transistors 27, 28, the drains of which are connected to the output of device 29. Two-terminal 30 simulates the op amp load properties.

In the drawing of FIG. 6 is a diagram of the inclusion of the inventive input stage of FIG. 3 in the structure of an op-amp with a paraphase output, the first output stage of which is implemented on “bent” cascodes and includes auxiliary resistors 25, 26, output field-effect transistors 27, 28, the drains of which are connected to the first 29 output of the device. Bipolar 30 here simulates the properties of the op amp load connected to the output of the first output stage (elements 25-28). The second output stage in the circuit of FIG. 6 is implemented on “kinked” cascodes and includes auxiliary resistors 31, 34, output field-effect transistors 32, 33, the drains of which are connected to the second 35 output of the device. Bipolar 36 here simulates the properties of the op amp load connected to the output 35 of the second output stage (elements 31,32,33,34).

In the drawing of FIG. 7, in accordance with paragraph 3 of the claims, the source of the first 15 additional field-effect transistor is connected to the combined sources of the first 7 and second 8 input field-effect transistors through the third 37 additional resistor, the source of the second 16 additional field-effect transistor is connected to the combined sources of the first 7 and second 8 the input field-effect transistors through the fourth 38 additional resistor, the source of the third 17 additional field-effect transistor is connected to the combined sources of the third 9 and fourth 10 input field-effect transistors through the fifth 39 additional resistor, and the source of the fourth 18 additional field-effect transistor is connected to the combined sources of the third 9 and fourth 10 input field-effect transistors through the sixth 40 additional resistor. Moreover, in the drawing of FIG. 7, the claimed input stage according to claim 3 is connected to the output stage on “bent” cascodes, which is implemented on the elements 25, 26, 27, 28 and has a first output of the device 29, to which the two-terminal load 30 is connected.

Consider the operation of the inventive device of FIG. 3.

Changes in the input common-mode signal u _c = u _c1 = u _c2 at the first 1 and second 2 inputs of the device lead to the appearance of increments of currents through the first 19 and second 20 additional resistors

(1)

(1)

(2)

(2)

where R ₁₉ , R ₂₀ - resistance of the first 19 and second 20 additional resistors,

μ is the internal feedback coefficient of field-effect transistors 15 (16) and 17 (18), taking into account the effect of voltage changes at the drains of these transistors on the displacement of their gate-gate characteristics at a constant drain current:

. (3)

. (3)

The increment of the currents 2i ₀₁ , 2i ₀₂ through the first 19 and second 20 additional resistors are transmitted respectively to the first 3 and second 5 current outputs. As a result, in equivalent load resistances (R _n1 , R _n2 ), the currents i ₀₁ and i ₀₂ are subtracted, which reduces the conductivity of the input common-mode signal g _cm = i _out / u _c to these outputs.

If the current mirrors 21 and 22 are used as the load connected to the first 3 and second 5 current outputs, as is done in the circuit of FIG. 4, then in the bipolar load 24 provides mutual compensation for errors due to "creep" of the input common-mode signal to the output of the device 23. Ultimately, this improves K _OS . Indeed, K _os.sf in the op amp circuit of FIG. 4 is determined by the formulas

(4)

(4)

(5)

(5)

(6)

(6)

(7)

(7)

where K _d is the gain of the input differential signal of the OS (u _I = u _c1 -u _c2 );

To _s.sf - the conversion coefficient of the input common-mode signal u _c = u _c1 = u _c2 to the output voltage of the OS;

S _d - the steepness of the transmission of the input differential voltage from the first 1 and second 2 inputs of the device to the output of the OS 23;

g _cm << S _d - the steepness of the input common-mode signal u _c = u _c1 = u _c2 to the output 23.

As follows from the graphs of FIG. 10 and FIG. 13, the claimed VK, in contrast to the VK prototype of FIG. 1, provides negligibly small values of g _cm , which contributes to an increase in K _OS.sf (formulas 4-7).

The above common-mode error compensation effects also work in the circuits of FIG. 5, FIG. 6 and FIG. 7, in which the inventive input stage is used (Fig. 3), as well as output stages on “kinked” cascodes.

Thus, the proposed input stage of the op-amp provides an increase in _O.s. in the op-amp with different options for constructing the output stages (Fig. 4, Fig. 5, Fig. 6, Fig. 7).

The results of computer simulation of an op-amp with the proposed input stage of FIG. 3 shown in FIG. 10 and FIG. 13 show that the conductivity of transferring a common-mode signal to the output of such an op-amp is reduced at low frequencies in a wide temperature range by several orders of magnitude. Moreover, this gain (N-time) is determined by the ratio of the OA common mode signal transmission conductivities with the input stage without compensation (prototype of FIG. 1) to the OA common mode signal transmission conductivity with the claimed VC of FIG. 3.

Thus, the proposed input stage has significant advantages in comparison with the VK-prototype. Due to the use of field-effect transistors with a p-n junction control, the circuit of the claimed VC and OA based on it stably operate in the range of cryogenic temperatures and in the conditions of penetrating radiation [32], and also provides an extremely low level of low-frequency noise.

BIBLIOGRAPHIC LIST

1. Patent application US 2006/0125522, fig.1a, fig.3, 2006

2. Patent application US 2005/0024140, fig.12, 2005

3. US Pat. No. 5,714,906, fig. 1a, 1998

4. Patent US 7.915.948, fig. 6, fig. 10, 2011

5. Patent US 4.783.637, fig. 1, 1988

6. Patent US 5.515.005, fig. 1, fig. 2, 1996

7. Patent SU No. 1220105, 1984

8. Patent US 3.968.451, fig. 7, 1976.

9. US Pat. No. 5,374,897, fig. 3, 1994

10. Patent US 6.504.419, fig. 2, 2003

11. Patent US 5.512.859, fig. 1, 1996

12. US Pat. No. 4,636,743, fig. 1.1987 g.

13. US patent 6,268,769, fig. 3, 2001

14. Patent US 3.974.455, fig. 7, 1976

15. Patent US 5.291.149, 1994

16. Auth. testimonial. USSR No. 530425

17. Patent US 5.814.953, 1998.

18. Patent US 5.225.791, 1993

19. Auth. testimonial. USSR No. 611288

20. Patent US 6.794.940, fig. 1, 2004

21. Patent application US 2006/0226908, fig. 4, 2006

22. Patent application US 2001/0052818, fig. 1, 2001

23. Patent application US 2004/0174216, fig. 1, fig. 2, 2004

24. Patent EP 1150423, fig. 2, 2001.

25. Patent application US 2003/0206060, fig. 1, 2003

26. US patent 6.642.789, fig. 1, 2003

27. US patent 4.377.789, fig. 1, 1983

28. US Pat. No. 6,100,762, fig. 1, 2000

29. US patent 5.909.146, fig. 5, 1999

30. Patent US 5.621.357, fig. 4, 1997

31. US patent 6.844.781, fig.2, 2005.

32. OV Dvornikov, VL Dziatlau, NN Prokopenko, KO Petrosiants, NV Kozhukhov and VA Tchekhovski, "The accounting of the simultaneous exposure of the low temperatures and the penetrating radiation at the circuit simulation of the BiJFET analog interfaces of the sensors," 2017 International Siberian Conference on Control and Communications (SIBCON), Astana, 2017, pp. 1-6. DOI: 10.1109 / SIBCON.2017.7998507

Claims (3)

1. Low-temperature input stage of the operational amplifier with increased attenuation of the input common-mode signal at complementary field effect transistors with a pn junction control, containing the first (1) and second (2) device inputs, the first (3) current output of the device, matched with the first (4) bus power supply, the second (5) current output of the device, consistent with the second (6) bus power supply, the first (7) and second (8) input field effect transistors with combined sources, the third (9) and fourth (10) input field effect transistors with combined sources, the first (11) reference current source associated with the combined sources of the first (7) and second (8) input field effect transistors with combined sources, the second (12) reference current source associated with the combined sources of the third (9) and fourth ( 10) input field-effect transistors with combined sources, and the first (1) input of the device is connected to the gates of the first (7) and third (9) input field-effect transistors, sec the second (2) input of the device is connected to the gates of the second (8) and fourth (10) input field-effect transistors, the drain of the second (8) input field-effect transistor is connected to the first (3) current output of the device, the drain of the fourth (10) input field-effect transistor the second (5) current output of the device, the drain of the first (7) input field-effect transistor is connected to the third (13) current output of the device, matched with the first (4) bus of the power supply, and the drain of the third (9) input field-effect transistor is connected to the fourth (14) ) the current output of the device, consistent with the second (6) bus of the power source, characterized in that the first (11) reference current source is based on the first (15) and second (16) additional field effect transistors, the gates of which are connected to the combined sources of the first ( 7) and the second (8) input field-effect transistors, and the sources are connected to the combined sources of the first (7) and second (8) input field-effect transistors, and the drain of the first (15) additional field the transistor is connected to the second (5) current output of the device, and the drain of the second (16) additional field-effect transistor is matched to the second (6) bus of the power source, the second (12) reference current source is based on the third (17) and fourth (18) additional field effect transistors, the gates of which are connected to the combined sources of the third (9) and fourth (10) input field effect transistors, and the sources are connected to the combined sources of the third (9) and fourth (10) input field effect transistors, and the drain of the third (17) additional field the transistor is connected to the first (3) current output of the device, and the drain of the fourth (18) additional field-effect transistor is matched to the first (4) bus of the power source, and field transistors with a control pn junction are used as the above-mentioned field transistors. 2. The low-temperature input stage of the operational amplifier with an increased attenuation of the input common-mode signal on complementary field-effect transistors with a control pn junction according to claim 1, characterized in that the sources of the first (15) and second (16) additional field-effect transistors are connected with the combined sources of the first (7 ) and the second (8) input field effect transistors through the first (19) additional resistor, and the sources of the third (17) and fourth (18) additional field effect transistors are connected to the combined sources of the third (9) and fourth (10) input field effect transistors through the second ( 20) additional resistor. 3. The low-temperature input stage of the operational amplifier with increased attenuation of the input common-mode signal on complementary field-effect transistors with a control pn junction according to claim 1, characterized in that the source of the first (15) additional field-effect transistor is connected to the combined sources of the first (7) and second (8 ) input field-effect transistors through a third (37) additional resistor, the source of the second (16) additional field-effect transistor is connected to the combined sources of the first (7) and second (8) input field-effect transistors through a fourth (38) additional resistor, the source of the third (17) additional the field-effect transistor is connected to the combined sources of the third (9) and fourth (10) input field-effect transistors through a fifth (39) additional resistor, and the source of the fourth (18) additional field-effect transistor is connected to the combined sources of the third (9) and fourth (10) input field transistors through the sixth (40) additional resistor.

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