RU2710296C1 - Differential cascade on complementary jfet field-effect transistors with high attenuation of input in-phase signal - Google Patents

Abstract

FIELD: radio equipment.

SUBSTANCE: invention relates to the field of radio equipment. Disclosed is a differential cascade on complementary JFET field-effect transistors with high attenuation of the input in-phase signal, which comprises first (1) and second (2) inputs of the device, first (3) input field-effect transistor, first (4) current output of device, first (5) bus of power supply source, second (6) input field transistor, second (7) current output of device, third (8) input field transistor, third (9) current output of device, second (10) power supply bus, fourth (11) input field transistor, fourth (12) current output of device, first (13) additional field transistor, first (14) auxiliary two-terminal device.

EFFECT: creation of conditions, at which higher values of attenuation factor of input in-phase signals and noise suppression factor on power buses are provided.

1 cl, 12 dwg

Description

The invention relates to the field of radio engineering and communications and can be used as a device for amplifying analog signals in the structure of analog microcircuits for various functional purposes, for example, operational amplifiers (op amps), comparators, bridge power amplifiers, etc., incl. operating at low temperatures and exposure to radiation [1].

Known circuits of classical differential cascades on complementary transistors [2-28], including on complementary CMOS field-effect transistors [3-28] and complementary field-effect transistors with a pn junction control (JFet) [2], which became the basis of many serial analog microcircuits. In the literature on analog microelectronics, this class of DC has a special designation - dual-input-stage [29].

For operation at low temperatures and severe restrictions on the level of noise, the use of JFet field-effect transistors is promising [30-32]. DCs of this class are actively used in the structure of low-noise analog interfaces for processing sensor signals [33-35].

 The closest prototype (Fig. 1) of the claimed device is a differential cascade described in patent US 5.291.149, fig.4, 1994, which contains the first 1 and second 2 inputs of the device, the first 3 input field-effect transistor, the gate of which is connected to the first 1 the input of the device, the drain is connected to the first 4 current output of the device, matched with the first 5 bus of the power source, the second 6 input field-effect transistor, the gate of which is connected to the second 2 input of the device, and the drain is connected to the second 7 current output of the device, matched with the first 5 bus the power source, and the sources of the first 3 and second 6 input field-effect transistors are connected to each other, the third 8 input field-effect transistor, the gate of which is connected to the first 1 input of the device, the drain is connected to the third 9 current output of the device, matched with the second 10 bus power source the fourth 11 input field-effect transistor, the gate of which is connected to the second 2 input of the device, and the drain is connected to the fourth 12 current output of the device, matched with the second 10 bus power supply, and the sources of the third 8 and fourth About 11 input field effect transistors are connected to each other.

A significant disadvantage of the known DC of FIG. 1 consists in the fact that the static mode of its input field-effect transistors (PTs) is determined by two independent sources of the reference current I ₁ (I ₂ ), which, as a rule, are not identical due to different cutoff voltages of the PT with p- and n-channels. This becomes a source of additional errors in the amplification of signals, worsens the attenuation coefficient of the input common-mode signals of the DC (K _OS.sf ), as well as the suppression coefficient of noise on the power buses (K _PP ). In precision devices, the requirements for these parameters sometimes dominate.

The main objective of the alleged invention is to create conditions under which in the Palace of Culture of FIG. 1 provides higher values of K _OS.Fs and K _pp , incl. at low temperatures (up to -197̊С).

The problem is solved in that in the differential cascade of FIG. 1, containing the first 1 and second 2 inputs of the device, the first 3 input field-effect transistor, the gate of which is connected to the first 1 input of the device, the drain is connected to the first 4 current output of the device, matched with the first 5 bus power supply, the second 6 input field-effect transistor, gate which is connected to the second 2 input of the device, and the drain is connected to the second 7 current output of the device, matched with the first 5 bus of the power source, and the sources of the first 3 and second 6 input field-effect transistors are connected to each other, the third 8 input field an EV transistor, the gate of which is connected to the first 1 input of the device, the drain is connected to the third 9 current output of the device, matched with the second 10 bus of the power supply, the fourth 11 input field-effect transistor, the gate of which is connected to the second 2 input of the device, and the drain is connected to the fourth 12 the current output of the device, consistent with the second 10 bus of the power source, and the sources of the third 8 and fourth 11 input field-effect transistors are connected to each other, new elements and communications are provided - the first 13 will be added to the circuit A field-effect transistor, the gate of which is connected to the combined sources of the first 3 and second 6 input field-effect transistors, the drain is connected to the combined sources of the third 8 and fourth 11 input field-effect transistors, and the source is connected to the combined sources of the first 3 and second 6 input field-effect transistors through the first 14 auxiliary bipolar.

In the drawing of FIG. 1 is a diagram of a DC prototype of US Pat. No. 5,291.149, fig. 4, 1994, and in the drawing of FIG. 2 is a diagram of the inventive differential cascade on complementary field effect transistors with a pn junction in accordance with claim 1.

In the drawing of FIG. 3 shows a diagram of the inventive differential cascade in accordance with claim 2.

In the drawing of FIG. 4 shows the static mode of the DC of FIG. 3 at t = -197ᵒC in LTSpice environment on CJFet models of transistors of Integral OJSC (Minsk).

In the drawing of FIG. 5 shows the flow characteristics of the DC of FIG. 4 at a temperature of 27 ° C, resistance of resistors R1 = R2 = 10 kOhm, supply voltages V1 = V2 = ± 5V for current outputs Out.1, Out.2, Out.3, Out.4 with an input voltage V3 = U _in , varying in limits -5 ÷ 5V.

In the drawing of FIG. 6 shows the flow characteristics of the DC of FIG. 4 at a temperature of -197 ° C, resistance of resistors R1 = R2 = 10 kOhm, supply voltages V1 = V2 = ± 5V for current outputs Out.1, Out.2, Out.3, Out.4 with an input voltage V3 = U _in , varying within -5 ÷ 5V.

In the drawing of FIG. 7 shows the static mode of the DC of FIG. 2 in the mode of measuring the transmission conductivity of the input common-mode signal u _c with the equivalent resistance of the resistor R15 (R1) = 13.5 kOhm, which provides identical static currents of the input field-effect transistors J1-J4 at 100 μA at a temperature of 25 ° C.

In the drawing of FIG. 8 shows the frequency dependence of the transconductance of the input common mode signal transduction (S _sp) differentsilnogo cascade FIG. 7 from inputs 1, 2 to the first 4 (Output.i ₁ ) and second 7 (Output.i ₂ ) current outputs.

In the drawing of FIG. 9 shows the frequency dependence of the steepness of interference transmission on the power buses S _p ⁽⁺⁾ , S _p ^(-) (sinusoidal voltage with an amplitude of 100 mV on the positive and negative buses) in the DC of FIG. 7 on the first 4 (Output i ₁ ) and second 7 (Output i ₂ ) current outputs.

In the drawing of FIG. 10 presents static currents in the inventive DC of FIG. 2 in the mode of measuring the transmission conductivity of the input common-mode signal at a temperature of 25 ° C.

In the drawing of FIG. 11 shows the frequency dependence of the steepness of transmission S _{sf of the} input common-mode signal DC of FIG. 10 for the first 4 (Output i ₁ ) and second 7 (Output i ₂ ) current outputs with static currents of input field effect transistors of 100 μA, identical to the currents of the PT in the circuit of FIG. 7.

In the drawing of FIG. 12 shows the frequency dependence of the steepness of interference transmission on the power buses S _p ⁽⁺⁾ , S _p ^(-) with an amplitude of 100 mV in the DC of FIG. 10 for the first 4 (Output i ₁ ) and second 7 (Output i ₂ ) current outputs.

The differential cascade on complementary JFET field effect transistors with increased attenuation of the input common mode signal of FIG. 2 contains the first 1 and second 2 inputs of the device, the first 3 input field-effect transistor, the gate of which is connected to the first 1 input of the device, the drain is connected to the first 4 current output of the device, matched with the first 5 bus of the power source, the second 6 input field-effect transistor, the gate of which connected to the second 2 input of the device, and the drain is connected to the second 7 current output of the device, consistent with the first 5 bus power supply, and the sources of the first 3 and second 6 input field-effect transistors are connected to each other, the third 8 input field the first transistor, the gate of which is connected to the first 1 input of the device, the drain is connected to the third 9 current output of the device, matched with the second 10 bus of the power supply, the fourth 11 input field-effect transistor, the gate of which is connected to the second 2 input of the device, and the drain is connected to the fourth 12 the current output of the device, consistent with the second 10 bus power supply, and the sources of the third 8 and fourth 11 input field-effect transistors are connected to each other. The first 13 additional field-effect transistor is introduced into the circuit, the gate of which is connected to the combined sources of the first 3 and second 6 input field-effect transistors, the drain is connected to the combined sources of the third 8 and fourth 11 input field-effect transistors, and the source is connected to the combined sources of the first 3 and second 6 input field-effect transistors through the first 14 auxiliary two-terminal.

The resistor 15 in the circuit of FIG. 2 corresponds to the equivalent resistance between the sources of transistors 3 and (6) and 8 (11). Its introduction is necessary to assess the effectiveness of the proposed circuit solutions in terms of the value of realized K _os.sf and K _pp .

In addition, in the drawing of FIG. 2 two-terminal 16, 17, 18 and 19 model the properties of the load DC. In practical analog microcircuits, the inputs of current mirrors are used as such loads, providing further conversion of current signals at outputs 4, 7, 9, 12.

In the drawing of FIG. 3, in accordance with paragraph 2 of the claims, a second 20 additional field-effect transistor is introduced into the circuit, the gate of which is connected to the combined sources of the third 8 and fourth 11 input field-effect transistors, the drain is connected to the combined sources of the first 3 and second 6 input field-effect transistors, and the source is connected to the combined sources of the third 8 and fourth 11 input field-effect transistors through the second 21 auxiliary two-terminal.

Consider the operation of the remote control of FIG. 2, taking into account the results of comparative computer simulation presented in the drawings of FIG. 8, FIG. 9, FIG. 11 and FIG. 12.

Computer simulation of the pass-through characteristic of the DC of FIG. 4 in the LTspice environment at room (Fig. 5) and cryogenic (Fig. 8) temperatures shows that the considered circuitry solution converts the input common-mode voltage of the DC u _c to the DC output currents (Out.1, Out.2, Out.3, Out.4) in the range V _in = ± 1V. This is sufficient for many applications.

The attenuation coefficient of the input common mode signal DK of figure 2 for the first 4 outputs (Output.i ₁ ) is determined by the formula

(1)

(1)

where K _sf = R ₁₆ S _sf is the conversion coefficient of the input common-mode signal DK (u _c = u _c1 = u _c2 ) to the voltage at the equivalent two-terminal load 16;

S _cf = i _out.1 / u _c is the transmission conductivity of the input common-mode signal u _c at the first 4 current output;

K _d = R ₁₆ (S ₃ + S ₆ ) is the differential voltage gain from the differential input of the DC (inputs 1, 2) to the first 4 current output;

S ₃ ≈S ₆ is the slope of the gate-gate characteristic of the first 3 and second 6 input field-effect transistors.

From equation (1) we can obtain

(2)

(2)

Similar formulas can also be obtained for interference suppression coefficients on power buses

(3)

(3)

(4)

(4)

Thus, to improve the noise immunity is necessary to minimize the DC circuit design for transmission by conduction in-phase input signal (S _sph = 0) and the conductivity of the tire power transmission noise (S _n ⁽⁺⁾ = 0, S _n ^(-) = 0).

The results of comparative computer simulation of the circuit of FIG. 2 with additional elements 13 and 14, which are introduced in accordance with claim 1, as well as without elements 13 and 14 (only with a resistor 15 providing an identical static mode of the input field-effect transistors DC 100 μA), are presented in the drawings of FIG. 8 and FIG. 11. Their analysis shows that the proposed circuitry solution provides at low frequencies the following transmission conductivities S _sf = 376 pSm and S _p ⁽⁺⁾ = S _p ^(-) = 900 pSm.

At the same time the DC analog circuit gives S _sph ⁼ 48 nS, S _n ^{(+) *} = S _n ^{(-) =} 128 nS.

Thus, in the inventive device, the coefficients K _os.sf and K _{pp are} improved by at least two orders of magnitude:

(5)

(5)

(6)

(6)

(7)

(7)

Therefore, the claimed device has significant advantages in comparison with the known circuitry of the DC of the dual-input-stage class [2-28] in terms of the attenuation coefficient of the input common-mode signal and the level of interference suppression on the power buses. This allows us to recommend the considered DC circuits for practical use in precision op-amps and construction of low-noise, low-temperature, and radiation-resistant analog microcircuits using the CJFet process of Integral OJSC (Minsk), as well as to the complementary bipolar field process of NPP Pulsar JSC (Moscow city).

Bibliographic list

1. Dvornikov OV, Dziatlau VL, Prokopenko NN, Petrosiants KO, Kozhukhov NV and Tchekhovski VA The accounting of the simultaneous exposure of the low temperatures and the penetrating radiation at the circuit simulation of the BiJFET analog interfaces of the sensors // 2017 International Siberian Conference on Control and Communications (SIBCON), Astana, 2017, pp. 1-6. DOI: 10.1109 / SIBCON.2017.7998507

2. Patent US 5.291.149 fig. 4, 1994

1. Patent US 4.377.789, fig. 1, 1983

2. Patent application US 2006/0125522, 2006

3. Patent US 7.907.011, 2011

4. US 2008/0024217, fig. 1, 2008

5. Patent EP 0318263.1989.

6. US patent 5.907.259, fig. 1, 1999

7. Patent US 7.408.410, 2008

8. Patent US 6.628.168, fig.2, 2003.

9. Patent application US 2009/0302895, 2009

10. US Pat. No. 5,714,906, fig. 4, 1998

11. Patent US 2005/0285677, 2005.

12. US Pat. No. 5,070.306, fig. 3, 1991

13. Patent US 2010/001797, 2010

14. Patent US 6.972.623, fig. 4, fig. 6, 2005

15. Patent US 2008/0252374, 2008

16. Patent US 7.586.373, 2009

17. Patent US 2006/0215787, 2006.

18. Patent US 7.453.319, 2008

19. Patent US 2004/0174216, fig. 2, 2004

20. Patent US 7.215.200, fig. 6, 2007

21. US patent No. 6.433.637, fig. 2, 2002

22. US patent No. 6.392.485, 2002

23. Patent US 5.963.085, fig. 3, 1999

24. Patent US 6.788.143, 2004.

25. US patent 4.390.850, 1983.

26. US patent 6.696.894, fig. 1, 2004

29. Prokopenko NN, Butyrlagin NV, Bugakova AV and Ignashin A. A. Method for speeding the micropower CMOS operational amplifiers with dual-input-stages // 2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), Batumi, 2017 , pp. 78-81.

30. Petrosyants KO, Ismail-zade MR, Sambursky LM, Dvornikov OV, Lvov BG and Kharitonov IA Automation of parameter extraction procedure for Si JFET SPICE model in the −200 ... + 110 ° C temperature range // 2018 Moscow Workshop on Electronic and Networking Technologies (MWENT), Moscow, 2018, pp. 1-5. DOI: 10.1109 / MWENT.2018.8337212

31. Creating low-temperature analog ICs for processing pulse signals from sensors. Part 2 / O. Dvornikov, V. Chekhovsky, V. Dyatlov, N. Prokopenko // Modern Electronics, 2015, No. 5. P. 24-28

32. Dvornikov O.V., Prokopenko N.N., Butyrlagin N.V. and Pakhomov I.V. The differential and differential difference operational amplifiers of sensor systems based on bipolar-field technological process AGAMC // 2016 International Siberian Conference on Control and Communications (SIBCON), Moscow, 2016, pp. 1-6. DOI: 10.1109 / SIBCON.2016.7491792

33. Dvornikov O.V., Chekhovsky V.A., Dyatlov V.L., Prokopenko N.N. Low-noise electronic signal processing module for avalanche photodiodes // Instruments and Methods of Measurement, No. 2 (7), 2013, pp. 42-46.

34. Dvornikov O. Chekhovsky V., Dyatlov V., Prokopenko N. Application of structural crystals to create sensor interfaces // Modern Electronics. - 2014. - No. 1. - S. 32-37.

35. Dvornikov OV, Bugakova AV, Prokopenko NN, Dziatlau VL and Pakhomov IV The microcircuits MH2XA010-02 / 03 for signal processing of optoelectronic sensors // 2017 18th International Conference of Young Specialists on Micro / Nanotechnologies and Electron Devices (EDM), Erlagol , 2017, pp. 396-402. DOI: 10.1109 / EDM.2017.7981781

Claims (2)

1. The differential cascade on complementary JFET field-effect transistors with increased attenuation of the input common mode signal, containing the first (1) and second (2) inputs of the device, the first (3) input field-effect transistor, the gate of which is connected to the first (1) input of the device, the drain is connected with the first (4) current output of the device, consistent with the first (5) bus of the power source, the second (6) input field-effect transistor, the gate of which is connected to the second (2) input of the device, and the drain is connected to the second (7) current output of the device, consistent with the first (5) power supply bus, and the sources of the first (3) and second (6) input field effect transistors are connected to each other, the third (8) input field effect transistor, the gate of which is connected to the first (1) input of the device, the drain is connected to the third (9) the current output of the device, consistent with the second (10) bus of the power source, the fourth (11) input field-effect transistor, the gate of which is connected to the second (2) input of the device, and the drain is connected to the fourth (12) current output of the device, matched with a second (10) power supply bus, and the sources of power the fifth (8) and fourth (11) input field effect transistors are connected to each other, characterized in that the first (13) additional field effect transistor is introduced into the circuit, the gate of which is connected to the combined sources of the first (3) and second (6) input field effect transistors , the drain is connected to the combined sources of the third (8) and fourth (11) input field effect transistors, and the source is connected to the combined sources of the first (3) and second (6) input field effect transistors through the first (14) auxiliary two-terminal device. 2. The differential cascade on complementary JFET field-effect transistors with increased attenuation of the input common-mode signal according to claim 1, characterized in that the second (20) additional field-effect transistor is introduced into the circuit, the gate of which is connected to the combined sources of the third (8) and fourth (11) input field-effect transistors, the drain is connected to the combined sources of the first (3) and second (6) input field-effect transistors, and the source is connected to the combined sources of the third (8) and fourth (11) input field-effect transistors through the second (21) auxiliary bipolar.

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