RU2684473C1 - Differential cascade on complementary field-effect transistors - Google Patents

Abstract

FIELD: radio equipment.SUBSTANCE: invention relates to radio engineering and communication and can be used as analogue signal amplification device, in structure of analogue microchips of various functional purpose, for example, operational amplifiers (OA), comparators, bridge power amplifiers, etc., incl. operating at low temperatures and exposure to radiation. Selection of additional resistors provides preset statistical mode for current in all field-effect transistors, which allows excluding traditional sources of reference current from DA circuit, which negatively affect these parameters during their construction.EFFECT: technical result consists in creation of conditions, in which in the declared differential amplifier (DA) is provided, higher stability of static mode of the DA at negative temperatures and change of supply voltages, possibility of varying the throughput characteristic restriction voltage (U) at developer's discretion (depending on preset SR values) at fixed static current consumption.1 cl, 13 dwg

Description

The invention relates to the field of radio engineering and communications and can be used as a device for amplifying analog signals in the structure of analog microcircuits for various functional purposes, for example, operational amplifiers (op amps), comparators, bridge power amplifiers, etc., incl. operating at low temperatures and exposure to radiation [1].

Known circuits of classical differential amplifiers (ДУ) on complementary transistors [2-28], including on complementary CMOS field-effect transistors [3-28] and complementary field-effect transistors with a pn junction control (JFet) [2], which became the basis of many serial analog microcircuits. In the literature on analog microelectronics, this class of DC has a special designation - dual-input-stage [29].

For operation at low temperatures with severe restrictions on the level of noise, the use of JFet field-effect transistors is promising [30-32]. DCs of this class are actively used in the structure of low-noise analog interfaces for processing sensor signals [33-35].

 The closest prototype (Fig. 1) of the claimed device is a differential cascade described in US patent 5.291.149, fig.4, 1994, which contains the first 1 input connected to the gate of the first 2 input field-effect transistor, the second 3 input connected to the gate the second 4 input field-effect transistor, the first 5 current output connected to the drain of the first 2 input field-effect transistor and matched to the first 6 bus of the power supply, the second 7 current output connected to the drain of the second 4 input field-effect transistor and matched to the first 6 power supply bus, third 8 input field-effect transistor, the drain of which is connected to the third 9 current output and matched with the second 10 bus of the power source, the fourth 11 input field-effect transistor, the drain of which is connected to the fourth 12 current output and matched with the second 10 bus of the power source, moreover, the channels of the first 2 and second 4 input field effect transistors have a first type of conductivity, and the channels of the third 8 and fourth 11 input field effect transistors have a different type of conductivity.

The first significant drawback of the known DC of FIG. 1 consists in the fact that the static mode of its input transistors is determined by two sources of the reference current I ₁ (I ₂ ), which, as a rule, are not identical. This becomes a source of additional errors when amplifying small signals. Secondly, in the known DC with a fixed current consumption, it is difficult to change the limiting voltage U _{gr of the} pass-through characteristic i _o = f (u _in ), which has a significant effect on the maximum slew rate of the output voltage (SR) of the operational amplifier with the input DC of FIG. 1 [36, 37]

, (1)

, (one)

where f ₁ is the frequency of unity gain of the adjusted op-amp with the input remote control of FIG. 1, as a rule, slightly dependent on U _gr .

This does not allow controlling the numerical values of SR in specific op amp circuits under given restrictions on current consumption, phase stability margin, voltage gain, etc.

The main objective of the alleged invention is to create conditions under which in the remote control of FIG. 1 is provided:

- higher stability of the static mode of the remote control at negative temperatures (up to -197 ° C) and changes in supply voltages (in comparison with the remote control of Fig. 1 based on classical sources of the reference current I ₁ , I ₂ );

- the ability to change the voltage limiting flow characteristics (U _gr ) at the discretion of the developer (depending on the set values of SR) with a fixed static current consumption.

The problem is solved in that in the differential cascade of FIG. 1, containing the first 1 input connected to the gate of the first 2 input field-effect transistor, the second 3 input connected to the gate of the second 4 input field-effect transistor, the first 5 current output connected to the drain of the first 2 input field-effect transistor and matched with the first 6 bus of the power supply , the second 7 current output connected to the drain of the second 4 input field-effect transistor and matched with the first 6 bus of the power supply, the third 8 input field-effect transistor, the drain of which is connected to the third 9 current output and matched with the second 10 bus power supply, the fourth 11 input field-effect transistor, the drain of which is connected to the fourth 12 current output and matched with the second 10 bus power supply, the channels of the first 2 and second 4 input field-effect transistors have the first type of conductivity, and the channels of the third 8 and fourth 11 input field-effect transistors have a different type of conductivity, new elements and connections are provided - between the sources of the third 8 and fourth 11 input field-effect transistors, the first 13 additional resistor is connected, between the source of the third 8 the input field-effect transistor and the source of the first 2 input field-effect transistor includes a second 14 additional resistor, between the source of the fourth 11 input field-effect transistor and the source of the second 4 input field-effect transistor the third 15 additional resistor is connected, and the source of the first 2 input field-effect transistor is connected to the gate of the fourth 11 input field-effect transistor transistor, and the source of the second 4 input field-effect transistor is connected to the gate of the third 8 input field-effect transistor.

In the drawing of FIG. 1 shows a diagram of a DC prototype, and in the drawing of FIG. 2 is a diagram of the claimed differential cascade on complementary field-effect transistors CJFET (OJSC Integral, Minsk) in accordance with claim 1.

In the drawing of FIG. 3 shows the static mode of the DC of FIG. 2 at t = 27ᵒC in LTSpice environment on CJFet models of transistors of Integral OJSC (Minsk).

In the drawing of FIG. 4 shows the static mode of the DC of FIG. 2 at
t = -197ᵒC in LTSpice environment on CJFet models of transistors of Integral OJSC (Minsk).

In the drawing of FIG. 5 shows the flow characteristics of the DC of FIG. 3 at a temperature of 27 ° C and different resistor resistances R3 * = 10/100 / 1k / 100k / 1MOhm for current outputs I _out1 , I _out2 , I _out3 , I _out4 with an input voltage V3 = V _in , varying within -5 ÷ 5V.

In the drawing of FIG. 6 shows the flow characteristics of the DC of FIG. 3 at a temperature of -197ᵒС and different resistances of the resistor R3 * = 10/100 / 1k / 100k / 1MOhm for current outputs I _out1 , I _out2 , I _out3 , I _out4 with an input voltage V3 = V _in , varying within -5 ÷ 5V .

In the drawing of FIG. Figure 7 shows the slope of the pass-through characteristic Gm for current outputs in the drain circuit of field-effect transistors J1, J2, J3, J4 DC fig. 2 at different temperatures t = -197 / -150 / -125 / -100 / -75 / -50 / -30 / 0/27/30 ° С.

In the drawing of FIG. 8 shows a diagram of the inventive differential cascade on complementary field effect transistors in accordance with paragraph 2 of the claims.

In the drawing of FIG. 9 shows the static mode of the DC of FIG. 8 at t = 27ᵒC in LTSpice medium on CJFet models of transistors of Integral OJSC (Minsk) with resistor R20 >> R13 (Fig. 8).

In the drawing of FIG. 10 shows the static mode of the DC of FIG. 8 at t = -197ᵒC in the LTSpice environment on CJFet models of transistors of Integral OJSC (Minsk) with the resistor R20 >> R13 (Fig. 8).

In the drawing of FIG. 11 shows the flow characteristics of the DC of FIG. 9 at a temperature of 27 ° C and different resistor resistances R3 * = 100 / 1k / 100k / 1Mohm for current outputs I _out1 , I _out2 , I _out3 , I _out4 with an input voltage V3 = V _in , varying within -5 ÷ 5V and the resistance of the resistor R20 >> R13 (Fig. 8).

In the drawing of FIG. 12 shows the flow characteristics of the DC of FIG. 8 at a temperature of -197ᵒС and different resistances of the resistor R3 * = 100 / 1k / 100k / 1MOhm for current outputs I _out1 , I _out2 , I _out3 , I _out4 with an input voltage V3 = V _in , varying within -5 ÷ 5V and resistance resistor R20 >> R13 (Fig. 8)

In the drawing of FIG. 13 shows the slope of the passage characteristic Gm for current outputs in the drain circuit of field effect transistors J1, J2 and J3, J4 of the DC of FIG. 9 at different temperatures t = -197 / -150 / -125 / -100 / -75 / -50 / -30 / 0/27/30 ° С.

The differential cascade on the complementary field effect transistors of FIG. 2 contains a first 1 input connected to a gate of a first 2 input field-effect transistor, a second 3 input connected to a gate of a second 4 input field-effect transistor, a first 5 current output connected to a drain of a first 2 input field-effect transistor and matched with a first 6 power supply bus, the second 7 current output connected to the drain of the second 4 input field-effect transistor and matched with the first 6 bus of the power supply, the third 8 input field-effect transistor, the drain of which is connected to the third 9 current output and matched with w a second 10 bus power supply, the fourth 11 input field-effect transistor, the drain of which is connected to the fourth 12 current output and matched with the second 10 bus power supply, the channels of the first 2 and second 4 input field-effect transistors have the first type of conductivity, and the channels of the third 8 and fourth 11 input field effect transistors have a different type of conductivity. Between the sources of the third 8 and fourth 11 input field-effect transistors, the first 13 additional resistor is connected, between the source of the third 8 input field-effect transistor and the source of the first 2 input field-effect transistor, the second 14 additional resistor is connected, between the source of the fourth 11 input field-effect transistor and the source of the second 4 input field-effect transistor the third 15 additional resistor is turned on, the source of the first 2 input field-effect transistor connected to the gate of the fourth 11 input field-effect transistor, and the source of the second about 4 input field-effect transistor is connected to the gate of the third 8 input field-effect transistor.

In the drawing of FIG. 2, the corresponding bipolar terminals 16, 17, 18, 19 are shown as load elements of the first 5, second 7, third 9, and fourth 12 current outputs of the DC. In a particular case, for example, in an operational amplifier based on the claimed DC, these can be input resistances of classical current mirrors.

In the drawing of FIG. 8, in accordance with paragraph 2 of the claims, a fourth 20 additional resistor is connected between the gates of the third 8 and fourth 11 input field-effect transistors.

Consider the operation of the remote control of FIG. 2.

In static mode, for example, when connecting the first 1 and second 3 inputs of the DC of FIG. 2 to the common bus of power supplies (6 and 10), the first 13 additional resistor does not affect the static currents of the source of all field-effect transistors of the circuit due to its symmetry. Wherein

, (2)

, (2)

, (3)

, (3)

, (4)

, (four)

, (5)

, (5)

where I and _i - drain current of the i-th field-effect transistor;

U _zi.8 , U _zi.11 - gate-source voltage of the corresponding third 8 and fourth 11 input field-effect transistors at the operating point with a source current equal to I ₀ ;

U _R14 = U _R15 - voltage drop at the second 14 and third 15 additional resistors from the current I ₀ .

Thus, by selecting the second 14 and third 15 additional resistors, an identical predetermined static current mode of all field effect transistors 2, 4, 8, 11 of the DC of FIG. 2:

. (6)

. (6)

It should be noted that the static mode of the DC of FIG. 2 practically does not depend on the value of the input common-mode signal and changes in the supply voltages on the first 6 and second 10 buses. This makes it possible to exclude from the circuit DC of FIG. 2 traditional sources of the reference current (I ₁ , I ₂ , Fig. 1), negatively affecting these parameters during their simplest construction.

If the input terminal 1 is supplied a positive input voltage with respect to input u _Rin 3, this causes an increase in current through the first resistor and a further decrease of the current source 4 and the second input 11 of the fourth field-effect transistors. In the limit, the source current of the first 2 input field-effect transistor can take a double value relative to its static level at u _in = 0. The numerical values of the resistances of the second 14 and third 15 additional resistors determine the voltage limiting the pass-through characteristic of the DC of FIG. 2: the greater the resistance of the additional resistors R14 = R15, the higher the input voltage u _in = U _g , the output current of the DC will be limited for the first 5 current output. The graphs of FIG. 4, FIG. 5, FIG. 6 obtained for the circuit of FIG. 2.

Similarly, to the voltage limiting U _gr DC of FIG. 8 affects the fourth 20 additional resistor. The lower its resistance, the lower the input voltage u _in = U _{g the} output current limitation of the DC of FIG. 8 for the first 5 current output (Fig. 11, Fig. 12), as well as other current outputs (7, 9, 12).

Thus, the first 13 and fourth 20 additional resistors determine the numerical values of the voltage limiting U _{g of the} proposed differential amplifier for all its current outputs 5, 7, 9, 12.

The graphs shown in the drawings of FIG. 5, FIG. 6, FIG. 11, FIG. 12, taken at different temperatures and numerical values of the resistances of the first 13 and fourth 20 additional resistors confirm the above qualitative conclusions.

The results of computer simulation in the LTspice environment of DC circuits of FIG. 3 and FIG. 8 show that, based on the proposed DC, a wide range of pass-through characteristics is realized with different numerical values of the limiting voltage U _gr for the first 5 and second 7 current outputs matched with the first 6 bus of the power supply, and the third 9 and fourth 12 current outputs matched with the second 10 bus power supply. As a result, this allows us to design differential and multidifferential operational amplifiers with a given speed (see formula (1)).

The graphs of FIG. 7 and FIG. 13 characterize the temperature dependence of the slope of the flow characteristic of the DC of FIG. 3 and DK of FIG. 8, which determines the differential voltage gain in practical op-amp circuits based on the proposed DCs.

Thus, the claimed device has significant advantages in comparison with the well-known circuitry solutions of a dual-input-stage class DC [2-28], which allows us to recommend it for practical use in various op-amps and construction of low-temperature and radiation-resistant analog microcircuits using the CJFet OJSC technological process Integral (Minsk), as well as a complementary field technological process of NPP Pulsar JSC (Moscow).

Bibliographic list

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Claims (2)

1. A differential cascade on complementary field-effect transistors, comprising a first (1) input connected to a gate of a first (2) input field-effect transistor, a second (3) input connected to a gate of a second (4) input field-effect transistor, a first (5) current output connected to the drain of the first (2) input field-effect transistor and matched to the first (6) power supply bus, a second (7) current output connected to the drain of the second (4) input field-effect transistor and matched to the first (6) power supply bus, third (8) input field a transistor whose drain is connected to a third (9) current output and matched to a second (10) power supply bus, a fourth (11) input field-effect transistor whose drain is connected to a fourth (12) current output and matched to a second (10) source bus power supply, and the channels of the first (2) and second (4) input field effect transistors have the first type of conductivity, and the channels of the third (8) and fourth (11) input field effect transistors have a different type of conductivity, characterized in that between the sources of the third (8) and fourth (11) input field transi of tori, the first (13) additional resistor is connected, between the source of the third (8) input field-effect transistor and the source of the first (2) input field-effect transistor, the second (14) additional resistor is connected, between the source of the fourth (11) input field-effect transistor and the source of the second (4) the input field-effect transistor includes a third (15) additional resistor, the source of the first (2) input field-effect transistor connected to the gate of the fourth (11) input field-effect transistor, and the source of the second (4) input field-effect transistor connected to the gate third (8) input field effect transistor. 2. The differential cascade on complementary field-effect transistors according to claim 1, characterized in that a fourth (20) additional resistor is connected between the gates of the third (8) and fourth (11) input field-effect transistors.

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