RU2416149C1 - Differential operating amplifier with low zero offset voltage - Google Patents

Abstract

FIELD: radio engineering.

SUBSTANCE: differential operating amplifier with low zero offset voltage includes the first (1) input differential cascade (DC) with the first (2) and the second (3) current outputs, the first (4) current mirror (CM) the input of which is connected to the first (2) current output of the first DC (1), and output is connected to input of buffer amplifier (5) and to source of pedestal current (6), emitter output of the first CM (4) is connected to bus of power supply (7). To the diagram there introduced is the second (8) input DC, the first (9) current output of which is connected to input of the second CM (10), and the second (11) current output is connected to input of the first CM (4) and to output of the second CM (10) and base of additional transistor (12) the emitter of which is connected to the second (3) current output of the first DC (1), and collector is connected to bus of power supply (7).

EFFECT: decreasing absolute value U_offset, its temperature and radiation drift at using current mirrors in the diagram.

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Description

The invention relates to the field of radio engineering and communication and can be used as a device for amplifying analog signals in the structure of analog microcircuits for various functional purposes (for example, in comparators and solving amplifiers with small values of the emf of zero bias).

In modern electronic equipment, differential operational amplifiers (op amps) with significant different parameters are used.

A special place is occupied by differential operational amplifiers (op amps) with asymmetric inclusion of an active load (current mirror), which provides direct control of a push-pull buffer amplifier (BU). Such op-amps have an important quality - they have a so-called rail-to-rail output (“from the power bus to the power bus”) and an extremely simple structure. However, op-amps of this class [1–11] have so far been used only in devices with low requirements for stability of the zero level, since their zero bias voltage varies by units or tens of millivolts.

The closest in essence to the claimed technical solution is the classical scheme of the op-amp of Fig. 1, presented in US patent No. 4.415.868, fig. 3, which is also present in a large number of other patents and monographs, for example [1-11], which have current mirrors with asymmetrical inclusion as a load circuit of the input transistors (with respect to the input stage).

A significant drawback of the known op-amp of FIG. 1 is that it has an increased value of the systematic component of the zero bias voltage (U _cm ), which depends on the current transmission error (K _i ) of the current mirror used. This error is especially significant when using the simplest but most high-frequency circuitry solutions for which K _i ≠ 1 as a current mirror.

The main task of the invention is to reduce the absolute value of U _cm , as well as its temperature and radiation drift when using current mirrors in the circuit having a current transfer coefficient not equal to unity K _i ≠ 1. Such a value of K _{i is} characteristic of many classical current mirrors.

The problem is achieved in that in a differential operational amplifier containing the first 1 input differential stage with the first 2 and second 3 current outputs, the first 4 current mirror, the input of which is connected to the first 2 current output of the first 1 input differential stage, and the output is connected to the input buffer amplifier 5 and a reference current source 6, the emitter output of the first 4 current mirrors is connected to the bus of the power source 7, new elements and connections are provided - the second 8 input differential helmet is introduced into the circuit e, the first 9 current output of which is connected to the input of the second 10 current mirror, and the second 11 current output is connected to the input of the first 4 current mirror and the base of the additional transistor 12, the emitter of which is connected to the second 3 current output of the first 1 of the input differential stage, and the collector is connected to the bus of the power source 7.

The amplifier circuit of the prototype is shown in figure 1. Figure 2 presents a diagram of the inventive device corresponding to the claims.

Figure 3 and figure 4 shows a diagram of an op-amp prototype (figure 3) and the claimed op-amp (figure 4) in a computer simulation environment PSpice on models of integrated transistors of FSUE NPP Pulsar.

Figure 5 shows the dependence of the bias voltage of the prototype and the claimed circuit from the current transfer coefficient K _{i of} current mirrors 4 and 10 K _i = K _i12.4 = K _i12.10 .

Figure 6 shows the temperature dependence of the voltage module of the zero bias circuit of figure 4.

The inventive differential operational amplifier contains a first 1 input differential stage with a first 2 and second 3 current outputs, a first 4 current mirror, the input of which is connected to the first 2 current output of the first 1 input differential stage, and the output is connected to the input of the buffer amplifier 5 and the reference current source 6, the emitter output of the first 4 current mirror is connected to the bus of the power source 7. A second 8 input differential stage is introduced into the circuit, the first 9 current output of which is connected to the input of the second 10 current the mirror, and the second 11 current output is connected to the input of the first 4 current mirror and connected to the output of the second 10 current mirror and the base of the additional transistor 12, the emitter of which is connected to the second 3 current output of the first 1 input differential stage, and the collector is connected to the bus of the power source 7 .

The first 1 and second 8 input differential stages in the circuit of figure 2 are implemented respectively on transistors 13, 14, two-terminal 15, as well as on transistors 16, 17 and two-terminal 18.

Consider the factors that determine the systematic component of the bias voltage zero (U _cm ) in the circuit of figure 2, i.e. circuit-dependent op amps.

If the currents of two-terminal circuits 15 and 18 of the first 1 and second 8 input differential stages are 2I ₀ , and the current of the reference current source 6 is equal to I ₀ , then the collector currents of the transistors 13, 14, 16, 17 of the first 1 and second 8 input differential stages are determined ratios:

where I _bp = I ₀ / β _i is the base current of the i-th npn transistor of the circuit at the emitter current I _e = I ₀ ,

β _i is the current gain of the base of the i-th transistor.

The output current of the second 10 current mirror is defined as

where I _p10 is the difference of the currents at the output and input of the second 10 current mirrors, depending on its circuitry.

Therefore, on the basis of Kirchhoff’s law at node A ₁ , the following current relation holds

As a result, the currents at the input and output of the first 4 current mirrors are determined by the formulas:

where I _p4 is the current difference at the input and output of the first 4 current mirrors, depending on its circuitry.

Since the current mirrors 4 and 10 are made using identical circuitry solutions, the difference in their error currents I _p is zero. Therefore, the differential current I _∑ in the node "A" with its short circuit to the equipotential common bus at I _BU ≈ 0 will be equal to zero:

Thus, in the inventive device, when condition (6) is fulfilled, the systematic component U _cm decreases due to the final value of β transistors and its radiation (or temperature) dependence. As a result, this reduces U _cm , since the differential current I _∑ in the node “A” creates U _cm , which depends on the steepness S of the conversion of the input differential voltage u _in to the differential current of the node “A”:

where r _e13 = r _e14 - the resistance of the emitter junctions of the input transistors 13 and 14 of the first 1 input differential stage.

Therefore, for the circuit of FIG. 2, a bias voltage of zero

where φ _t = 26 mV is the temperature potential.

In the op-amp prototype, I _∑ ≠ 0. Therefore, here the systematic component of U _{cm is} obtained at least an order of magnitude more than in the claimed scheme.

Computer simulation of the circuits of figure 3, figure 4 confirms (figure 5, figure 6) these theoretical conclusions.

Despite a significant decrease in β transistors due to radiation and thermal effects, the proposed op-amp also has a lower zero bias voltage under these conditions than the op-amp.

In some cases, in the claimed op-amp, the inputs of the second 8 input differential cascade can be used (Vkh. ^(-) 3, Vkh. ⁽⁺⁾ 4), which makes it possible to implement on its basis the so-called multidifferential op-amps, which have great prospects for use in microcircuitry.

Thus, the claimed device has significant advantages compared to the prototype in terms of the value of the static error of amplification of DC signals and can be used as IP modules of modern systems on a chip.

BIBLIOGRAPHIC LIST

1. US patent No. 4.415.868, fig. 3.

2. Germany patent No. 2928841, fig.3.

3. Japan Patent JP 54-34589, CL 98 (5) A014.

4. Japanese Patent JP 154-10221, CL H03F 3/45.

5. Japan patent JP 54-102949, cl. 98 (5) A21.

6. US patent No. 4.366.442, fig.2.

7. US patent No. 6.426.678.

8. US Patent Application 2007/0152753, fig.5c.

9. US Patent No. 6,531,920, fig. 4.

10. US patent No. 4.262.261.

11. Ezhkov Yu.A. Handbook of amplifier circuitry. - 2nd ed., Revised. - M .: IP RadioSoft, 2002 .-- 272 p. - Fig. 9.3 (p. 235).

Claims (1)

A differential operational amplifier with a low zero bias voltage, containing the first (1) input differential stage with the first (2) and second (3) current outputs, the first (4) current mirror, the input of which is connected to the first (2) current output of the first (1 ) of the input differential stage, and the output is connected to the input of the buffer amplifier (5) and the reference current source (6), the emitter output of the first (4) current mirror is connected to the bus of the power source (7), characterized in that the second (8 ) input differential stage, first (9) t whose output is connected to the input of the second (10) current mirror, and the second (11) current output is connected to the input of the first (4) current mirror and connected to the output of the second (10) current mirror and the base of the additional transistor (12), the emitter of which is connected to the second (3) current output of the first (1) input differential stage, and the collector is connected to the bus of the power source (7).

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