RU2402155C1 - Differential amplifier with low voltage of zero shift - Google Patents

Abstract

FIELD: radio engineering. ^ SUBSTANCE: differential amplifier comprises input parallel-balance cascade (PBC) (1) with the first (2) and second (3) current outputs, current mirror (4), input of which is connected to the first (2) current output of input PBC (1), and output is connected to the second (3) current output of input PBC (1) and base of input transistor (T) (5) of output buffer amplifier, T (6) of reference current source, collector of which is connected to output of device (7) and is connected to emitter of input T (5), and emitter is connected to the first bus (8) of supply source. Base T (6) of reference current source is connected to input of current mirror (4) via additional circuit of potentials matching (9), and emitter T (6) of reference current source is connected to the first bus (8) of supply source via additional current-stabilising dipole (10). ^ EFFECT: reduced absolute value of shift voltage and its temperature drift. ^ 10 dwg

Description

The invention relates to the field of radio engineering and communication and can be used as a device for amplifying analog signals in the structure of analog microcircuits for various functional purposes (for example, in comparators and precision operational amplifiers (op amps) with small values of the emf of zero bias).

In modern electronic equipment, differential amplifiers (DU) with significant different parameters are used. A special place is occupied by remote controls with the simplest two-stage architecture, containing a small number of elements. On their basis, for example, various classes of selective circuits are performed, where the number of low-power amplifiers can be measured in tens of units. The present invention relates to this type of remote control.

The closest in essence to the claimed technical solution is the classic scheme DU of figure 1, presented in US patent No. 4629997, fig.4, which is also present in a large number of other patents [1-23].

A significant drawback of the known DE of FIG. 1 is that it has an increased value of the systematic component of the zero bias voltage (U _cm ), which depends on the properties of its architecture.

The main objective of the invention is to reduce the absolute value of U _cm and its temperature drift.

This goal is achieved by the fact that in the differential amplifier of figure 1, containing the input parallel-balanced stage 1 with the first 2 and second 3 current outputs, the current mirror 4, the input of which is connected to the first 2 current output of the input parallel-balanced stage 1, and the output connected to the second 3 current output of the input parallel-balanced stage 1 and the base of the second transistor 5 of the output buffer amplifier, the transistor 6 of the reference current source, the collector of which is connected to the output of the device 7 and connected to the input emitter transistor 5 of the output buffer amplifier, and the emitter is connected to the first 8 bus of the power supply, new elements and connections are provided - the base of the transistor 6 of the reference current source is connected to the input of the current mirror 4 through an additional potential matching circuit 9, and the emitter of the transistor 6 of the reference current source is connected to bus power source 8 through an additional current-stabilizing two-terminal 10.

The amplifier circuit of the prototype is shown in the drawing of figure 1. The drawing of figure 2 presents a diagram of the inventive device in accordance with the claims. In the drawings of Fig.3 - Fig.5 shows particular cases of execution of the matching circuit potentials 9.

In the drawing of Fig.6 shows a diagram of a differential amplifier - a prototype, and in the drawing of Fig.7 - of the claimed remote control in a computer simulation environment PSpice on models of integrated transistors of FSUE NPP Pulsar.

The drawing of Fig.8 shows the temperature dependence of the voltage of the zero bias circuit of Fig.6 - Fig.7.

The drawing of Fig. 9 shows the upgraded circuit of Fig. 7 in the computer simulation environment PSpice on models of integrated transistors of the Federal State Unitary Enterprise NPP "Pulsar", into which an additional transistor of thermo-radiation compensation VT11 is introduced, and in the drawing of Fig. 10 - the dependence of the zero bias voltage on the temperature of the circuit of Fig. .6 (prototype) and the circuit of FIG. 9.

The differential amplifier of figure 2 contains an input parallel-balanced cascade 1 with first 2 and second 3 current outputs, a current mirror 4, the input of which is connected to the first 2 current output of the input parallel-balanced stage 1, and the output is connected to the second 3 current output of the input parallel -balance stage 1 and the base of the second transistor 5 of the output buffer amplifier, the transistor 6 of the reference current source, the collector of which is connected to the output of the device 7 and connected to the emitter of the input transistor 5 of the output buffer amplifier , and the emitter is connected to the first 8 bus power supply. The base of the transistor 6 of the reference current source is connected to the input of the current mirror 4 through an additional potential matching circuit 9, and the emitter of the transistor 6 of the reference current source is connected to the bus of the power source 8 through an additional current-stabilizing two-terminal 10.

Consider the factors that determine the systematic component of the bias voltage of zero U _cm in the circuit of figure 2, i.e. depending on the circuitry of the remote control.

As a subcircuit 1, various cascades can be used - on field-effect transistors, with different construction of stabilization circuits of the static mode. We assume that the currents of outputs 2 and 3 are the same and equal in magnitude to the current I ₀ :

In this case, the current of the two-terminal 10

where n is the coefficient of proportionality.

In this regard, the base currents of transistors 5 and 6

where I _bp = I _e.i / β _i , is the base current of npn transistors 4, 5, 13, 14, 10 with an emitter current I _e.i = I ₀ ;

β _i is the current gain of the base npn of the transistor;

m is the coefficient of proportionality.

When the current transfer coefficient of the potential matching circuit is 9 K _i, its output current

Therefore, the output current of the current mirror 4

As a result, the current difference in the node "A" when it is shorted to the equipotential common bus

where I _BU = mI _bp is the base current of the npn transistor 5.

Substituting (2) ÷ (6) in (7), we find that the difference current determining U _cm

As a result, at I _p = 0, zero offset DN1 of FIG. 2 is not required by U _cm , the supply of which to its inputs Bx. ⁽⁺⁾ 1, Bx. ^(-) 2 compensates for the differential current I _p in the node "A".

To obtain I _p = 0, the coefficients n, m and K _i must satisfy the condition

In the first particular case (n = m = 1) should be

For m = 1, n = 2, the current transfer coefficient

In the first (10) case, it is necessary to use the circuit of figure 3 or figure 4. In the second (11) - diagram of figure 5.

Thus, in the inventive device, the systematic component U _cm decreases due to the final value of β transistors and its radiation (or temperature) dependence. As a result, this reduces U _cm , since the difference current I _p in the node “A” creates U _cm , which depends on the steepness of the conversion S of the input differential voltage u _{in the} remote control into the output current of the node “A”:

In the particular case (figure 2):

where r _e11 = r _e12 are the resistance of the emitter junctions of the input transistors 11 and 12 of the differential stage 1.

Therefore, for the private circuit of figure 2

where φ _t = 26 mV is the temperature potential.

In the remote control prototype (Fig. 1) I _p ≠ 0, therefore, here the systematic component U _{cm is} obtained by an order of magnitude greater (U _cm = -1.2 mV) than in the claimed circuit U _cm = 64 μV, (Fig. 8) )

Computer simulation of the circuits of Fig.6 - Fig.7 confirms (Fig.8) these theoretical conclusions.

If it is necessary to ensure symmetry of the amplitudes of the positive and negative half-waves of the output voltage of the remote control of FIG. 2, then auxiliary bias circuits of potentials V4 and V1 should be introduced (FIG. 6).

To minimize U _cm at elevated temperatures (t °> 80 ° C), the transistor VT11 is provided in the circuit of Fig. 9, which is in the closed state. However, the current through its pn junction to the substrate, which increases significantly at high temperatures (or when exposed to radiation), compensates for the corresponding current to the substrate through the pn junction of the VT8 transistor. This reduces the derivative dU _cm / dT at t °> 80 ° C (Fig. 10). With high-quality technical processes, the need for the introduction of thermoradiation compensation transistors disappears.

Thus, the claimed device has significant advantages in comparison with the prototype in terms of the value of the static error of amplification of DC signals.

Information sources

1. US patent No. 4042886.

2. Japan patent JP 10032437.

3. Japan patent JP 2005033558.

4. US patent No. 4595883, fig. 4.

5. US patent application No. 2005/0063270A1, fig.2.

6. US patent No. 5166638, fig. 1.

7. US Patent No. 5537081, fig. 3.

8. US patent No. 6114904.

9. French Patent FR No. 2227574, fig. 1, fig. 3b, fig. 4b.

10. Integrated circuits. Operational Amplifiers [Text]: Reference. - M., Dodeka-XXI Publishing House, 2001. - P.159, operational amplifiers 574UDZ.

11. Integrated circuits. Operational Amplifiers [Text]: Reference. - M., Dodleka-XXI Publishing House, 2001. - P.280, operational amplifiers 1407UD3, 1416UD1.

12. US Patent No. 5365191, fig. 9.

13. US patent No. 5568090.

14. US patent No. 4629997.

15. US Patent Application 2009/0021306, fig. 2.

16. US patent No. 4223276, fig. 1, fig. 2.

17. US Patent Application 2008/0061877, fig. 6.

18. US Patent Application 2006/0202761.

19. U.S. Patent No. 4,338,527, fig. 3.

20. Japan Patent 54-37561 H03F 3/45, fig. 2, fig. 4.

21. Japan patent 54004131.

22. U.S. Patent No. 5,144,259, fig. 1.

23. US patent No. 6922105, fig. 7.

Claims (1)

A differential amplifier with a low zero bias voltage, containing an input parallel-balanced stage (1) with the first (2) and second (3) current outputs, a current mirror (4), the input of which is connected to the first (2) current output of the parallel-balanced input stage (1), and the output is connected to the second (3) current output of the input parallel-balanced stage (1) and the base of the input transistor (5) of the output buffer amplifier, the transistor (6) of the reference current source, the collector of which is connected to the output of the device (7 ) and is connected to the input emitter transistor (5) of the output buffer amplifier, and the emitter is connected to the first (8) bus of the power source, characterized in that the base of the transistor (6) of the reference current source is connected to the input of the current mirror (4) through an additional potential matching circuit (9), and the emitter of the transistor (6) of the reference current source is connected to the bus of the power source (8) through an additional current-stabilizing two-terminal device (10).

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