RU2411644C1 - Complementary differential amplifier - Google Patents

Abstract

FIELD: radio engineering.

SUBSTANCE: amplifier comprises the first (1) input parallel-balance cascade (PBC) on p-n-p transistors (T) and the second (2) PBC on n-p-n T parallel-connected by differential input, the first (3) current-stabilising dipole (CD) in common emitter circuit (4) of the first (1) input PBC, the second (5) CD in common emitter circuit (6) of the second (2) input PBC, the first (7) current mirror (CM), input of which is connected to current output (8) of the second (2) PBC, and output is connected to high-impedance output (9) of device, the second (10) CM, input of which is connected to current input (11) of the first (1) PBC, and output is connected to high-impedance output (9) of device, buffer amplifier (12), input of which is connected to high-impedance output (9) of device, and output is low-impedance output of device. Circuit comprises the first (13) and second (14) additional T, emitter of the first T (13) is connected to the first (3) CD, collector is connected to the common emitter circuit (4) of the first (1) PBC, and base via the first (15) non-inverting current repeater (CR) is connected to input of the second (10) CM, emitter of the second T (14) is connected to the second (5) CD, collector is connected to common emitter circuit (6) of the second (2) PBC, and base via the second (16) non-inverting CR is connected to input of the first (7) CR.

EFFECT: reduced absolute value of U_cm and its temperature drift.

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Description

The invention relates to the field of radio engineering and communication and can be used as a device for amplifying analog signals in the structure of analog microcircuits for various functional purposes (for example, in precision operational amplifiers (op amps), comparators, etc.).

Known schemes for complementary differential amplifiers (KDUs) based on two parallel-connected differential stages (DC) with current-stabilizing two-terminal circuits in the emitter circuits of input transistors (the so-called "dual input stage") and output stages performed on current repeaters. KDU with such an architecture became the basis for the construction of many modern operational amplifiers [1-15], including Op-amps with a rail-to-rail option having a maximum output voltage amplitude close to the supply voltage.

The closest prototype (figure 1, figure 2) of the inventive device is a complementary differential amplifier described in US patent No. 5.291.149, fig. 3, containing the first 1 input parallel-balanced cascade on pnp transistors and connected in parallel to it via the differential input, the second 2 input parallel-balanced cascade on npn transistors, the first 3 current-stabilizing two-terminal in a common emitter circuit 4 of the first 1 input parallel-balanced cascade on pnp transistors , the second 5 current-stabilizing two-terminal in the common emitter circuit 6 of the second 2 input parallel-balanced cascade on npn transistors, the first 7 current mirror, the input of which is connected to the current output m 8 of the second 2 input parallel-balanced cascade on npn transistors, and the output is connected to the high-impedance output 9 of the device, the second 10 current mirror, the input of which is connected to the current output 11 of the first 1 input parallel-balanced cascade on pnp transistors, and the output is connected to the high-impedance the output 9 of the device, a buffer amplifier 12, the input of which is connected to the high-impedance output 9 of the device, and the output is a low-impedance output of the device.

A significant drawback of the known remote control (Fig. 1) is that it has an increased value of the systematic component of the zero bias voltage (U _cm ), which depends on the properties of its architecture.

The main objective of the proposed invention is to reduce the absolute value of U _cm and its temperature drift.

The problem is achieved in that in the differential amplifier (figure 1, figure 2), containing the first 1 input parallel-balanced cascade on pnp transistors and connected in parallel to it on the differential input of the second 2 input parallel-balanced cascade on npn transistors, the first 3 current-stabilizing two-terminal in the common emitter circuit 4 of the first 1 input parallel-balanced cascade on pnp transistors, the second 5 current-stabilizing two-terminal in the common emitter circuit 6 of the second 2 input parallel-balanced cascade on npn transistors, the first 7 current mirror, the input of which is connected to the current output 8 of the second 2 input parallel-balanced cascade on npn transistors, and the output is connected to the high-impedance output 9 of the device, the second 10 current mirror, the input of which is connected to the current output 11 of the first 1 input parallel-balanced cascade on pnp transistors, and the output is connected to the high-impedance output 9 of the device, a buffer amplifier 12, the input of which is connected to the high-impedance output 9 of the device, and the output is a low-impedance output three new elements and connections are provided - the first 13 and second 14 additional transistors are introduced into the circuit, the emitter of the first 13 additional transistor is connected to the first 3 current-stabilizing two-terminal, the collector is connected to a common emitter circuit 4 of the first 1 input parallel-balanced cascade on pnp transistors, and the base through the first 15 non-inverting current repeater is connected to the input of the second 10 current mirror, the emitter of the second 14 additional transistor is connected to the second 5 current-stabilizing two-pole speaker connected to the common emitter circuit 6 of the second 2-input parallel balanced stage to n-p-n transistor and the base 16 through a second non-inverting current follower connected to the input 7 of the first current mirror.

A circuit of a known complementary differential amplifier is shown in FIG. Figure 2 shows the functional diagram of the CDA of figure 1.

Figure 3 presents a diagram of the inventive device in accordance with the claims.

Figure 4 shows a diagram of the inventive device of figure 3 with a specific implementation of the main functional units 1, 2, 15 and 16. As current mirrors 7 and 10, it is advisable to use the classic Wilson current mirrors.

Figures 5 and 6 show the schemes of a differential amplifier - a prototype (Fig. 5) and the claimed KDU (Fig. 6) in a computer simulation environment PSpice on models of integrated transistors of the Federal State Unitary Enterprise NPP Pulsar.

Figure 7 shows the temperature dependence of the zero bias voltage of the circuits of Fig.5, Fig.6.

The complementary differential amplifier of figure 2 contains the first 1 input parallel-balanced cascade on pnp transistors and a parallel 2 parallel input-balanced cascade on npn transistors, the first 3 current-stabilizing two-terminal in the common emitter circuit 4 of the first 1 input parallel-balanced cascade on pnp transistors, the second 5 current-stabilizing two-terminal in the common emitter circuit 6 of the second 2 input parallel-balanced cascade on npn transistors, the first 7 current a speaker whose input is connected to the current output 8 of the second 2 input parallel-balanced cascade on npn transistors, and the output is connected to the high-impedance output 9 of the device, the second 10 current mirror, the input of which is connected to the current output 11 of the first 1 input parallel-balanced cascade on pnp transistors, and the output is connected to the high-impedance output 9 of the device, a buffer amplifier 12, the input of which is connected to the high-impedance output 9 of the device, and the output is the low-impedance output of the device. The first 13 and second 14 additional transistors are introduced into the circuit, the emitter of the first 13 additional transistor is connected to the first 3 current-stabilizing bipolar, the collector is connected to the common emitter circuit 4 of the first 1 input parallel-balanced cascade on pnp transistors, and the base is connected through the first 15 non-inverting current repeater with the input of the second 10 current mirror, the emitter of the second 14 additional transistor is connected to the second 5 current-stabilizing two-pole, the collector is connected to a common emitter circuit 6 second about 2 parallel input-balanced stage to n-p-n transistor and the base 16 through a second non-inverting current follower connected to the input 7 of the first current mirror.

As non-inverting current repeaters 15 and 16, the authors recommend using cascades with a common base (transistors 21, 22 in the KDU of figure 4) or passive two-terminal devices (for example, zener diodes).

Current mirrors 7 and 10 can be made on the basis of precision Wilson current mirrors.

The buffer amplifier is implemented on the basis of classical architectures with low input currents.

Consider the factors determining the systematic component of the bias voltage of zero U _cm in the circuit of figure 3, i.e. depending on the circuitry of the CDU.

If the currents of the two-terminal circuits 5 and 3 are equal to 2I ₀ , then the collector currents (I _k.i ) and the base (I _b.i ) of the transistors of the circuit, as well as the currents of the outputs 8 and 11:

where I _b.i = I _e.i / β _i is the base current npn (I _b.p ) or pnp (I _b.n ) of the transistors of the circuit at their emitter current I _e.i = I ₀ ;

β _i is the current gain of the base of the i-th transistor.

Input (I _Rin) and output (I _out) the currents of the current mirrors 7 and 10:

where K _i = 1 - module of the current transfer coefficient of non-inverting current repeaters 15 and 16;

To _i12 = 1 is the current transfer coefficient module of current mirrors 7 and 10.

As a result, the current difference in node “A” when it is short-circuited to an equipotential common bus

where I _BU ≈0 is the input current of the buffer amplifier 12.

Substituting (1) ÷ (10) into (11), we find that the difference current determining U _{cm of the} CDD is zero: I _p = 0.

As a result, this reduces U _cm , since the differential current I _p in the node “A” creates U _cm , which depends on the steepness S of the conversion of the input differential voltage u _{in the} remote control into the output current of the node “A”:

where r _e18 = r _e19 = r _e17 = r _e20 are the resistance of the emitter junctions of the transistors 17, 18, 19, 20 (for KDU figure 4).

Therefore, for the circuit of FIG. 3 to FIG. 4, the systematic component U _cm is close to zero:

where φ _t = 26 mV is the temperature potential.

In the CDA prototype I _p ≠ 0, therefore, here the systematic component U _{cm is} obtained more than an order of magnitude more than in the claimed scheme (Fig. 7).

Computer simulation of the circuits of Fig.5, Fig.6 confirms (Fig.7) these theoretical conclusions.

Thus, the claimed device has significant advantages in comparison with the prototype in terms of the value of the static error of amplification of DC signals.

Bibliographic list

1. US Patent No. 5.291.149 fig. 3

2. US Patent No. 4,595.883

3. US Patent No. 5.225.791

4. US Patent No. 3,974.455

5. US Patent No. 4,783.637

6. A. St. USSR 611288

7. French Patent No. 2224932

8. US Patent No. 3,968.451

9. US Patent No. 5,512.859

10. US Patent No. 6,268.769 fig.3

11. US Patent No. 5,515.005

12. US Patent Application No. 2005/0024140 A1

13. Japanese patent JP 7050528

14. Patent WO 98/0091

15. US Patent No. 4,757.273 fig.22

Claims (1)

A complementary differential amplifier containing the first (1) input parallel-balanced cascade on pn-p transistors and connected in parallel to it through the differential input of the second (2) input parallel-balanced cascade on npn transistors, the first (3) current-stabilizing two-terminal in a common emitter circuit ( 4) the first (1) input parallel-balanced cascade on pnp transistors, the second (5) current-stabilizing two-terminal in a common emitter circuit (6) the second (2) input parallel-balanced cascade on npn transistors, the first (7) a current mirror, the input of which is connected to the current output (8) of the second (2) input parallel-balanced cascade on npn transistors, and the output is connected to the high-impedance output (9) of the device, the second (10) current mirror, the input of which is connected to the current output ( 11) the first (1) input parallel-balanced stage on pn-p transistors, and the output is connected to the high-impedance output (9) of the device, a buffer amplifier (12), the input of which is connected to the high-impedance output (9) of the device, and the output is a low-impedance output devices, excellent In that the first (13) and second (14) additional transistors are introduced into the circuit, the emitter of the first (13) additional transistor is connected to the first (3) current-stabilizing two-terminal device, the collector is connected to the common emitter circuit (4) of the first (1) input parallel -balanced cascade on pn-p transistors, and the base through the first (15) non-inverting current follower is connected to the input of the second (10) current mirror, the emitter of the second (14) additional transistor is connected to the second (5) current-stabilizing two-pole, the collector is connected to s emitter circuit (6) of the second (2) input of parallel-balanced stage to an n-p-n transistor and the base through a second (16) non-inverting current follower connected to the input of the first (7) of the current mirror.

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