RU2416155C1 - Differential operating amplifier - Google Patents

Abstract

FIELD: radio engineering.

SUBSTANCE: differential operating amplifier includes input differential cascade (DC) (1) with the first (2) and the second (3) current outputs; current mirror (4) the input of which is connected to the first (2) current output of input DC (1), and output is connected to the base of input transistor (5) of output buffer amplifier (BA) (6), and the first (7) current-stabilising bipole (CB). To the diagram there introduced is the first (8) and the second (9) additional transistors, as well as the second CB (10); at that, collector of the second (9) additional transistor is connected to output of current mirror (4), base is connected to emitter of input transistor (5) of BA (6), as well as to output of device and the second CB (10), emitter of the first (8) additional transistor is connected to the first CB (7), collector is connected to emitter of the second (9) additional transistor, and base of the second (8) additional transistor is connected to potential offset circuit (11).

EFFECT: decreasing absolute U_offset value and its temperature and radiation drift.

3 cl, 7 dwg

Description

The invention relates to the field of radio engineering and communication and can be used as a device for amplifying analog signals, in the structure of analog microcircuits for various functional purposes (for example, in comparators and precision decision amplifiers with small values of EMF of zero bias).

In modern electronic equipment, differential operational amplifiers (op amps) with significant different parameters are used.

A special place is occupied by differential operational amplifiers (op amps) with an active load providing direct control of a push-pull buffer amplifier. Such op-amps have a single-channel structure of signal transmission along the negative feedback circuit and are characterized by lower phase distortion of the signal and higher indices characterizing the stability of the op-amp.

The present invention relates to a class of op-amps based on asymmetric input stages [1-11], which until now have been used only in devices with low requirements for stability of zero level.

The closest in essence to the claimed technical solution is the classical OS scheme (Fig. 1), presented in US patent No. 4.366.442 fig.2, which is also present in a large number of other patents, for example, [1-11], having as load circuits of input transistors controlled current mirrors. Within the framework of such an architecture, it is possible to construct the simplest op-amps providing the maximum amplitude of the output voltage close to the voltages of the power sources.

A significant drawback of the known OS (Fig. 1) is that it has an increased value of the systematic component of the zero bias voltage (U _cm ), which depends on the properties of its architecture.

The main objective of the invention is to reduce the absolute value of U _cm and its temperature and radiation drift.

The problem is achieved in that in the differential operational amplifier (Fig. 1), containing the input differential stage 1 with the first 2 and second 3 current outputs, the current mirror 4, the input of which is connected to the first 2 current output of the input differential stage 1, the output is connected to the base of the input transistor 5 of the output buffer amplifier 6, the first 7 current-stabilizing two-terminal network, new elements and connections are provided - the first 8 and second 9 additional transistors, as well as the second 10 current-stabilizing two a terminal, the collector of the second 9 additional transistor connected to the output of the current mirror 4, the base connected to the emitter of the input transistor 5 of the buffer amplifier 6, as well as the output of the device and the second 10 current-stabilizing two-terminal, the emitter of the first 8 additional transistor connected to the first 7 current-stabilizing two-terminal, collector connected to the emitter of the second 9 additional transistor, and the base of the second 8 additional transistor is connected to the potential bias circuit 11.

The amplifier circuit of the prototype is shown in figure 1. Figure 2 presents a diagram of the inventive device in accordance with claim 1 of the claims.

Figure 3 presents a diagram of the inventive device in accordance with claim 2, and figure 4 - in accordance with claim 3 of the claims.

In Fig.5 and Fig.6 shows a diagram of a differential op-amp prototype (Fig.5) and the claimed opamp (Fig.6) in a computer simulation environment PSpice on models of integrated transistors of FSUE NPP Pulsar.

In Fig.7 shows the temperature dependence of the bias voltage zero of the compared circuits of Fig.5 and Fig.6.

The differential operational amplifier (figure 2) contains the input differential stage 1 with the first 2 and second 3 current outputs, a current mirror 4, the input of which is connected to the first 2 current output of the input differential stage 1, the output is connected to the base of the input transistor 5 of the output buffer amplifier 6 , the first 7 current-stabilizing two-terminal network. The first 8 and second 9 additional transistors are introduced into the circuit, as well as the second 10 current-stabilizing bipolar, the collector of the second 9 additional transistor connected to the output of the current mirror 4, the base connected to the emitter of the input transistor 5 of the buffer amplifier 6, as well as the output of the device and the second 10 current-stabilizing bipolar, the emitter of the first 8 additional transistor is connected to the first 7 current-stabilizing bipolar, the collector is connected to the emitter of the second 9 additional transistor, and the base of the second 8 additional transistor is connected to the potential bias circuit 11. The input differential stage 1 is made on transistors 12, 13 and two-terminal 14.

In Fig. 3, in accordance with claim 2, an additional pn junction 15 connected between the output of the device and the second 10 current-stabilizing two-terminal device is used as potential bias circuit 11.

In Fig. 4, in accordance with claim 3, the first 8 additional transistor contains the main and additional collectors, the main collector connected to the emitter of the second 9 additional transistor, and the additional collector connected to the emitter of the input 5 of the transistor buffer amplifier 6.

Consider the factors that determine the systematic component of the bias voltage of zero U _cm in the circuit of figure 2, i.e. depending on the circuitry of the remote control.

If the current of the two-terminal 14 is equal to 2I ₀ , and the two-terminal 7 and 10 to the value I ₀ (I ₇ = I ₁₀ = I ₀ ), then the collector currents of the transistors of the circuit:

where I _b.p. = I _e.i / β _i is the base current of npn (I _b.p. ) transistors with an emitter current I _e.i = I ₀ ;

β _i is the current gain of the base of npn transistors;

I _{input 4} = I _{output 4} - input and output currents of the current mirror 4.

Taking into account (1) - (6), it is possible to find the current difference in the node “A” during its short circuit to the equipotential common bus:

where I _b.5 = I _b.r - base current npn of the transistor 5.

Thus, in the inventive device, when condition (7) is satisfied, the systematic component U _cm decreases due to the finite value of β transistors and its radiation (or temperature) dependence. As a result, this reduces U _cm , since the differential current I _p in the node “A” creates U _cm , which depends on the steepness S of the conversion of the input differential voltage u _in to the output current of the node “A”:

where r _e13 = r _e12 - resistance of the emitter junctions of the input transistors 13 and 12 of the input differential stage 1.

Therefore, for the circuit of FIG. 2

where φ _t = 26 mV is the temperature potential.

In the op-amp prototype I _p ≠ 0, therefore, here the systematic component U _{cm is} obtained at least an order of magnitude more than in the claimed scheme (Fig. 5, Fig. 6).

Computer simulation of the circuits of Fig.5 and Fig.6 confirms (Fig.7) these theoretical conclusions.

In addition, despite a significant decrease in β transistors due to radiation exposure, the proposed op-amp has under these conditions a lower bias voltage than the op-amp.

In the circuit of figure 3, corresponding to claim 2 of the claims, the static mode along the base circuit of the transistor 8 is set by the p-n junction 15 and the two-terminal 10.

The peculiarity of the circuit of Fig. 4 is that here the static mode of the transistor 5 is set not only by a two-terminal 10, but also by an additional collector of the transistor 8. This increases the stability of zero with current instabilities I ₁₄ = 2I ₀ and I _e = 2I ₀

Thus, the claimed device has significant advantages in comparison with the prototype in terms of the value of the static error of amplification of DC signals.

Literature

1. US Patent No. 4,415,868 fig. 3.

2. Germany patent No. 2928841 fig. 3.

3. Japan patent JP 54-34589 C. 98 (5) A014.

4. Japanese Patent JP 154-10221, CL H03F 3/45.

5. Japan patent JP 54-102949, cl. 98 (5) A21.

6. US Patent No. 4,366,442 fig.2.

7. US patent No. 6.426.678.

8. US Patent Application 2007/0152753 fig.5c.

9. US Patent No. 6,531,920, fig. 4.

10. US patent No. 4.262.261.

11. Ezhkov Yu.A. Handbook of amplifier circuitry. - 2nd ed., Revised. - M .: IP RadioSoft, 2002 .-- 272 p. - Fig. 9.3 (p. 235).

Claims (3)

1. A differential operational amplifier containing an input differential stage with first and second current outputs, a current mirror, the input of which is connected to the first current output of the input differential stage, the output is connected to the base of the input transistor of the output buffer amplifier, the first current-stabilizing two-terminal device, characterized in that the circuit introduced the first and second additional transistors, as well as the second current-stabilizing two-terminal network, and the collector of the second additional transistor is connected to by the output of the current mirror, the base is connected to the emitter of the input transistor of the buffer amplifier, as well as the output of the device and the second current-stabilizing two-terminal, the emitter of the first additional transistor is connected to the first current-stabilizing two-terminal, the collector is connected to the emitter of the second additional transistor, and the base of the second additional transistor is connected to the potential bias circuit . 2. The differential operational amplifier according to claim 1, characterized in that an additional pn junction (15) is used as the potential bias circuit (11), connected between the output of the device and the second (10) current-stabilizing two-terminal device. 3. The differential operational amplifier according to claim 1, characterized in that the first additional transistor contains a primary and secondary collectors, the primary collector connected to the emitter of the second additional transistor, and the secondary collector connected to the emitter of the input transistor of the buffer amplifier.

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