RU2155375C2 - Устройство и способ обработки данных - Google Patents

Устройство и способ обработки данных Download PDF

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Publication number
RU2155375C2
RU2155375C2 RU96106909/09A RU96106909A RU2155375C2 RU 2155375 C2 RU2155375 C2 RU 2155375C2 RU 96106909/09 A RU96106909/09 A RU 96106909/09A RU 96106909 A RU96106909 A RU 96106909A RU 2155375 C2 RU2155375 C2 RU 2155375C2
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RU
Russia
Prior art keywords
bus
data
address
circuit
executor
Prior art date
Application number
RU96106909/09A
Other languages
English (en)
Russian (ru)
Other versions
RU96106909A (ru
Inventor
Вальтер Флинн Дэвид
Original Assignee
Арм Лимитед
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Арм Лимитед filed Critical Арм Лимитед
Publication of RU96106909A publication Critical patent/RU96106909A/ru
Application granted granted Critical
Publication of RU2155375C2 publication Critical patent/RU2155375C2/ru

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G06F13/1631—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0879—Burst mode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
    • G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Information Transfer Systems (AREA)
RU96106909/09A 1993-08-20 1994-08-04 Устройство и способ обработки данных RU2155375C2 (ru)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9317361.5 1993-08-20
GB9317361A GB2281137B (en) 1993-08-20 1993-08-20 Data bus

Publications (2)

Publication Number Publication Date
RU96106909A RU96106909A (ru) 1998-06-20
RU2155375C2 true RU2155375C2 (ru) 2000-08-27

Family

ID=10740798

Family Applications (1)

Application Number Title Priority Date Filing Date
RU96106909/09A RU2155375C2 (ru) 1993-08-20 1994-08-04 Устройство и способ обработки данных

Country Status (13)

Country Link
US (1) US5680643A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
EP (1) EP0714536B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
JP (1) JP3150154B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
KR (1) KR100317033B1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
CN (1) CN1040703C (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
DE (1) DE69410617T2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
GB (1) GB2281137B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
IL (1) IL110610A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
IN (1) IN190336B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
MY (1) MY111292A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
RU (1) RU2155375C2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
TW (1) TW289099B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)
WO (1) WO1995006287A1 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6243768B1 (en) * 1996-02-09 2001-06-05 Intel Corporation Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus
US5983024A (en) * 1997-11-26 1999-11-09 Honeywell, Inc. Method and apparatus for robust data broadcast on a peripheral component interconnect bus
JP2004310547A (ja) * 2003-04-08 2004-11-04 Matsushita Electric Ind Co Ltd 情報処理装置、メモリ、情報処理方法及びプログラム
US7328288B2 (en) * 2003-12-11 2008-02-05 Canon Kabushiki Kaisha Relay apparatus for relaying communication from CPU to peripheral device
US7269704B2 (en) * 2005-03-30 2007-09-11 Atmel Corporation Method and apparatus for reducing system inactivity during time data float delay and external memory write
US7617354B2 (en) * 2007-03-08 2009-11-10 Qimonda North America Corp. Abbreviated burst data transfers for semiconductor memory
JP5350677B2 (ja) * 2008-05-19 2013-11-27 株式会社東芝 バス信号制御回路、及び、バス信号制御回路を備えた信号処理回路
CN101309306B (zh) * 2008-07-16 2010-06-30 哈尔滨工业大学 在Modbus通信网络中为从节点设备分配地址的方法
CN106502806B (zh) * 2016-10-31 2020-02-14 华为技术有限公司 一种总线协议命令处理装置及相关方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU1257656A1 (ru) * 1984-12-18 1986-09-15 Предприятие П/Я В-8117 Устройство дл сопр жени цифровой вычислительной машины с внешним устройством
EP0278264A2 (en) * 1987-02-13 1988-08-17 International Business Machines Corporation Data processing system with overlap bus cycle operations
EP0348113A2 (en) * 1988-06-24 1989-12-27 Advanced Micro Devices, Inc. Programmable burst apparatus and technique

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4851990A (en) * 1987-02-09 1989-07-25 Advanced Micro Devices, Inc. High performance processor interface between a single chip processor and off chip memory means having a dedicated and shared bus structure
US5159679A (en) * 1988-09-09 1992-10-27 Compaq Computer Corporation Computer system with high speed data transfer capabilities
JP2519860B2 (ja) * 1991-09-16 1996-07-31 インターナショナル・ビジネス・マシーンズ・コーポレイション バ―ストデ―タ転送装置および方法
US5553310A (en) * 1992-10-02 1996-09-03 Compaq Computer Corporation Split transactions and pipelined arbitration of microprocessors in multiprocessing computer systems

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SU1257656A1 (ru) * 1984-12-18 1986-09-15 Предприятие П/Я В-8117 Устройство дл сопр жени цифровой вычислительной машины с внешним устройством
EP0278264A2 (en) * 1987-02-13 1988-08-17 International Business Machines Corporation Data processing system with overlap bus cycle operations
EP0348113A2 (en) * 1988-06-24 1989-12-27 Advanced Micro Devices, Inc. Programmable burst apparatus and technique

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
AMITOI et al. Burst mode memories improve cache design. IEEE "Wescon conference Record". North Hollywood. US :IEEE 1990, v.34, c.29-32. *
Computer system channel performance enhancement via address boundary release. IEEE "IBM Technical Disclousure Bulletin". New York. US : IEEE November, 1990, v. 33, N 6B, c.422. *

Also Published As

Publication number Publication date
CN1040703C (zh) 1998-11-11
TW289099B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1996-10-21
GB2281137B (en) 1997-10-08
GB2281137A (en) 1995-02-22
JPH09504391A (ja) 1997-04-28
DE69410617T2 (de) 1999-02-04
GB9317361D0 (en) 1993-10-06
IL110610A (en) 1997-04-15
EP0714536B1 (en) 1998-05-27
EP0714536A1 (en) 1996-06-05
WO1995006287A1 (en) 1995-03-02
IL110610A0 (en) 1994-11-11
JP3150154B2 (ja) 2001-03-26
DE69410617D1 (de) 1998-07-02
US5680643A (en) 1997-10-21
MY111292A (en) 1999-10-30
IN190336B (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 2003-07-19
KR100317033B1 (ko) 2002-02-28
CN1129481A (zh) 1996-08-21
KR960704273A (ko) 1996-08-31

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MM4A The patent is invalid due to non-payment of fees

Effective date: 20070805