NL8202886A - Inrichting voor het uitlezen van gegevens, die bij de overdracht van gegevens wordt gebruikt. - Google Patents

Inrichting voor het uitlezen van gegevens, die bij de overdracht van gegevens wordt gebruikt. Download PDF

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Publication number
NL8202886A
NL8202886A NL8202886A NL8202886A NL8202886A NL 8202886 A NL8202886 A NL 8202886A NL 8202886 A NL8202886 A NL 8202886A NL 8202886 A NL8202886 A NL 8202886A NL 8202886 A NL8202886 A NL 8202886A
Authority
NL
Netherlands
Prior art keywords
data
signal
pulse
level
frequency divider
Prior art date
Application number
NL8202886A
Other languages
English (en)
Dutch (nl)
Original Assignee
Victor Company Of Japan
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Victor Company Of Japan filed Critical Victor Company Of Japan
Publication of NL8202886A publication Critical patent/NL8202886A/nl

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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B14/00—Transmission systems not characterised by the medium used for transmission
    • H04B14/02—Transmission systems not characterised by the medium used for transmission characterised by the use of pulse modulation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1407—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol
    • G11B20/1419—Digital recording or reproducing using self-clocking codes characterised by the use of two levels code representation depending on a single bit, i.e. where a one is always represented by a first code symbol while a zero is always represented by a second code symbol to or from biphase level coding, i.e. to or from codes where a one is coded as a transition from a high to a low level during the middle of a bit cell and a zero is encoded as a transition from a low to a high level during the middle of a bit cell or vice versa, e.g. split phase code, Manchester code conversion to or from biphase space or mark coding, i.e. to or from codes where there is a transition at the beginning of every bit cell and a one has no second transition and a zero has a second transition one half of a bit period later or vice versa, e.g. double frequency code, FM code
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/14—Digital recording or reproducing using self-clocking codes
    • G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
    • G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code

Landscapes

  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Medicines That Contain Protein Lipid Enzymes And Other Medicines (AREA)
NL8202886A 1981-07-17 1982-07-16 Inrichting voor het uitlezen van gegevens, die bij de overdracht van gegevens wordt gebruikt. NL8202886A (nl)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP11165281 1981-07-17
JP56111652A JPS5813046A (ja) 1981-07-17 1981-07-17 デ−タ読み取り回路

Publications (1)

Publication Number Publication Date
NL8202886A true NL8202886A (nl) 1983-02-16

Family

ID=14566749

Family Applications (1)

Application Number Title Priority Date Filing Date
NL8202886A NL8202886A (nl) 1981-07-17 1982-07-16 Inrichting voor het uitlezen van gegevens, die bij de overdracht van gegevens wordt gebruikt.

Country Status (9)

Country Link
US (1) US4504960A (ko)
JP (1) JPS5813046A (ko)
KR (1) KR860001257B1 (ko)
CA (1) CA1186766A (ko)
DE (1) DE3226642A1 (ko)
FR (1) FR2509890A1 (ko)
GB (1) GB2104349B (ko)
NL (1) NL8202886A (ko)
SU (1) SU1301326A3 (ko)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL8303563A (nl) * 1983-10-17 1985-05-17 Philips Nv Inrichting voor het weergeven van digitale informatie via een overdrachtsmedium.
KR900001593B1 (ko) * 1985-03-30 1990-03-15 가부시끼가이샤 도오시바 디지탈신호 재생회로
JPH0624291B2 (ja) * 1985-04-17 1994-03-30 日本電気株式会社 位相検出回路
US4564794A (en) * 1985-05-23 1986-01-14 International Business Machines Corporation Phase locked loop and a motor control servo
IT1189150B (it) * 1986-06-10 1988-01-28 Honeywell Inf Systems Unita' di temporizzazione in tecnologia ttl
US5313496A (en) * 1990-12-26 1994-05-17 Trw Inc. Digital demodulator circuit
JP3140483B2 (ja) * 1991-05-24 2001-03-05 株式会社日立製作所 同期データ取り込み方法および回路
WO1994011952A1 (en) * 1992-11-13 1994-05-26 Ampex Systems Corporation Pseudo clock extractor
JP2959372B2 (ja) * 1993-12-03 1999-10-06 日本電気株式会社 クロック生成回路
JP3340558B2 (ja) * 1994-06-14 2002-11-05 松下電器産業株式会社 信号検出装置およびそれを用いたクロック再生装置
US5572554A (en) * 1994-07-29 1996-11-05 Loral Corporation Synchronizer and method therefor
US5952863A (en) * 1996-12-09 1999-09-14 Texas Instruments Incorporated Circuit and method for generating non-overlapping clock signals for an integrated circuit
ATE359524T1 (de) * 2000-09-11 2007-05-15 Freescale Semiconductor Inc Prüfbare analog/digitalschnittstelleschaltung
FR2880482B1 (fr) * 2004-12-30 2007-04-27 Cit Alcatel Dispositif de conversion d'un signal transmis en un signal numerique
US7622961B2 (en) * 2005-09-23 2009-11-24 Intel Corporation Method and apparatus for late timing transition detection
WO2016179655A1 (en) 2015-05-13 2016-11-17 Beyer Peter Ernest Lighting system with integrated smoke detector
CN109751043B (zh) * 2017-11-01 2021-11-09 中国石油化工股份有限公司 用于地层压力随钻测量工具的压力脉冲编解码系统和方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3266024A (en) * 1962-05-31 1966-08-09 Ibm Synchronizing apparatus
US3537084A (en) * 1967-08-14 1970-10-27 Burroughs Corp Data storage timing system with means to compensate for data shift
US3549804A (en) * 1969-02-10 1970-12-22 Sanders Associates Inc Bit sampling in asynchronous buffers
US3764989A (en) * 1972-12-20 1973-10-09 Ultronic Systems Inc Data sampling apparatus
US3921076A (en) * 1973-03-08 1975-11-18 Int Navigation Corp Method of and apparatus for locating predetermined portions of a radio-frequency pulse, particularly adapted for leading edge location of loran and similar navigational pulses
DE2346934A1 (de) * 1973-09-18 1975-04-03 Siemens Ag Digitaler phasenregelkreis
JPS50155113A (ko) * 1974-05-27 1975-12-15
US3986126A (en) * 1975-05-15 1976-10-12 International Business Machines Corporation Serial pulse-code-modulated retiming system
US4146743A (en) * 1976-08-09 1979-03-27 Hewlett-Packard Company Adaptive sampling decoder-encoder apparatus and method
GB1585080A (en) * 1976-11-06 1981-02-25 Marconi Co Ltd Circuit for producing synchronisation pulses
FR2377729A1 (fr) * 1977-01-14 1978-08-11 Thomson Csf Dispositif de decodage de signaux numeriques, et systeme comportant un tel dispositif
JPS5943020B2 (ja) * 1979-04-27 1984-10-19 富士通株式会社 受信タイミング信号生成方式
GB2091522A (en) * 1980-11-03 1982-07-28 Perkins Res & Mfg Co Clock Generating Digital Data Receiver

Also Published As

Publication number Publication date
US4504960A (en) 1985-03-12
DE3226642A1 (de) 1983-02-03
FR2509890A1 (fr) 1983-01-21
GB2104349B (en) 1985-09-18
JPS5813046A (ja) 1983-01-25
CA1186766A (en) 1985-05-07
KR840001026A (ko) 1984-03-26
GB2104349A (en) 1983-03-02
FR2509890B1 (ko) 1984-12-28
DE3226642C2 (ko) 1988-09-15
KR860001257B1 (ko) 1986-09-01
SU1301326A3 (ru) 1987-03-30

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Legal Events

Date Code Title Description
BA A request for search or an international-type search has been filed
BB A search report has been drawn up
BC A request for examination has been filed
A85 Still pending on 85-01-01
BV The patent application has lapsed