GB2091522A - Clock Generating Digital Data Receiver - Google Patents

Abstract

The method and apparatus for implementation of a digital coherent receiver that can generate a synchronized clock signal from a random digital NRZ data stream having a certain amount of distortion and jitter, but a fixed bit rate. A local clock pulse generator generates pulses at a multiple of that of the transmitter clock and beginning at a first detected transition of the coming data. Pulses are selected from the output of the generator to form a series of the same frequency as that of the transmitter clock and each having an edge at about the mid-point of each data bit.

Description

SPECIFICATION Clock Generating Digital Data Receiver This invention relates to methods and apparatus for transmitting digital data and, more particularly, to high data rate multiplexers.

In transmitting fixed bit rate base-band digital signals, non-return-to-zero (NRZ) data format is frequently desired because it makes maximum use of the available band width of the communication channel, and, therefore, is most cost-effective. in modern communications systems, the use of fiber optics is increasing because of its usefulness in high-speed data transmission.

In order to transmit in NRZ format, which does not carry the clock information for every bit transmitted, a receiver has to be designed so that both the data and the synchronization clock are reconstructed from the NRZ data stream alone.

To minimize the receiving error, as required by all practical applications, the synchronization clock, thus reconstructed, has to be (1) coherent (in frequency) to the NRZ data stream, and (2) since the received data usually has a certain amount of distortion and jitter, the clock has to be able to track the data to maintain a constant timing relationship and be able to respond in very short time.

Moreover, before such a receiver can be widely applied, it must not put any constraint on the NRZ data pattern it is to receive; i.e., it should work on truly random data.

Last, but not least, is the general requirement that the receiver be able to work in the high speed environment of fiber optics applications.

These constraints, added together, preclude the use of known techniques as employed in prior art receivers already existing in the market, such as the Universal Asynchronous Receiver/Transmitter and the Phase-Lock-Loop.

The Universal Asynchronous Receiver/Transmitter (UART) transmits data words (usually 7 or 8 bits per word) asynchronously in NRZ format. Its receiver uses a clock with frequency a multiple of the incoming NRZ data rate. The multiplier is usually 8 or 16. Its receiver, however, does not have bit synchronization capability. It relies on a particular data pattern being transmitted. The incoming data line has to be high when no data is being transmitted. Then, the data word has to be sandwiched between a number of start bits (usually selectable from 1, 1-1/2, to 2 bits) and stop bits. The receiver detects the start bits, determines where the mid-point of each bit is, and then clocks the data bits into the serial-toparallel register at the previously determined midpoint. It does not have tracking capability.None of the single-chip UART's in the market can handle data rates that are required in many contemporary applications.

The Phase-Lock-Loop (PLL) is widely used in coherent receiving schemes. Once locked onto the incoming signal, its voltage controlled oscillator (VCO) is coherent to the incoming signal frequency and will remain in a fixed timing relationship to it on a relatively long-term basis. It cannot adjust itself on short notice, however. Its design incorporates an RC time constant (the lowpass filter of the loop) that cannot respond to short-term variation. It requires some time (a function of the RC) for its VCO to lock up with the incoming signal, and will begin to drift away if the signal has temporarily gone D.C. Errors, therefore, will occur under these conditions.

An even more significant set-back with PLL is encountered when the incoming signal is data in NRZ format. First of all, the data stream cannot be random, since the spectrum of a truly random NRZ data stream has no component at its base band frequency. Therefore, in order to use the PLL, the data pattern has to be manipulated so that there is an identifiable spectral line, such as one half of base band. Also, the data pattern must be manipulated so that there will not be any prolonged period with no data transition, otherwise the PLL will start to lose lock, and error will occur. These requirements impose a substantial overhead on the data transfer rate, and complicate the system design.

Wherefore, it is the object of the present invention to provide a data transmission system for synchronized data wherein the receiver constructs a synchronized clock at the receiving end which clock is synchronized to received NRZ data that is truly random in nature.

The foregoing object has been met in a digital data transmission system wherein digital data varying at a base rate set by a clock of known frequency FO at a transmitter is sent by the transmitter and received by a receiver requiring both the data and a clock signal synchronized to the data by the improvement to the receiver of the present invention comprising means for receiving the incoming data from the transmitter, means connected to the receiving means for detecting a transition in logical states of the incoming data, clock-pulse generating means connected to the transition detection means for generating a series of clock-pulse signals at a frequency which is a multiple of the known frequency FO beginning upon the first detected transition in the incoming data signal, and, means for selecting respective ones of the clock-pulse signals to form a series of clock-pulses occurring at a frequency which is coherent to the known frequency FO and which occur with a rising edge at about mid-point of the individual data pulses of the incoming data to be used as the synchronized clock for the data by the remainder of the receiver circuits.

In the preferred embodiment, correction means are also provided connected to the transition detection means and the clock-pulse selecting means for manipulating the clock-pulses used as the synchronized clock to maintain the synchronized clock-pulses with their rising edge at about the mid-point of the individual data pulses on a best-guess basis as the data jitters and distorts.

In the description which follows: Figure 1 is a block diagram of a signal transmission system as wherein the present invention is employed; Figure 2 is a block diagram showing the prior art method of handling synchronized data; Figure 3 is a block diagram showing the circuitry of the present invention; Figure 4 is a detailed timing diagram showing the theory of operation of the present invention; Figure 5 is another timing diagram showing the operation of the present invention under ideal (no jittering or distortion) NRZ data transmission conditions; Figure 6 is a timing diagram showing the operation of the present invention during the transmission of NRZ data in which jittering and distortion is occurring; and, Figure 7 is a detailed circuit diagram of the portion of a receiver embodying the present invention as being presently commercially sold by the assignee of the present invention under the designation CMX-100 fiber Optic Digital Time Division Multiplexer.

Referring briefly to Figure 1, a signal transmission system, generally indicated as 10, as whereing the objectives achieved by the present invention are desired is shown in block diagram form. A pair of multiplexers 12, at sites removed from one another, are interconnected by a fiber optical cable 14. Both multiplexers 12 are substantially identical so that only the one on the right as Figure 1 is viewed will be described.

Multiplexer 12 can accept various inputs such as from a fiber optic modem 16, a terminal 18, CPU interface 20 or a conventional multiplexer 22 having multiple low speed channels connected thereto. Within the fiber optic apparatus such as multiplexers 12 and fiber optic modem 16, electric signals from electric devices are converted to light signals by light emitting diodes within the apparatus, which light signals travel down the fiber optic cables 14 and 24. On the receiving end, the light signal emerging from the cables 14, 24, strike photo diodes which convert the light energy back into electric signals useful in various electronic circuits.

Turning now to Figure 2, one conventional scheme for sending synchronous data is to transmit both the data and clock from the sender 26 over separate lines 28, 30, respectively, to the receiver 32. Within receiver 32 data handling logic 34 and clock handling logic 36 receive the data and clock signals from lines 28, 30, respectively, and pass on the reconstructed data and clock to the balance of the circuitry within receiver 32. If such a scheme were to be employed within multiplexers 12 of system 10, the fiber optic cable 14 connecting the two would have to contain four optical fibers if bi-directional transmission is to be accomplished (i.e. "duplex mode" transmission). That is, two optical fibers would carry data in the respective opposite direction and two optic fibers would carry the clocks.As will be seen, by employing the method and apparatus of the present invention, fiber optical cable 14 requires only two optic fibers for full duplex operation.

The basic improvements to a receiver when employing the technique of operation of the present invention are shown in Figure 3. In the vast majority of digital data transmission systems, the frequency of the clock to which the data being sent was synchronized at the sending end is known. The present invention works in such an environment and uses this prior knowledge of the synchronized clock requirement to its advantage.

As will be seen, the synchronized clock is not transmitted when using the receiver of the present invention. Rather, the receiver itself, when stimulated by the receipt of random data, constructs a clock signal coherent to the known frequency of the synchronized clock at the transmitting end and synchronizes it to the received data. Moreover, the constructed synchronized clock produced by the receiver is continuously monitored and adjusted so as to keep it in synchronization with the received data bits as the data bits fluctuate due to jitter and distortion.

To accomplish this, raw NRZ data at the known FO bit per second rate is received by signal processing circuit 38. Signal processing circuit 38 passes the data to a multi-stage time delay circuit 40. In a manner to be more fully described hereinafter, the data is extracted from the time delay circuit 40 to become the quanitized NRZ data employed within the balance of the receiver circuits and, additionally, is passed on to transition detection circuit 42. Upon the detection of a transition between logic states in the data, a signal is sent to timing correction logic 44 and from thence to an N-bit shift register 46. The receiver includes a clock generator 48 operating at a multiple of the incoming data frequency.This clock controls the above described circuits whereby the pulse from transition detection circuit 42 is shifted through the shift register 46 at the NFO rate. By selectively choosing a bit position within the shift register, the output thereof becomes a synchronized clock associated with the quanitized NRZ data at approximately the mid-point of the data bits and coherent to the known frequency FO. It is this output which is the constructed synchronized clock.

Additionally, the output from the shift register is returned to timing correctional logic 44 whereby necessary modifications to the bit stream forming the synchronized clock can be made so that the rising edge of the selected bit forming the synchronized clock remains positioned at the approximate mid-point of the data bits regardless of jitter and distortion within the incoming data.

The theory of operation of the method and apparatus of the present invention can best be understood with reference to the detailed timing diagram of Figure 4 which corresponds to ideal data being received in the actual commercial embodiment of the present invention which employs two stages of flip-flops for the time delay circuit 40 and a four-position shift register 46.

The commercial receiver is implemented by ECL 1 OK logic chips to provide the speed required. It features a digital transition detector, a digital feedback control pulse generator that has indefinite memory of the pulse width and frequency. It uses a clock generator 48 with a frequency four (4) times the incoming data rate, The two timing lines on the bottom of Figure 4 indicate time segments at the FO and 4x FO rates.

The NRZ data bit lengths of the FO bits-perseconds is first quanitized into multiples of 1/4FO seconds by shifting the data through the 2-bit shift register 40 clocked by the 4x FO clock 48.

For purposes of the timing diagram shown, it is assumed that a steady state of "zero" of data in is followed by two "one" bits followed by a return to zero. The change in state from 0 to 1 occurs at the second FO timing mark from the left. At the next 4xFO clock pulse, the change of state from 0 to 1 is shifted into position "D 1". Thereafter, at the next internal clock pulse, the change of state is shifted into the second position of the time delay circuit 40, indicated as "DO". As can be seen, each bit of data is (ideally) of a width equal to the time between two FO timing marks. In actual practice, however, the leading and trailing edge of each bit can fluctuate considerably due to distortion and jitter introduced into the transmitted signal by extraneous sources.Thus, the ideal situation is where the rising edge of the generated synchronized clock (the time at which the bit state will be sampled) occurs at approximately the mid-point of each bit, as indicated by the arrows 50. If the status of each bit is sampled at that time, the chances are optimized that the sampled state of the bit will be its true state as transmitted. This is accomplished in the following manner. The first shift position "D1" triggers the transition detection logic 42.

The transition detection logic 42 generates a pulse of 1/4 FO seconds every time level transition occurs in the data stream at position "D1". This pulse is fed to the 4-bit shift register 46 and is circulated in the register to the positions "Q3", "Q2", "Q1", and "Q0". This circulating bit bears a fixed timing relationship to the quanitized NRZ data bit that it was induced from, and it resumes the same position 1/FO seconds (one ideal data bit length) later. It is, therefore, coherent and can be used as the synchronized clock to the data stream. This can be seen from the timing diagram of Figure 4. The rising leading, edge indicated by the arrow 52, of position "D1" causes the transition detection circuit 42 to inject a pulse 54 into position "Q3" of shift register 46.At the next internal clock time it is shifted to position "Q2", and thereafter to positions "Q1" and "QO" as shown. From position "Q0" it is circulated back to position "Q3", at the next time interval, to be recirculated in the foregoing manner over and over again as the timing diagram of Figure 4 indicates. As can be seen, if the output of stage "Q1" is employed as the generated synchronized clock, the rising edges, indicated by the arrows 56, will occur at the data bit midpoints, as indicated by the arrows 50, in the manner desired. Such is the case as actually embodied as will be seen hereinafter in the detailed discussion of the circuit of the actual embodiment.

Briefly, it should also be noted that at the end of the second bit in the data stream appearing at position "D1", as indicated by the arrow 58, the transition detection circuit 42 will desire to inject a bit to position "Q3". Note, also, however, that a pulse, indicated by the arrow 60, is also in position "QO" which would tend to be circulated into position "Q3" on the next internal clock pulse. This simultaneous occurrence indicates that the data and synchronized clock are in synchronization. The correction logic 44 will be discussed hereinafter for the case when the data and the clock begin to drift out of ideal position.

The foregoing relationship is indicated in a slightly different manner in the timing diagram of Figure 5, showing the ideal state in the transmission of NRZ data wherein no jittering or distortion is taking place. The arrows in the timing diagram of Figure 5 (and in Figure 6 to follow) indicate events that cause the outcome. Broken, vertical lines indicate recovered data bit length.

Turning now to Figure 6, a timing diagram is shown which demonstrates the operation of the present invention in the presence of data jittering and distortion. At "1", the raw NRZ data were distorted and jittering, causing the bit length of the quantitized NRZ data to vary. At "2", the 4-bit shift register carried two circulating bits for one bit-time and then was corrected by the timing correction logic the next bit-time. At "3", because of the jitter in bit 4, there were two circulating bits in the 4-bit shift register which would remain there until corrected with the availability of further data transitions. At "4", one more circulating bit was induced by the unique and imperfect timing of bit 8. At "5", correction was made when the bit 9 transition timing conformed with the timing of one of the three circulating bits, giving that bit particular statistically significance.Thus it can be seen that a statistically supported best guess is made to modify the bit being used as the synchronized clock so as to attempt to maintain the rising edge of the synchronized clock at approximately the mid-point of each data bit.

The timing correction takes place with reference to the circulated bit. While being circulated, its position can be altered by the timing correction logic. This logic circuit monitors the position of the bit being circulated in the shift register and the timing of the pulse generated by the transition detection logic. This information is used to determine whether it is necessary to reposition the circulation bit to compensate for the distortion and jittering of the NRZ data bits so that the timing relationship remains constant. As illustrated by the foregoing timing diagrams of Figures 4-6, when there is no distortion or jitter of a sample NRZ data stream, the synchronized clock constructed by the receiver is a constant pulse stream of fixed pulse width.When there is distortion and jittering, the sync clock first becomes wider, and then when a new data transition occurs, the timing correction logic uses that information to reposition the next pulse. This way, the receiver generated synchronized clock is made to track the NRZ data. Also, because this pulse train is self-regenerating, it will go on even though there may not be any data transition for an indefinite duration.

The operation of the timing delay logic now will be discussed in greater detail with reference to the specific circuit of Figure 7. In Figure 7, that portion of the commercial multiplexer of the assignee corporation herein which embodies the present invention is shown. The signal processing circuit 38 is shown as a single TTL to ECL level translation gate. The incoming NRZ data may not necessarily conform to any existing logic family voltage levels. As necessary, a signal processing circuit can be used to shift the voltage level to that of the specific implementation. Signal enhancement techniques, such as filtering and amplifying can also be incorporated into the signal processing circuit design if needed.

It should be noted that the multi-stage time delay circuit, which is shown and discussed hereinafter as a 2-bit register, can also be implemented by analog components such as a multiple tapped time delay line.

While the specific embodiment is directed to a specific mode of implementing the timing correction logic, it is to be understood that the timing correction logic can be implemented to suit specific application in a variety of ways within the scope of the present invention. It may be very elaborate or very simple. It may selectively use all stages of the N-bit shift register as feedback information. The left (number N) of the N-bit shift register can vary according to specific application.

In the present tested embodiment, it employs four bits. The higher the number of bits it has, the better is the receiver's capability to track the incoming NRZ data signal, since the timing correction logic can be implemented accordingly to handle more variation of the NRZ data timing.

The stage, Qk, of the N-bit shift register that is used as the synchronized clock is generally chosen so that its rising edge will be approximately at the midpoint of the data bit coming out of the later stage of the multi-stage time delay circuit. It may be chosen differently to suit specific applications. Other arrangement of this timing is also possible. Even though the method of operation of the present invention does not require incoming NRZ data to conform to any specific pattern, it is beneficial to have as many data transitions as possible within a given number of data bits. This way, the tracking capability of the receiver is enhanced, minimizing the possibility of an error occurring.

Turning now with specificity to the circuit of Figure 7, the multi-stage time delay circuit 40 is seen to comprise the two flip-flops 62 and 64.

The outputs of flip-flops 62 and 64 are "D1" and "DO", as labelled. This corresponds to the labelling of the associated timing diagram of Figure 4. The output of flip-flop 64 (DO) is input to amplifier 66, the output of which, labelled "SDATTL1", is the data which is input to the balance of the receiver circuit. The transition detection circuit, generally indicated as 42, comprises gates 68 and 70. As connected to the flip-flops 62 and 64, output line 72 from gates 68 and 70 produces a logical "1" when a change in logical state of the data has occurred. Shift register 46 is contained in the single chip so labelled. As will be noted, the output of the clock generator 48, labelled "64MCKE", is connected as the driving input of the two flip-flops 62, 64 and the shift register 46.The "Q1" output of the shift register 46 is connected to an ECL to TTL level translator, the output of which is labelled "SYNCLK1" and which is the receiver generated synchronized clock used by the balance of the receiver circuits. The timing correction logic, generally indicated as 44, is provided by the gates 76 and 78. The functioning of the timing correction can best be understood with simultaneous reference to the circuit of Figure 7 and truth tables 1 and 2 hereinafter. Referring first to Table 1, the state under ideal conditions (as in the case shown in Figure 5) is diagrammed.

Assuming that a transition bit caused the propagation of a bit through positions "Q3", "Q2", "Ql", and finally "QO" of shift register 46, and assuming a transition in logical state of the input data exactly on time for the next bit of data, the "Q0" position would contain a "1" coincident with the "1" at the transition bit. As can be seen in Figure 7, the output of position "Q0" is fed back through line 80 as an input to both gates 76 and 78. Likewise, output line 72 appears as an input to both gates 76 and 78. Remember, the available options are to shift the transition bit into position "Q3" and/or to shift the contents of position "QO" (in this case "1") into position "03".According to the gating logic shown, upon the presence of both a transition bit and a "1" in position "QO", the shifting into position "03" is inhibited and a parallel load is enabled causing the 1-bit to be loaded into position "Q3" as indicated in Truth Table 1.

Truth Table 1 Time (4x FO Transition 03 02 Q 1 OO clock period) Bit 1 10001 2 0 1 0 0 0 Truth Table 2 Time Q3 Q2 Q1 QO (4xFO Transition period) clock Bit 1 10010 2 0 1 0 0 1 3 0 1 1 0 0 4 0 0 1 1 0 5 0 0 0 1 1 6 1 1001 7 0 1 0 0 0 The operation of the timing correction logic 44 under jittering and distortion conditions can be seen with reference to truth Table 2, Figure 6, and Figure 7. As discussed above, the transition from "O" to "1" logic state of bit 1 of Figure 6 would have caused the injection of a "1" bit into position "03".As can be seen from the broken vertical lines defining the actual bit length, due to jittering or distortion, bit # was shortened in length. That is, the transition defining the change of state effectively came late. At this point in time, however, timing correction logic 44 has no way in knowing what the true state of affairs is.

Consequently, the transition from bit #2 to bit #3 appears to be one clock pulse early. That is, the transition bit appears with a "1" in the "Q1" position rather than in the "00" position as discussed above with reference to Truth Table 1 and Figure 5. Thus, as shown, at the next clock pulse the transition bit is shifted into position "03" and the bit from position "01" is shifted into position "00". Thus, the circulating register carries two circulating bits until sufficient additional information is provided to allow correction to take place. It can be seen that at the next clock pulse, the bit from position "03" is shifted to position "Q2" and the bit from position from "00', is shifted to position "03". For the next two clock pulses the bits are merely shifted one position each clock pulse since no additional information is yet received.Upon the "00" bit being shifted into "03" and the "01" bit being shifted to "Q0", however the transition bit for the transition between bit #3 and bit #4 also appears. Of the three transitions, rather than bit #1 and bit #4 being late with respect to the transition from bit #2 to bit #3, the logic applies a best guess under the facts provided. Since two out of the three transitions are in the same direction, the logic assumes that bit #3 is actually early and adjusts the timing to the common offset for bits #1 and #4.Thus, the parallel load which occurs in the simultaneous occurrence of the transition bit and the "00', bit on feedback line 80 causes a bit to be parallel loaded into position "Q3" and no shift to take place, whereby the former bit in position "Q3" which, otherwise, would have shifted into position "Q2", is eliminated. In this manner, the receiver generated synchronized clock is readjusted to correspond to the leading edge of bit position #4.

The presence of gates 82, 84, and 86 should be noted. In passing, these are necessary to assure a preset condition of the flip-flops 62 and 64 and the shift register 46 upon reset of the apparatus. Reset pulses from the remainder of the receiver apparatus are provided in a manner well known to those skilled in the art requiring no further comment with respect to the present invention.

Thus, it can be seen that the improvement to a digital data receiver of the present invention has truly met its stated objectives.

Wherefore, having thus described my invention, I claim:

Claims (9)

Claims

1. In a digital data transmission system wherein digital data varying at a basic rate set by a clock of known frequency (FO) at a transmitter is sent by the transmitter and received by a receiver requiring both the data and a clock signal synchronized to the data, the improvement to the receiver comprising: a) means for receiving the incoming data signal from the transmitter; b) means connected to said receiving means for detecting a transition in logical states of the incoming data signal; c) clock pulse generating means connected to said transition detection means for generating a series of clock pulse signals at a frequency which is a multiple of the known frequency FO beginning upon the first detected transition in the incoming data signal; and, d) means connected to said clock pulse generating means for selecting respective ones of said clock pulse signals to form a series of clock pulses coherent to the known frequency FO and having an edge occurring at about mid-point of the individual data pulses of the incoming data, said coherent clock pulses being used as the clock synchronized to the data by the remainder of the receiver circuits.

2. The improvement to a digital data receiver of claim 1 and additionally comprising: means connected to said transition detection means and said clock pulse selecting means for manipulating said clock pulses used as said synchronized clock to maintain said edge of said synchronized clock pulses at about the mid-point of the individual data pulses on a best guess basis as the data jitters and distorts.

3. The improvement to a digital data receiver of claim 1 wherein: a) said transition detection means includes means for quantizing the incoming data signal and an output for providing said quanitized data to the balance of the receiver circuits to be used thereby as the incoming data signal; and, b) said selecting means includes means for changeably selecting the ones of said clock pulses to be used as said synchronized clock so as to select pulses which will maintain said synchronized clock with pulses having an edge occurring at about mid-point of the pulses of said quanitized data.

4. In a digital data transition system wherein digital data varying at a basic rate of known frequency (FO) at a transmitter is sent by the transmitter and received by a receiver requiring both the data and a clock signal synchronized to the data, the improvement to the receiver comprising: a) a clock pulse generator producing at an output thereof a clock signal at a frequency (NFO) which is a multiple (N) of the known frequency (FO);; b) a time delay circuit having a plurality of stages for sequentially receiving and holding a data bit for one clock pulse, said time delay circuit having an input to the first stage thereof connected to receive the incoming data signal from the transmitter and being connected to said output of said clock pulse generator to be driven thereby, said time delay circuit having an output connected to one of said stages after said first stage and connected to the remainder of the receiver's circuits as a source of a quanitized data signal to be used in place of the incoming data signal as received; c) a transition detection circuit connected to said time delay circuit to detect transitions in the logical state of said quanitized data signal and producing a pulse bit at an output thereof upon each occurrence of a change in said logical state; and, d) a circular shift register having N stages with the last stage being shifted into the first, said shift register being connected to said output of said clock pulse generator to be driven thereby, said shift register having an output connected to one of said stages thereof between said first and last stages and connected to the remainder of the receiver's circuits as a source of a synchronized clock signal, said first stage being connected to said output of said transition detection circuit.

5. The improvement to a digital data receiver of claim 4 wherein: said output of said circular shift register is connected to one of said stages thereof about half way between said first and last stages whereby said synchronized clock signal will occur about half way through each data pulse of said quanitized data signal.

6. The improvement to a digital data receiver of claim 4 or claim 5 and additionally comprising: timing correction logic means disposed in the connection between said circular shift register and said transition detection circuit, and between the first and second stages and the last and first stages of said circular shift register for modifying the pattern of bits circulating in said circular shift register to maintain the rising edge of the bit appearing as said synchronized clock at about the mid-point of said quanitized data's bits as said data bits jitter and distort.

7. The improvement to a digital data receiver of claim 6 wherein: said timing correction logic means includes logic to load the contents of the last stage into the first stage, not load the input from said transmission detection means into the first stage, and not shift the first stage into the second stage when the last stage and the input from said transition detection means are both a "1" bit at the time a shift would otherwise take place.

8. The improvement to a digital data receiver of claim 4 wherein: a) said time delay circuit has two stages; b) said circular shift register has four stages; and, c) said synchronized clock is taken from the third stage of said shift register.

9. In a digital data transition system wherein digital data varying at a basic rate of known frequency (FO) at a transmitter is sent by the transmitter and received by a receiver requiring both the data and a clock signal synchronized to the data, the improvement to the receiver comprising: a) a clock pulse generator producing at an output thereof a clock signal at a frequency (4FO) of four times the known frequency; b) a pair of flip-flops connected to said clock output to be driven thereby, one of said flip-flops being connected to receive the incoming data from the transmitter as its input, the other of said flip-flops being connected to said one of said flipflops as its input and having an output connected to the remainder of the receiver's circuits as a source of a quanitized data signal to be used in place of the incoming data signal as received;; c) a transition detection circuit connected to said flip-flops to detect transitions in the logical state of said quanitized data signal and producing a pulse bit at an output thereof upon each occurrence of a change in said logical state; d) a four stage circular shift register wherein the fourth stage is shifted in to the first, said shift register being connected to said output of said clock pulse generator to be driven thereby, said shift register having an output connected to the third stage and connected to the remainder of the receiver's circuits as a source of a synchronized clock signal, the first stage being connected to said output of said transition detection circuit; and, e) timing correction logic means disposed in the connection between said circular shift register and said transition detection circuit, and between the first and second stages and the fourth and first stages of said circular shift register for modifying the pattern of bits circulating in said circular shift register to maintain the rising edge of the bit in the third stage being used as the synchronized clock at about the midpoint of said quanitized datas bits as said data bits jitter and distort, said logic means including logic to load the contents of the fourth stage into the first stage, not load the input from said transition detection means into the first stage, and not shift the first stage into the second stage when the fourth stage and the input from said transition detection means are both a "1" bit at the time a shift would otherwise take place.