NL7908534A - Werkwijze voor het vervaardigen van een mos-inrichting met zelf-uitgerichte contacten. - Google Patents

Werkwijze voor het vervaardigen van een mos-inrichting met zelf-uitgerichte contacten. Download PDF

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Publication number
NL7908534A
NL7908534A NL7908534A NL7908534A NL7908534A NL 7908534 A NL7908534 A NL 7908534A NL 7908534 A NL7908534 A NL 7908534A NL 7908534 A NL7908534 A NL 7908534A NL 7908534 A NL7908534 A NL 7908534A
Authority
NL
Netherlands
Prior art keywords
layer
source
gate
drain regions
gate electrodes
Prior art date
Application number
NL7908534A
Other languages
English (en)
Dutch (nl)
Original Assignee
American Micro Syst
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by American Micro Syst filed Critical American Micro Syst
Publication of NL7908534A publication Critical patent/NL7908534A/nl

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
    • H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
NL7908534A 1979-01-08 1979-11-23 Werkwijze voor het vervaardigen van een mos-inrichting met zelf-uitgerichte contacten. NL7908534A (nl)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US184079A 1979-01-08 1979-01-08
US184079 1979-01-08

Publications (1)

Publication Number Publication Date
NL7908534A true NL7908534A (nl) 1980-07-10

Family

ID=21698078

Family Applications (1)

Application Number Title Priority Date Filing Date
NL7908534A NL7908534A (nl) 1979-01-08 1979-11-23 Werkwijze voor het vervaardigen van een mos-inrichting met zelf-uitgerichte contacten.

Country Status (7)

Country Link
JP (1) JPS5593271A (enrdf_load_html_response)
CA (1) CA1131796A (enrdf_load_html_response)
DE (1) DE3000121A1 (enrdf_load_html_response)
FR (1) FR2446011A1 (enrdf_load_html_response)
GB (1) GB2040564A (enrdf_load_html_response)
IT (1) IT8019078A0 (enrdf_load_html_response)
NL (1) NL7908534A (enrdf_load_html_response)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4506437A (en) * 1978-05-26 1985-03-26 Rockwell International Corporation Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
US4455737A (en) * 1978-05-26 1984-06-26 Rockwell International Corporation Process for and structure of high density VLSI circuits, having self-aligned gates and contacts for FET devices and conducting lines
US4409722A (en) * 1980-08-29 1983-10-18 International Business Machines Corporation Borderless diffusion contact process and structure
US4341009A (en) * 1980-12-05 1982-07-27 International Business Machines Corporation Method for making an electrical contact to a silicon substrate through a relatively thin layer of silicon dioxide on the surface of the substrate
JPS57113289A (en) * 1980-12-30 1982-07-14 Fujitsu Ltd Semiconductor device and its manufacture
US4517729A (en) * 1981-07-27 1985-05-21 American Microsystems, Incorporated Method for fabricating MOS device with self-aligned contacts
US4686000A (en) * 1985-04-02 1987-08-11 Heath Barbara A Self-aligned contact process
JPS63207171A (ja) * 1987-02-24 1988-08-26 Nippon Telegr & Teleph Corp <Ntt> 半導体メモリ装置及びその製造方法
US5159353A (en) * 1991-07-02 1992-10-27 Hewlett-Packard Company Thermal inkjet printhead structure and method for making the same
KR100377833B1 (ko) * 2001-06-19 2003-03-29 삼성전자주식회사 보더리스 콘택 구조를 갖는 반도체 장치 및 그 제조방법

Also Published As

Publication number Publication date
GB2040564A (en) 1980-08-28
DE3000121A1 (de) 1980-07-17
IT8019078A0 (it) 1980-01-08
FR2446011B3 (enrdf_load_html_response) 1981-11-06
CA1131796A (en) 1982-09-14
JPS5593271A (en) 1980-07-15
FR2446011A1 (fr) 1980-08-01

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Legal Events

Date Code Title Description
A85 Still pending on 85-01-01
BV The patent application has lapsed