MX371491B - Divisor de frecuencia, ciclo de fase cerrada, transceptor, estacion de radio y metodo para dividir frecuencia. - Google Patents

Divisor de frecuencia, ciclo de fase cerrada, transceptor, estacion de radio y metodo para dividir frecuencia.

Info

Publication number
MX371491B
MX371491B MX2017016221A MX2017016221A MX371491B MX 371491 B MX371491 B MX 371491B MX 2017016221 A MX2017016221 A MX 2017016221A MX 2017016221 A MX2017016221 A MX 2017016221A MX 371491 B MX371491 B MX 371491B
Authority
MX
Mexico
Prior art keywords
frequency
signal
receive
output
circuit
Prior art date
Application number
MX2017016221A
Other languages
English (en)
Other versions
MX2017016221A (es
Inventor
Sjöland Henrik
Ek Staffan
Påhlsson Tony
Original Assignee
Ericsson Telefon Ab L M
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ericsson Telefon Ab L M filed Critical Ericsson Telefon Ab L M
Publication of MX2017016221A publication Critical patent/MX2017016221A/es
Publication of MX371491B publication Critical patent/MX371491B/es

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
    • H03L7/0996—Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
    • H03K23/667—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by switching the base during a counting cycle
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/191—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number using at least two different signals from the frequency divider or the counter for determining the time difference
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
    • H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/68—Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a base which is a non-integer

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Superheterodyne Receivers (AREA)

Abstract

Se proporciona un circuito electrónico dispuesto para recibir una señal oscilante y la salida de una señal de salida a una frecuencia que tiene una relación de frecuencia con la señal oscilante definida por una relación de división. El circuito electrónico comprende un primer divisor de frecuencia dispuesto para recibir la señal oscilante y salida de señales de frecuencia N divididas de distintas fases, un segundo divisor de frecuencia dispuesto para recibir una de las señales N y la frecuencia dividir la señal recibida por un valor dado por un primer control de señal proporcionada a la segunda divisor de frecuencia, los circuitos de retención N estando cada uno dispuesto para recibir una respectiva de las señales N en una entrada de sincronización del circuito de retención respectivo y para recibir una salida del segundo divisor de frecuencia en una entrada del circuito de retención respectivo, un circuito multiplexor dispuesto para recibir salidas de los circuitos de retención N y emitir una señal, en que se basa la señal de salida, seleccionada de las señales recibidas en base a una segunda señal de control proporcionada al circuito multiplexor, y un circuito de control dispuesto para proporcionar la primera señal de control y la segunda señal de control en base a la relación de división. También se proporciona un circuito de ciclo de retención de fase, un circuito de transceptor, una estación de radio, y un método de frecuencia que divide una señal oscilante.
MX2017016221A 2015-06-16 2015-06-16 Divisor de frecuencia, ciclo de fase cerrada, transceptor, estacion de radio y metodo para dividir frecuencia. MX371491B (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/EP2015/063497 WO2016202367A1 (en) 2015-06-16 2015-06-16 Frequency divider, phase-locked loop, transceiver, radio station and method of frequency dividing

Publications (2)

Publication Number Publication Date
MX2017016221A MX2017016221A (es) 2018-03-07
MX371491B true MX371491B (es) 2020-01-31

Family

ID=53442775

Family Applications (1)

Application Number Title Priority Date Filing Date
MX2017016221A MX371491B (es) 2015-06-16 2015-06-16 Divisor de frecuencia, ciclo de fase cerrada, transceptor, estacion de radio y metodo para dividir frecuencia.

Country Status (13)

Country Link
US (2) US10110238B2 (es)
EP (1) EP3311490B1 (es)
JP (1) JP6484354B2 (es)
KR (1) KR20180006964A (es)
CN (1) CN107750432A (es)
AR (1) AR105007A1 (es)
AU (1) AU2015399336B2 (es)
MX (1) MX371491B (es)
MY (1) MY182290A (es)
PH (1) PH12017502159A1 (es)
RU (1) RU2668737C1 (es)
WO (1) WO2016202367A1 (es)
ZA (1) ZA201708326B (es)

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KR102627861B1 (ko) * 2019-04-16 2024-01-23 에스케이하이닉스 주식회사 위상 감지 회로, 이를 이용하는 클럭 생성 회로 및 반도체 장치
US10530373B1 (en) * 2019-06-01 2020-01-07 Globalfoundries Inc. Method and system for generating a saw-tooth signal with fast fly back interval
CN112953531B (zh) * 2021-02-18 2022-03-18 华南理工大学 一种基于delta-sigma调制器的锁相环小数分频方法
US11570033B1 (en) * 2021-08-17 2023-01-31 Apple Inc. Multiphase signal generator

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US6542013B1 (en) * 2002-01-02 2003-04-01 Intel Corporation Fractional divisors for multiple-phase PLL systems
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Also Published As

Publication number Publication date
JP2018522472A (ja) 2018-08-09
AR105007A1 (es) 2017-08-30
ZA201708326B (en) 2019-06-26
MX2017016221A (es) 2018-03-07
US10110238B2 (en) 2018-10-23
EP3311490B1 (en) 2019-04-24
KR20180006964A (ko) 2018-01-19
US20180367153A1 (en) 2018-12-20
US20180159546A1 (en) 2018-06-07
JP6484354B2 (ja) 2019-03-13
WO2016202367A1 (en) 2016-12-22
MY182290A (en) 2021-01-18
CN107750432A (zh) 2018-03-02
RU2668737C1 (ru) 2018-10-02
EP3311490A1 (en) 2018-04-25
AU2015399336A1 (en) 2018-01-18
US10312923B2 (en) 2019-06-04
AU2015399336B2 (en) 2018-12-06
PH12017502159A1 (en) 2018-05-28

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