KR970707578A - 노출된 반도체 다이스를 테스트하기 위한 자기 제한 실리콘 베이스 상호접속부를 제조하는 방법(method for fabricating a self limting silcon based interconnect for testing bare semiconductor dice) - Google Patents

노출된 반도체 다이스를 테스트하기 위한 자기 제한 실리콘 베이스 상호접속부를 제조하는 방법(method for fabricating a self limting silcon based interconnect for testing bare semiconductor dice)

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KR970707578A
KR970707578A KR1019970703033A KR19970703033A KR970707578A KR 970707578 A KR970707578 A KR 970707578A KR 1019970703033 A KR1019970703033 A KR 1019970703033A KR 19970703033 A KR19970703033 A KR 19970703033A KR 970707578 A KR970707578 A KR 970707578A
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forming
silicon
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contact member
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KR100285224B1 (ko
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아크람 살만
엠. 판워스 워렌
지. 우드 앨런
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마이클 엘. 린치
마이크론 테크놀러지 인코오포레이티드
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/06711—Probe needles; Cantilever beams; "Bump" contacts; Replaceable probe pins
    • G01R1/06733—Geometry aspects
    • G01R1/06738—Geometry aspects related to tip portion
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
    • G01R1/07314—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0373—Conductors having a fine structure, e.g. providing a plurality of contact points with a structured tool
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09045—Locally raised area or protrusion of insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49453—Pulley making

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  • Geometry (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Led Device Packages (AREA)
  • Formation Of Insulating Films (AREA)
  • Measuring Leads Or Probes (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

반도체 다이상의 접착 패드와의 일시적인 전기 접촉을 생성하기 위한 자기 제한 실리콘 베이스 상호접속부를 형성하는 방법이 제공된다. 상기 상호접속부는 테스트(예컨대, 번－인 테스트)용으로 상기 다이상에 접착 패드에 접촉하는데 적합한 적촉 부재의 어레이를 갖는 실리콘 기판을 포함한다. 상기 상호접속부는 상기 기판상 접촉 부재를 형성하고；상기 접촉 부재의 팁상에 도전층을 형성하며；그 후 상기 도전층에 도전성 트레이스를 형성함으로써 제조된다. 상기 도전층은 상기 기판 및 접촉 부재상에 실리콘 함유층(예컨대, 폴리실리콘, 비경질 실리콘) 및 금속층(예컨대, 티타늄, 텅스텐, 플리타늄)을 증착시킴으로써 형성된다. 이들 층은 규화물을 형성하도록 반응된다. 비반응 금속 및 실리콘 함유층은 이어서 상기 접촉 부재의 팁상에 남아 있는 도전성 층에 선택적으로 에칭된다. 도전성 트레이스는 그 후 적절한 경화 공정을 사용하여 상기 도전층과 접촉하여 형성된다. 접착 와이어가 상기 도전성 트레이스에 부착되고 외부 테스트 회로에 부착될 수 있다. 선택적으로 외부접촉(예컨대, 슬라이드 접촉)과 같은 다른 도전성 경로는 상기 도전성 트레이스 및 외부 회로 사이에 도전성 경로를 제공할 수 있다. 상기 도전층, 도전성 트레이스 및 접착 와이어는 상기 접촉 부재의 팁으로부터 외부 테스트 회로로 저저항 도전성 경로를 제공한다.

Description

노출된 반도체 다이스를 테스트하기 위한 자기 제한 실리콘 베이스 상호접속부를 제조하는 방법(METHOD FOR FABRICATING A SELF LIMITING SILICON BASED INTERCONNECT FOR TESTING BARE SEMICONDUCTOR DICE)
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 제2도의 평면도, 제14도는 완전한 접촉 부재 및 도전성 트레이스를 도시하는 개략적인 단면도, 제17도는 중첩된 다이와 완전한 상호접속부의 평면도.

Claims (20)

  1. 반도체 집적 회로 다이를 테스트하는 상호접속부를 제조하는 방법에 있어서；기판상에 상승 접촉 부재의 어레이를 형성하는 단계를 포함하는데, 상기 접촉 부재는 상기 다이상의 전기 전도성 접촉 위치를 연결하도록 크기 조정 및 이격되고；상기 접촉 부재상에 제1물질층과 제2물질층을 형성하는 단계와；상기 접촉 부재상에 도전층을 형성하도록 제1물질층과 제2물질층을 반응시키는 단계와；상기 도전층에 상기 제1 및 제2층을 선택적으로 에칭하는 단계와；상기 도정층과 접촉하는 상기 기판상에 도전성 트레이스를 형성하는 단계를 포함하는 것을 특징으로 하는 상호접속부 제조 방법.
  2. 제1항에 있어서, 상기 도전층은 규화물을 포함하는 것을 특징으로 하는 상호접속부 제조 방법.
  3. 제1항에 있어서, 상기 제1층은 실리콘 함유 물질이고 상기 제2층은 금속이며, 상기 제1 및 제2층은 금속 규화물로 상기 도전층을 형성하도록 가열되는 것을 특징으로 하는 상호접속부 제조 방법.
  4. 제1항에 있어서, 상기 제1물질층은 폴리실리콘 및 비경질 실리콘으로 이루어진 물질의 그룹에서 선택되는 것을 특징으로 하는 상호접속부 제조 방법.
  5. 제1항에 있어서, 상기 제2물질층은 티타늄, 플래티늄, 텅스텐, 코발트, 탄탈륨, 니켈, 몰리브덴, 구리, 금 및 이리듐으로 이루어진 물질의 그룹에서 선택되는 것을 특징으로 하는 상호접속부 제조 방법.
  6. 제1항에 있어서, 상기 접촉 부재는 상기 접착 패드를 관통하는 데 및 상기 접착 패드로의 관통을 제한하도록 정지면을 제공하는데 적합한 나이프 에지와 같이 형성된 돌출 정점을 포함하는 것을 특징으로 하는 상호접속부 제조 방법.
  7. 반도체 다이를 테스트하는 상호접속부를 제조하는 방법에 있어서；기판상에 상승 접촉 부재를 형성하는 단계를 포함하는데, 상기 접촉 부재는 상기 다이상의 접촉 지점과 접촉하도록 크기 조정되고 이격되며；상기 기판과 접촉 부재상에 실리콘 함유층을 형성하는 단계와；상기 실리콘 함유층상에 절연층을 형성하는 단계와；상기 접촉 부재상에 상기 절연층을 에칭하는 단계와；상기 실리콘 함유층상 및 상기 절연층상에 금속층을 증착시키는 단계와, 상기 접촉 부재상에 규화물층을 형성하도록 상기 실리콘 함유층과 금속층을 가열하는 단계와；상기 금속층을 에칭하고, 상기 절연층을 제거하며, 상기 규화물층으로 덮여진 접촉 부재의 팁을 남기도록 상기 규화물층에 실리콘 함유층을 선택적으로 에칭하는 단계와；상기 규화물층과 접촉하는 도전성 트레이스를 형성하는 단계를 포함하는 것을 특징으로 하는 상호접속부 제조 방법.
  8. 제7항에 있어서, 상기 기판은 자체의 표면상에 형성된 절연층을 갖는 단결정 실리콘을 포함하는 것을 특징으로 하는 상호접속부 제조 방법.
  9. 제7항에 있어서, 상기 실리콘 함유층은 도핑된 폴리실리콘, 도핑되지 않은 폴리실리콘, 도핑된 비경질 실리콘 및 도핑되지 않은 비경질 실리콘으로 이루어진 물질의 그룹에서 선택되는 것을 특징으로 하는 상호접속부 제조 방법.
  10. 제7항에 있어서, 상기 금속층은 티나늄, 플래티늄, 텅스턴, 코발트, 탄탈륨, 니켈, 몰리브덴, 구리 및 금으로 이루어진 그룹에서 선택되는 것을 특징으로 하는 상호접속부 제조 방법.
  11. 제7항에 있어서, 상기 접촉 부재는 상기 접착 패드를 관통하는 나이프 에지로 형성된 돌출 정점을 포함하는 것을 특징으로 하는 상호접속부 제조 방법.
  12. 제7항에 있어서, 저항을 감소시키도록 상기 규화물층을 어닐링하는 단계를 추가로 포함하는 것을 특징으로 하는 상호접속부 제조 방법.
  13. 제7항에 있어서, 접착 와이어를 상기 도전성 트레이스에 부착하는 단계를 추가로 포함하는 것을 특징으로 하는 상호접속부 제조 방법.
  14. 제7항에 있어서, 단일 기판상에 복수의 상호 접속부를 형성하는 단계와 상기 상호접속부를 단일화시키는 단계를 추가로 포함하는 것을 특징으로 하는 상호접속부 제조 방법.
  15. 제7항에 있어서, 상기 도전성 트레이스는 알루미늄, 구리, 플래티늄, 텅스텐, 탄탈륨, 몰리브덴 및 이들 금속의 합금으로 이루어진 금속에서 선택된 금속으로부터 경화 공정에 의해 형성되는 것을 특징으로 하는 상호접속부 제조 방법.
  16. 제7항에 있어서, 상기 다이와 테스트 회로 사이에 일시적인 전기 접속을 설정하는 테스트 장치내에 상기 상호접속부를 위치시키는 단계를 추가로 포함하는 것을 특징으로 하는 상호접속부 제조 방법.
  17. 반도체 다이의 접착 패드와 전기 접촉을 설정하는 상호접속부를 형성하는 방법에 있어서；돌출 정점을 갖는 기판상에 상승 접촉 부재를 형성하는 단계와；상기 접촉 부재와 기판상에 제1절연층을 형성하는 단계와；상기 실리콘 함유층상에 제2절연층을 형성하는 단계와；상기 접촉 부재를 노출된 상태로 둘 때 상기 기판상에 마스크를 형성하는 단계와；상기 마스크를 사용하는 상기 접촉 부재상의 상기 제2절연층을 제거하는 단계와, 상기 마스크를 제거하는 단계와；상기 접촉 부재와 기판상에 금속층을 증착시키는 단계와；규화물층을 형성하도록 상기 금속층과 실리콘 함유층을 가열하는 단계와；상기 접촉 부재상에 규화물 팁을 형성하도록 상기 규화물층에 상기 금속층 및 상기 실리콘 함유층을 선택적으로 에칭하는 단계와；상기 제2절연층을 제거하는 단계와; 상기 규화물층과 접촉하는 도전성 트레이스를 형성하는 단계와; 상기 도전성 트레이스에 접착 와이어를 부착하는 단계를 포함하는 것을 특징으로 하는 상호접속부 형성 방법.
  18. 제17항에 있어서, 저항을 감소시키도록 상기 규화물층을 어닐링하는 단계를 추가로 포함하는 것을 특징으로 하는 상호접속부 형성 방법.
  19. 제17항에 있어서, 상기 돌출 정점은 상기 접착 패드로의 관통을 제한하는 정지면을 형성하기 위해 상기 접착 패드를 관통하는 나이프 에지로 형성되는 것을 특징으로 하는 상호접속부 형성 방법.
  20. 제17항에 있어서, 웨이퍼상에 복수의 상호접속부를 형성하고, 상기 상호접속부를 단일화하기 위해 상기`웨이퍼를 절단하는 단계를 추가로 포함하는 것을 특징으로 하는 상호접속부 형성 방법.
    ※ 참고사항：최초출원 내용에 의하여 공개하는 것임.
KR1019970703033A 1994-11-07 1995-11-06 노출된 반도체 다이스를 테스트하기 위한 자기 제한 실리콘베이스 상호접속부를 제조하는 방법 KR100285224B1 (ko)

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US08/335,267 1994-11-07
US08/335,267 US5483741A (en) 1993-09-03 1994-11-07 Method for fabricating a self limiting silicon based interconnect for testing bare semiconductor dice
US8/335,267 1994-11-07
PCT/US1995/014483 WO1996014660A1 (en) 1994-11-07 1995-11-06 Method for fabricating a self-limiting silicon based interconnect for testing bare semiconductor dice

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EP0792518A1 (en) 1997-09-03
ATE238606T1 (de) 2003-05-15
US5483741A (en) 1996-01-16
JP3195359B2 (ja) 2001-08-06
DE69530509D1 (de) 2003-05-28
AU4232396A (en) 1996-05-31
KR100285224B1 (ko) 2001-04-02
DE69530509T2 (de) 2004-03-04
WO1996014660A1 (en) 1996-05-17
EP0792518B1 (en) 2003-04-23

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