KR970707578A - 노출된 반도체 다이스를 테스트하기 위한 자기 제한 실리콘 베이스 상호접속부를 제조하는 방법(method for fabricating a self limting silcon based interconnect for testing bare semiconductor dice) - Google Patents

노출된 반도체 다이스를 테스트하기 위한 자기 제한 실리콘 베이스 상호접속부를 제조하는 방법(method for fabricating a self limting silcon based interconnect for testing bare semiconductor dice)

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KR970707578A
KR970707578A KR1019970703033A KR19970703033A KR970707578A KR 970707578 A KR970707578 A KR 970707578A KR 1019970703033 A KR1019970703033 A KR 1019970703033A KR 19970703033 A KR19970703033 A KR 19970703033A KR 970707578 A KR970707578 A KR 970707578A
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forming
silicon
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contact member
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아크람 살만
엠. 판워스 워렌
지. 우드 앨런
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마이클 엘. 린치
마이크론 테크놀러지 인코오포레이티드
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/06711—Probe needles; Cantilever beams; "Bump" contacts; Replaceable probe pins
    • G01R1/06733—Geometry aspects
    • G01R1/06738—Geometry aspects related to tip portion
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
    • G01R1/07314—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0367—Metallic bump or raised conductor not used as solder bump
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0364—Conductor shape
    • H05K2201/0373—Conductors having a fine structure, e.g. providing a plurality of contact points with a structured tool
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09009—Substrate related
    • H05K2201/09045—Locally raised area or protrusion of insulating substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49453—Pulley making

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Led Device Packages (AREA)
  • Measuring Leads Or Probes (AREA)
  • Formation Of Insulating Films (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

반도체 다이상의 접착 패드와의 일시적인 전기 접촉을 생성하기 위한 자기 제한 실리콘 베이스 상호접속부를 형성하는 방법이 제공된다. 상기 상호접속부는 테스트(예컨대, 번－인 테스트)용으로 상기 다이상에 접착 패드에 접촉하는데 적합한 적촉 부재의 어레이를 갖는 실리콘 기판을 포함한다. 상기 상호접속부는 상기 기판상 접촉 부재를 형성하고；상기 접촉 부재의 팁상에 도전층을 형성하며；그 후 상기 도전층에 도전성 트레이스를 형성함으로써 제조된다. 상기 도전층은 상기 기판 및 접촉 부재상에 실리콘 함유층(예컨대, 폴리실리콘, 비경질 실리콘) 및 금속층(예컨대, 티타늄, 텅스텐, 플리타늄)을 증착시킴으로써 형성된다. 이들 층은 규화물을 형성하도록 반응된다. 비반응 금속 및 실리콘 함유층은 이어서 상기 접촉 부재의 팁상에 남아 있는 도전성 층에 선택적으로 에칭된다. 도전성 트레이스는 그 후 적절한 경화 공정을 사용하여 상기 도전층과 접촉하여 형성된다. 접착 와이어가 상기 도전성 트레이스에 부착되고 외부 테스트 회로에 부착될 수 있다. 선택적으로 외부접촉(예컨대, 슬라이드 접촉)과 같은 다른 도전성 경로는 상기 도전성 트레이스 및 외부 회로 사이에 도전성 경로를 제공할 수 있다. 상기 도전층, 도전성 트레이스 및 접착 와이어는 상기 접촉 부재의 팁으로부터 외부 테스트 회로로 저저항 도전성 경로를 제공한다.

Description

노출된 반도체 다이스를 테스트하기 위한 자기 제한 실리콘 베이스 상호접속부를 제조하는 방법(METHOD FOR FABRICATING A SELF LIMITING SILICON BASED INTERCONNECT FOR TESTING BARE SEMICONDUCTOR DICE)
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 제2도의 평면도, 제14도는 완전한 접촉 부재 및 도전성 트레이스를 도시하는 개략적인 단면도, 제17도는 중첩된 다이와 완전한 상호접속부의 평면도.

Claims (20)

  1. 반도체 집적 회로 다이를 테스트하는 상호접속부를 제조하는 방법에 있어서；기판상에 상승 접촉 부재의 어레이를 형성하는 단계를 포함하는데, 상기 접촉 부재는 상기 다이상의 전기 전도성 접촉 위치를 연결하도록 크기 조정 및 이격되고；상기 접촉 부재상에 제1물질층과 제2물질층을 형성하는 단계와；상기 접촉 부재상에 도전층을 형성하도록 제1물질층과 제2물질층을 반응시키는 단계와；상기 도전층에 상기 제1 및 제2층을 선택적으로 에칭하는 단계와；상기 도정층과 접촉하는 상기 기판상에 도전성 트레이스를 형성하는 단계를 포함하는 것을 특징으로 하는 상호접속부 제조 방법.
  2. 제1항에 있어서, 상기 도전층은 규화물을 포함하는 것을 특징으로 하는 상호접속부 제조 방법.
  3. 제1항에 있어서, 상기 제1층은 실리콘 함유 물질이고 상기 제2층은 금속이며, 상기 제1 및 제2층은 금속 규화물로 상기 도전층을 형성하도록 가열되는 것을 특징으로 하는 상호접속부 제조 방법.
  4. 제1항에 있어서, 상기 제1물질층은 폴리실리콘 및 비경질 실리콘으로 이루어진 물질의 그룹에서 선택되는 것을 특징으로 하는 상호접속부 제조 방법.
  5. 제1항에 있어서, 상기 제2물질층은 티타늄, 플래티늄, 텅스텐, 코발트, 탄탈륨, 니켈, 몰리브덴, 구리, 금 및 이리듐으로 이루어진 물질의 그룹에서 선택되는 것을 특징으로 하는 상호접속부 제조 방법.
  6. 제1항에 있어서, 상기 접촉 부재는 상기 접착 패드를 관통하는 데 및 상기 접착 패드로의 관통을 제한하도록 정지면을 제공하는데 적합한 나이프 에지와 같이 형성된 돌출 정점을 포함하는 것을 특징으로 하는 상호접속부 제조 방법.
  7. 반도체 다이를 테스트하는 상호접속부를 제조하는 방법에 있어서；기판상에 상승 접촉 부재를 형성하는 단계를 포함하는데, 상기 접촉 부재는 상기 다이상의 접촉 지점과 접촉하도록 크기 조정되고 이격되며；상기 기판과 접촉 부재상에 실리콘 함유층을 형성하는 단계와；상기 실리콘 함유층상에 절연층을 형성하는 단계와；상기 접촉 부재상에 상기 절연층을 에칭하는 단계와；상기 실리콘 함유층상 및 상기 절연층상에 금속층을 증착시키는 단계와, 상기 접촉 부재상에 규화물층을 형성하도록 상기 실리콘 함유층과 금속층을 가열하는 단계와；상기 금속층을 에칭하고, 상기 절연층을 제거하며, 상기 규화물층으로 덮여진 접촉 부재의 팁을 남기도록 상기 규화물층에 실리콘 함유층을 선택적으로 에칭하는 단계와；상기 규화물층과 접촉하는 도전성 트레이스를 형성하는 단계를 포함하는 것을 특징으로 하는 상호접속부 제조 방법.
  8. 제7항에 있어서, 상기 기판은 자체의 표면상에 형성된 절연층을 갖는 단결정 실리콘을 포함하는 것을 특징으로 하는 상호접속부 제조 방법.
  9. 제7항에 있어서, 상기 실리콘 함유층은 도핑된 폴리실리콘, 도핑되지 않은 폴리실리콘, 도핑된 비경질 실리콘 및 도핑되지 않은 비경질 실리콘으로 이루어진 물질의 그룹에서 선택되는 것을 특징으로 하는 상호접속부 제조 방법.
  10. 제7항에 있어서, 상기 금속층은 티나늄, 플래티늄, 텅스턴, 코발트, 탄탈륨, 니켈, 몰리브덴, 구리 및 금으로 이루어진 그룹에서 선택되는 것을 특징으로 하는 상호접속부 제조 방법.
  11. 제7항에 있어서, 상기 접촉 부재는 상기 접착 패드를 관통하는 나이프 에지로 형성된 돌출 정점을 포함하는 것을 특징으로 하는 상호접속부 제조 방법.
  12. 제7항에 있어서, 저항을 감소시키도록 상기 규화물층을 어닐링하는 단계를 추가로 포함하는 것을 특징으로 하는 상호접속부 제조 방법.
  13. 제7항에 있어서, 접착 와이어를 상기 도전성 트레이스에 부착하는 단계를 추가로 포함하는 것을 특징으로 하는 상호접속부 제조 방법.
  14. 제7항에 있어서, 단일 기판상에 복수의 상호 접속부를 형성하는 단계와 상기 상호접속부를 단일화시키는 단계를 추가로 포함하는 것을 특징으로 하는 상호접속부 제조 방법.
  15. 제7항에 있어서, 상기 도전성 트레이스는 알루미늄, 구리, 플래티늄, 텅스텐, 탄탈륨, 몰리브덴 및 이들 금속의 합금으로 이루어진 금속에서 선택된 금속으로부터 경화 공정에 의해 형성되는 것을 특징으로 하는 상호접속부 제조 방법.
  16. 제7항에 있어서, 상기 다이와 테스트 회로 사이에 일시적인 전기 접속을 설정하는 테스트 장치내에 상기 상호접속부를 위치시키는 단계를 추가로 포함하는 것을 특징으로 하는 상호접속부 제조 방법.
  17. 반도체 다이의 접착 패드와 전기 접촉을 설정하는 상호접속부를 형성하는 방법에 있어서；돌출 정점을 갖는 기판상에 상승 접촉 부재를 형성하는 단계와；상기 접촉 부재와 기판상에 제1절연층을 형성하는 단계와；상기 실리콘 함유층상에 제2절연층을 형성하는 단계와；상기 접촉 부재를 노출된 상태로 둘 때 상기 기판상에 마스크를 형성하는 단계와；상기 마스크를 사용하는 상기 접촉 부재상의 상기 제2절연층을 제거하는 단계와, 상기 마스크를 제거하는 단계와；상기 접촉 부재와 기판상에 금속층을 증착시키는 단계와；규화물층을 형성하도록 상기 금속층과 실리콘 함유층을 가열하는 단계와；상기 접촉 부재상에 규화물 팁을 형성하도록 상기 규화물층에 상기 금속층 및 상기 실리콘 함유층을 선택적으로 에칭하는 단계와；상기 제2절연층을 제거하는 단계와; 상기 규화물층과 접촉하는 도전성 트레이스를 형성하는 단계와; 상기 도전성 트레이스에 접착 와이어를 부착하는 단계를 포함하는 것을 특징으로 하는 상호접속부 형성 방법.
  18. 제17항에 있어서, 저항을 감소시키도록 상기 규화물층을 어닐링하는 단계를 추가로 포함하는 것을 특징으로 하는 상호접속부 형성 방법.
  19. 제17항에 있어서, 상기 돌출 정점은 상기 접착 패드로의 관통을 제한하는 정지면을 형성하기 위해 상기 접착 패드를 관통하는 나이프 에지로 형성되는 것을 특징으로 하는 상호접속부 형성 방법.
  20. 제17항에 있어서, 웨이퍼상에 복수의 상호접속부를 형성하고, 상기 상호접속부를 단일화하기 위해 상기`웨이퍼를 절단하는 단계를 추가로 포함하는 것을 특징으로 하는 상호접속부 형성 방법.
    ※ 참고사항：최초출원 내용에 의하여 공개하는 것임.
KR1019970703033A 1994-11-07 1995-11-06 노출된 반도체 다이스를 테스트하기 위한 자기 제한 실리콘베이스 상호접속부를 제조하는 방법 KR100285224B1 (ko)

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US08/335,267 1994-11-07
US08/335,267 US5483741A (en) 1993-09-03 1994-11-07 Method for fabricating a self limiting silicon based interconnect for testing bare semiconductor dice
US8/335,267 1994-11-07
PCT/US1995/014483 WO1996014660A1 (en) 1994-11-07 1995-11-06 Method for fabricating a self-limiting silicon based interconnect for testing bare semiconductor dice

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Families Citing this family (169)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5781022A (en) * 1991-06-04 1998-07-14 Micron Technology, Inc. Substrate having self limiting contacts for establishing an electrical connection with a semiconductor die
US5946553A (en) * 1991-06-04 1999-08-31 Micron Technology, Inc. Process for manufacturing a semiconductor package with bi-substrate die
US5686317A (en) * 1991-06-04 1997-11-11 Micron Technology, Inc. Method for forming an interconnect having a penetration limited contact structure for establishing a temporary electrical connection with a semiconductor die
US5519332A (en) * 1991-06-04 1996-05-21 Micron Technology, Inc. Carrier for testing an unpackaged semiconductor die
US5716218A (en) * 1991-06-04 1998-02-10 Micron Technology, Inc. Process for manufacturing an interconnect for testing a semiconductor die
US5495179A (en) * 1991-06-04 1996-02-27 Micron Technology, Inc. Carrier having interchangeable substrate used for testing of semiconductor dies
US5607818A (en) * 1991-06-04 1997-03-04 Micron Technology, Inc. Method for making interconnects and semiconductor structures using electrophoretic photoresist deposition
US5691649A (en) * 1991-06-04 1997-11-25 Micron Technology, Inc. Carrier having slide connectors for testing unpackaged semiconductor dice
US6828812B2 (en) * 1991-06-04 2004-12-07 Micron Technology, Inc. Test apparatus for testing semiconductor dice including substrate with penetration limiting contacts for making electrical connections
US5578934A (en) * 1991-06-04 1996-11-26 Micron Technology, Inc. Method and apparatus for testing unpackaged semiconductor dice
US5815000A (en) 1991-06-04 1998-09-29 Micron Technology, Inc. Method for testing semiconductor dice with conventionally sized temporary packages
US6340894B1 (en) 1991-06-04 2002-01-22 Micron Technology, Inc. Semiconductor testing apparatus including substrate with contact members and conductive polymer interconnect
US5578526A (en) * 1992-03-06 1996-11-26 Micron Technology, Inc. Method for forming a multi chip module (MCM)
US7368924B2 (en) 1993-04-30 2008-05-06 International Business Machines Corporation Probe structure having a plurality of discrete insulated probe tips projecting from a support surface, apparatus for use thereof and methods of fabrication thereof
US6528984B2 (en) 1996-09-13 2003-03-04 Ibm Corporation Integrated compliant probe for wafer level test and burn-in
US6414506B2 (en) 1993-09-03 2002-07-02 Micron Technology, Inc. Interconnect for testing semiconductor dice having raised bond pads
US5592736A (en) * 1993-09-03 1997-01-14 Micron Technology, Inc. Fabricating an interconnect for testing unpackaged semiconductor dice having raised bond pads
US6246247B1 (en) 1994-11-15 2001-06-12 Formfactor, Inc. Probe card assembly and kit, and methods of using same
US6624648B2 (en) 1993-11-16 2003-09-23 Formfactor, Inc. Probe card assembly
US20020053734A1 (en) 1993-11-16 2002-05-09 Formfactor, Inc. Probe card assembly and kit, and methods of making same
US5546012A (en) * 1994-04-15 1996-08-13 International Business Machines Corporation Probe card assembly having a ceramic probe card
US5854558A (en) * 1994-11-18 1998-12-29 Fujitsu Limited Test board for testing a semiconductor device and method of testing the semiconductor device
US6284563B1 (en) * 1995-10-31 2001-09-04 Tessera, Inc. Method of making compliant microelectronic assemblies
US6211572B1 (en) * 1995-10-31 2001-04-03 Tessera, Inc. Semiconductor chip package with fan-in leads
US6483328B1 (en) * 1995-11-09 2002-11-19 Formfactor, Inc. Probe card for probing wafers with raised contact elements
US5876580A (en) * 1996-01-12 1999-03-02 Micromodule Systems Rough electrical contact surface
US5869974A (en) * 1996-04-01 1999-02-09 Micron Technology, Inc. Micromachined probe card having compliant contact members for testing semiconductor wafers
US5838161A (en) * 1996-05-01 1998-11-17 Micron Technology, Inc. Semiconductor interconnect having test structures for evaluating electrical characteristics of the interconnect
US5982185A (en) * 1996-07-01 1999-11-09 Micron Technology, Inc. Direct connect carrier for testing semiconductor dice and method of fabrication
US6255833B1 (en) 1997-03-04 2001-07-03 Micron Technology, Inc. Method for testing semiconductor dice and chip scale packages
US6639416B1 (en) 1996-07-02 2003-10-28 Micron Technology, Inc. Method and apparatus for testing semiconductor dice
US5929647A (en) * 1996-07-02 1999-07-27 Micron Technology, Inc. Method and apparatus for testing semiconductor dice
US5693565A (en) * 1996-07-15 1997-12-02 Dow Corning Corporation Semiconductor chips suitable for known good die testing
US5789278A (en) * 1996-07-30 1998-08-04 Micron Technology, Inc. Method for fabricating chip modules
US5707881A (en) * 1996-09-03 1998-01-13 Motorola, Inc. Test structure and method for performing burn-in testing of a semiconductor product wafer
US7282945B1 (en) 1996-09-13 2007-10-16 International Business Machines Corporation Wafer scale high density probe assembly, apparatus for use thereof and methods of fabrication thereof
EP0925509B1 (en) 1996-09-13 2005-09-07 International Business Machines Corporation Probe structure having a plurality of discrete insulated probe tips
US5886414A (en) * 1996-09-20 1999-03-23 Integrated Device Technology, Inc. Removal of extended bond pads using intermetallics
US5783868A (en) * 1996-09-20 1998-07-21 Integrated Device Technology, Inc. Extended bond pads with a plurality of perforations
US6258609B1 (en) 1996-09-30 2001-07-10 Micron Technology, Inc. Method and system for making known good semiconductor dice
US5783461A (en) * 1996-10-03 1998-07-21 Micron Technology, Inc. Temporary semiconductor package having hard-metal, dense-array ball contacts and method of fabrication
US5801452A (en) * 1996-10-25 1998-09-01 Micron Technology, Inc. Multi chip module including semiconductor wafer or dice, interconnect substrate, and alignment member
US6037786A (en) * 1996-12-13 2000-03-14 International Business Machines Corporation Testing integrated circuit chips
US5952840A (en) * 1996-12-31 1999-09-14 Micron Technology, Inc. Apparatus for testing semiconductor wafers
US5834945A (en) 1996-12-31 1998-11-10 Micron Technology, Inc. High speed temporary package and interconnect for testing semiconductor dice and method of fabrication
US6060891A (en) * 1997-02-11 2000-05-09 Micron Technology, Inc. Probe card for semiconductor wafers and method and system for testing wafers
US6798224B1 (en) 1997-02-11 2004-09-28 Micron Technology, Inc. Method for testing semiconductor wafers
US5894161A (en) * 1997-02-24 1999-04-13 Micron Technology, Inc. Interconnect with pressure sensing mechanism for testing semiconductor wafers
US6040618A (en) 1997-03-06 2000-03-21 Micron Technology, Inc. Multi-chip module employing a carrier substrate with micromachined alignment structures and method of forming
US6025730A (en) 1997-03-17 2000-02-15 Micron Technology, Inc. Direct connect interconnect for testing semiconductor dice and wafers
US6025731A (en) * 1997-03-21 2000-02-15 Micron Technology, Inc. Hybrid interconnect and system for testing semiconductor dice
US6016060A (en) * 1997-03-25 2000-01-18 Micron Technology, Inc. Method, apparatus and system for testing bumped semiconductor components
US5929521A (en) * 1997-03-26 1999-07-27 Micron Technology, Inc. Projected contact structure for bumped semiconductor device and resulting articles and assemblies
US5962921A (en) * 1997-03-31 1999-10-05 Micron Technology, Inc. Interconnect having recessed contact members with penetrating blades for testing semiconductor dice and packages with contact bumps
FR2762140B1 (fr) * 1997-04-10 2000-01-14 Mesatronic Procede de fabrication d'une carte a pointes de contact multiple pour le test des puces semiconductrices
US6025728A (en) * 1997-04-25 2000-02-15 Micron Technology, Inc. Semiconductor package with wire bond protective member
US6004869A (en) 1997-04-25 1999-12-21 Micron Technology, Inc. Method for making a low resistivity electrode having a near noble metal
JPH10303252A (ja) * 1997-04-28 1998-11-13 Nec Kansai Ltd 半導体装置
US6414585B1 (en) 1997-05-13 2002-07-02 Chipscale, Inc. Integrated passive components and package with posts
US6051489A (en) * 1997-05-13 2000-04-18 Chipscale, Inc. Electronic component package with posts on the active side of the substrate
US5931685A (en) * 1997-06-02 1999-08-03 Micron Technology, Inc. Interconnect for making temporary electrical connections with bumped semiconductor components
US6040702A (en) 1997-07-03 2000-03-21 Micron Technology, Inc. Carrier and system for testing bumped semiconductor components
US6107122A (en) * 1997-08-04 2000-08-22 Micron Technology, Inc. Direct die contact (DDC) semiconductor package
US6072326A (en) * 1997-08-22 2000-06-06 Micron Technology, Inc. System for testing semiconductor components
US6040239A (en) * 1997-08-22 2000-03-21 Micron Technology, Inc. Non-oxidizing touch contact interconnect for semiconductor test systems and method of fabrication
US6329829B1 (en) 1997-08-22 2001-12-11 Micron Technology, Inc. Interconnect and system for making temporary electrical connections to semiconductor components
DE69721986T2 (de) 1997-08-27 2004-02-12 Imec Vzw Taststift-Konfiguration sowie Herstellungsverfahren und Verwendung von Taststiften
US6285201B1 (en) 1997-10-06 2001-09-04 Micron Technology, Inc. Method and apparatus for capacitively testing a semiconductor die
US5924003A (en) * 1997-11-14 1999-07-13 Kinetrix, Inc. Method of manufacturing ball grid arrays for improved testability
US6048750A (en) 1997-11-24 2000-04-11 Micron Technology, Inc. Method for aligning and connecting semiconductor components to substrates
US6028436A (en) 1997-12-02 2000-02-22 Micron Technology, Inc. Method for forming coaxial silicon interconnects
US6130148A (en) 1997-12-12 2000-10-10 Farnworth; Warren M. Interconnect for semiconductor components and method of fabrication
US6114240A (en) * 1997-12-18 2000-09-05 Micron Technology, Inc. Method for fabricating semiconductor components using focused laser beam
US6833613B1 (en) 1997-12-18 2004-12-21 Micron Technology, Inc. Stacked semiconductor package having laser machined contacts
US6107109A (en) 1997-12-18 2000-08-22 Micron Technology, Inc. Method for fabricating a semiconductor interconnect with laser machined electrical paths through substrate
US6620731B1 (en) * 1997-12-18 2003-09-16 Micron Technology, Inc. Method for fabricating semiconductor components and interconnects with contacts on opposing sides
DE19800574B4 (de) * 1998-01-09 2013-11-14 Robert Bosch Gmbh Mikromechanisches Bauelement
US6456100B1 (en) * 1998-01-20 2002-09-24 Micron Technology, Inc. Apparatus for attaching to a semiconductor
US6045026A (en) * 1998-02-23 2000-04-04 Micron Technology, Inc. Utilize ultrasonic energy to reduce the initial contact forces in known-good-die or permanent contact systems
JPH11237729A (ja) * 1998-02-24 1999-08-31 Oki Electric Ind Co Ltd マスクのペリクル構造、そのペリクルｉｄ識別装置及びそのペリクルｉｄ識別方法
US6181144B1 (en) 1998-02-25 2001-01-30 Micron Technology, Inc. Semiconductor probe card having resistance measuring circuitry and method fabrication
US6103613A (en) 1998-03-02 2000-08-15 Micron Technology, Inc. Method for fabricating semiconductor components with high aspect ratio features
US6217232B1 (en) 1998-03-24 2001-04-17 Micron Technology, Inc. Method and apparatus for aligning an optic fiber with an opto-electronic device
US6299456B1 (en) 1998-04-10 2001-10-09 Micron Technology, Inc. Interposer with contact structures for electrical testing
US6677776B2 (en) * 1998-05-11 2004-01-13 Micron Technology, Inc. Method and system having switching network for testing semiconductor components on a substrate
US6246250B1 (en) 1998-05-11 2001-06-12 Micron Technology, Inc. Probe card having on-board multiplex circuitry for expanding tester resources
US6337577B1 (en) 1998-05-11 2002-01-08 Micron Technology, Inc. Interconnect and system for testing bumped semiconductor components with on-board multiplex circuitry for expanding tester resources
US6239590B1 (en) 1998-05-26 2001-05-29 Micron Technology, Inc. Calibration target for calibrating semiconductor wafer test systems
US6164523A (en) * 1998-07-01 2000-12-26 Semiconductor Components Industries, Llc Electronic component and method of manufacture
US6369600B2 (en) * 1998-07-06 2002-04-09 Micron Technology, Inc. Test carrier for testing semiconductor components including interconnect with support members for preventing component flexure
US6758958B1 (en) * 1998-07-24 2004-07-06 Interuniversitair Micro-Elektronica Centrum System and a method for plating of a conductive pattern
US6235630B1 (en) * 1998-08-19 2001-05-22 Micron Technology, Inc. Silicide pattern structures and methods of fabricating the same
US6353326B2 (en) 1998-08-28 2002-03-05 Micron Technology, Inc. Test carrier with molded interconnect for testing semiconductor components
US6337575B1 (en) 1998-12-23 2002-01-08 Micron Technology, Inc. Methods of testing integrated circuitry, methods of forming tester substrates, and circuitry testing substrates
US6307394B1 (en) 1999-01-13 2001-10-23 Micron Technology, Inc. Test carrier with variable force applying mechanism for testing semiconductor components
US6242932B1 (en) 1999-02-19 2001-06-05 Micron Technology, Inc. Interposer for semiconductor components having contact balls
US6819127B1 (en) 1999-02-19 2004-11-16 Micron Technology, Inc. Method for testing semiconductor components using interposer
US6980017B1 (en) 1999-03-10 2005-12-27 Micron Technology, Inc. Test interconnect for bumped semiconductor components and method of fabrication
US6222280B1 (en) 1999-03-22 2001-04-24 Micron Technology, Inc. Test interconnect for semiconductor components having bumped and planar contacts
US6437591B1 (en) 1999-03-25 2002-08-20 Micron Technology, Inc. Test interconnect for bumped semiconductor components and method of fabrication
US6396291B1 (en) 1999-04-23 2002-05-28 Micron Technology, Inc. Method for testing semiconductor components
US6263566B1 (en) 1999-05-03 2001-07-24 Micron Technology, Inc. Flexible semiconductor interconnect fabricated by backslide thinning
US6365967B1 (en) * 1999-05-25 2002-04-02 Micron Technology, Inc. Interconnect structure
US6285203B1 (en) 1999-06-14 2001-09-04 Micron Technology, Inc. Test system having alignment member for aligning semiconductor components
US6297653B1 (en) 1999-06-28 2001-10-02 Micron Technology, Inc. Interconnect and carrier with resistivity measuring contacts for testing semiconductor components
US6556030B1 (en) * 1999-09-01 2003-04-29 Micron Technology, Inc. Method of forming an electrical contact
US6563215B1 (en) 2000-01-10 2003-05-13 Micron Technology, Inc. Silicon carbide interconnect for semiconductor components and method of fabrication
US6975030B1 (en) 2000-01-10 2005-12-13 Micron Technology, Inc. Silicon carbide contact for semiconductor components
US7033920B1 (en) * 2000-01-10 2006-04-25 Micron Technology, Inc. Method for fabricating a silicon carbide interconnect for semiconductor components
DE10001117A1 (de) * 2000-01-13 2001-07-26 Infineon Technologies Ag Testvorrichtung für ein Halbleiterbauelement
US6469394B1 (en) 2000-01-31 2002-10-22 Fujitsu Limited Conductive interconnect structures and methods for forming conductive interconnect structures
US6638831B1 (en) 2000-08-31 2003-10-28 Micron Technology, Inc. Use of a reference fiducial on a semiconductor package to monitor and control a singulation method
US6543674B2 (en) 2001-02-06 2003-04-08 Fujitsu Limited Multilayer interconnection and method
CN1647105B (zh) * 2002-04-16 2010-05-05 Nxp股份有限公司 数据载体用模块结构及带有该模块结构的数据载体
US20030204949A1 (en) * 2002-05-01 2003-11-06 Ultratera Corporation Method of forming connections on a conductor pattern of a printed circuit board
US6909300B2 (en) * 2002-05-09 2005-06-21 Taiwan Semiconductor Manufacturing Co., Ltd Method for fabricating microelectronic fabrication electrical test apparatus electrical probe tip having pointed tips
US7705349B2 (en) * 2002-08-29 2010-04-27 Micron Technology, Inc. Test inserts and interconnects with electrostatic discharge structures
US6982565B2 (en) * 2003-03-06 2006-01-03 Micron Technology, Inc. Test system and test method with interconnect having semiconductor spring contacts
US7597561B2 (en) * 2003-04-11 2009-10-06 Neoconix, Inc. Method and system for batch forming spring elements in three dimensions
US7114961B2 (en) * 2003-04-11 2006-10-03 Neoconix, Inc. Electrical connector on a flexible carrier
US7244125B2 (en) * 2003-12-08 2007-07-17 Neoconix, Inc. Connector for making electrical contact at semiconductor scales
US7628617B2 (en) * 2003-06-11 2009-12-08 Neoconix, Inc. Structure and process for a contact grid array formed in a circuitized substrate
US20070020960A1 (en) * 2003-04-11 2007-01-25 Williams John D Contact grid array system
US7113408B2 (en) * 2003-06-11 2006-09-26 Neoconix, Inc. Contact grid array formed on a printed circuit board
US20100167561A1 (en) * 2003-04-11 2010-07-01 Neoconix, Inc. Structure and process for a contact grid array formed in a circuitized substrate
US7758351B2 (en) * 2003-04-11 2010-07-20 Neoconix, Inc. Method and system for batch manufacturing of spring elements
US8584353B2 (en) * 2003-04-11 2013-11-19 Neoconix, Inc. Method for fabricating a contact grid array
US7056131B1 (en) 2003-04-11 2006-06-06 Neoconix, Inc. Contact grid array system
US20050120553A1 (en) * 2003-12-08 2005-06-09 Brown Dirk D. Method for forming MEMS grid array connector
US7042080B2 (en) * 2003-07-14 2006-05-09 Micron Technology, Inc. Semiconductor interconnect having compliant conductive contacts
US20050227510A1 (en) * 2004-04-09 2005-10-13 Brown Dirk D Small array contact with precision working range
US7142449B2 (en) * 2004-01-16 2006-11-28 Hewlett-Packard Development Company, L.P. Low temperature silicided tip
JP2005241275A (ja) * 2004-02-24 2005-09-08 Japan Electronic Materials Corp プローブカード
US7282932B2 (en) * 2004-03-02 2007-10-16 Micron Technology, Inc. Compliant contact pin assembly, card system and methods thereof
JP4723195B2 (ja) * 2004-03-05 2011-07-13 株式会社オクテック プローブの製造方法
US7347698B2 (en) * 2004-03-19 2008-03-25 Neoconix, Inc. Deep drawn electrical contacts and method for making
US7025601B2 (en) * 2004-03-19 2006-04-11 Neoconix, Inc. Interposer and method for making same
US20050205988A1 (en) * 2004-03-19 2005-09-22 Epic Technology Inc. Die package with higher useable die contact pad area
US7090503B2 (en) * 2004-03-19 2006-08-15 Neoconix, Inc. Interposer with compliant pins
US7383632B2 (en) * 2004-03-19 2008-06-10 Neoconix, Inc. Method for fabricating a connector
US20060000642A1 (en) * 2004-07-01 2006-01-05 Epic Technology Inc. Interposer with compliant pins
US7354276B2 (en) * 2004-07-20 2008-04-08 Neoconix, Inc. Interposer with compliant pins
US7109068B2 (en) * 2004-08-31 2006-09-19 Micron Technology, Inc. Through-substrate interconnect fabrication methods
US7371676B2 (en) * 2005-04-08 2008-05-13 Micron Technology, Inc. Method for fabricating semiconductor components with through wire interconnects
US7502606B2 (en) * 2005-04-11 2009-03-10 Microsoft Corporation Computer-readable medium, method, and device for associating information with a contact
US7393770B2 (en) * 2005-05-19 2008-07-01 Micron Technology, Inc. Backside method for fabricating semiconductor components with conductive interconnects
US7429529B2 (en) * 2005-08-05 2008-09-30 Farnworth Warren M Methods of forming through-wafer interconnects and structures resulting therefrom
US20070050738A1 (en) * 2005-08-31 2007-03-01 Dittmann Larry E Customer designed interposer
US7517798B2 (en) 2005-09-01 2009-04-14 Micron Technology, Inc. Methods for forming through-wafer interconnects and structures resulting therefrom
US7307348B2 (en) * 2005-12-07 2007-12-11 Micron Technology, Inc. Semiconductor components having through wire interconnects (TWI)
US7357644B2 (en) * 2005-12-12 2008-04-15 Neoconix, Inc. Connector having staggered contact architecture for enhanced working range
WO2007124113A2 (en) * 2006-04-21 2007-11-01 Neoconix, Inc. Clamping a flat flex cable and spring contacts to a circuit board
US7659612B2 (en) 2006-04-24 2010-02-09 Micron Technology, Inc. Semiconductor components having encapsulated through wire interconnects (TWI)
CN101164863B (zh) * 2006-10-20 2012-06-13 精工爱普生株式会社 Mems器件及其制造方法
JP4737140B2 (ja) * 2006-10-20 2011-07-27 セイコーエプソン株式会社 Ｍｅｍｓデバイスおよびその製造方法
JP2009194196A (ja) * 2008-02-15 2009-08-27 Nec Electronics Corp 半導体装置の製造方法および半導体装置
US8119576B2 (en) * 2008-10-10 2012-02-21 Halliburton Energy Services, Inc. Ceramic coated particulates
US8641428B2 (en) 2011-12-02 2014-02-04 Neoconix, Inc. Electrical connector and method of making it
JP5702416B2 (ja) * 2012-07-11 2015-04-15 本田技研工業株式会社 電流印加装置
DE102013215771B4 (de) * 2012-08-10 2019-06-13 Smartrac Technology Gmbh Kontakthöckerverbindung sowie Kontakthöcker und Verfahren zur Herstellung einer Kontakthöckerverbindung und Anwendung des Verfahrens zur Herstellung eines einen Chip und eine Antenne umfassenden Transponders
US9711424B2 (en) * 2012-09-17 2017-07-18 Littelfuse, Inc. Low thermal stress package for large area semiconductor dies
US9494618B2 (en) * 2012-12-26 2016-11-15 Translarity, Inc. Designed asperity contactors, including nanospikes, for semiconductor test using a package, and associated systems and methods
US9680273B2 (en) 2013-03-15 2017-06-13 Neoconix, Inc Electrical connector with electrical contacts protected by a layer of compressible material and method of making it
US9391040B2 (en) 2014-10-17 2016-07-12 International Business Machines Corporation Planarity-tolerant reworkable interconnect with integrated testing
US9577358B2 (en) * 2014-10-25 2017-02-21 ComponentZee, LLC Fluid pressure activated electrical contact devices and methods
US10003149B2 (en) 2014-10-25 2018-06-19 ComponentZee, LLC Fluid pressure activated electrical contact devices and methods
KR102523979B1 (ko) 2018-02-14 2023-04-21 삼성디스플레이 주식회사 표시 장치
US11525739B2 (en) * 2018-05-08 2022-12-13 Texas Instruments Incorporated Thermistor die-based thermal probe
EP4022671A4 (en) * 2019-08-29 2023-09-27 HRL Laboratories LLC INTEGRATED CUTTING EDGE WITH LOW INCLINE FOR TEMPORARY CONNECTING MICROSTRUCTURES

Family Cites Families (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4312117A (en) * 1977-09-01 1982-01-26 Raytheon Company Integrated test and assembly device
US4585991A (en) * 1982-06-03 1986-04-29 Texas Instruments Incorporated Solid state multiprobe testing apparatus
US4754316A (en) * 1982-06-03 1988-06-28 Texas Instruments Incorporated Solid state interconnection system for three dimensional integrated circuit structures
JPS60198838A (ja) * 1984-03-23 1985-10-08 Nec Corp プロ−ブカ−ド
CA1312952C (en) * 1987-09-24 1993-01-19 Hisaaki Kawade Microprobe, preparation thereof and electronic device by use of said microprobe
US4924589A (en) * 1988-05-16 1990-05-15 Leedy Glenn J Method of making and testing an integrated circuit
US5323035A (en) * 1992-10-13 1994-06-21 Glenn Leedy Interconnection structure for integrated circuits and method for making same
US5103557A (en) * 1988-05-16 1992-04-14 Leedy Glenn J Making and testing an integrated circuit using high density probe points
JPH0817192B2 (ja) * 1988-05-30 1996-02-21 株式会社日立製作所 半導体ｌｓｉ検査装置用プローブヘッドの製造方法
US4937653A (en) * 1988-07-21 1990-06-26 American Telephone And Telegraph Company Semiconductor integrated circuit chip-to-chip interconnection scheme
US5408190A (en) * 1991-06-04 1995-04-18 Micron Technology, Inc. Testing apparatus having substrate interconnect for discrete die burn-in for nonpackaged die
US4899107A (en) * 1988-09-30 1990-02-06 Micron Technology, Inc. Discrete die burn-in for nonpackaged die
US5073117A (en) * 1989-03-30 1991-12-17 Texas Instruments Incorporated Flip-chip test socket adaptor and method
JPH0369131A (ja) * 1989-08-08 1991-03-25 Fujitsu Ltd 半導体集積回路試験用プローブおよび該プローブを用いる試験工程を含む半導体装置の製造方法
US4943343A (en) * 1989-08-14 1990-07-24 Zaher Bardai Self-aligned gate process for fabricating field emitter arrays
DE68903951T2 (de) * 1989-08-16 1993-07-08 Ibm Verfahren fuer die herstellung mikromechanischer messfuehler fuer afm/stm-profilometrie und mikromechanischer messfuehlerkopf.
US4963225A (en) * 1989-10-20 1990-10-16 Tektronix, Inc. Method of fabricating a contact device
US5123850A (en) * 1990-04-06 1992-06-23 Texas Instruments Incorporated Non-destructive burn-in test socket for integrated circuit die
US5088190A (en) * 1990-08-30 1992-02-18 Texas Instruments Incorporated Method of forming an apparatus for burn in testing of integrated circuit chip
US5207585A (en) * 1990-10-31 1993-05-04 International Business Machines Corporation Thin interface pellicle for dense arrays of electrical interconnects
US5116460A (en) * 1991-04-12 1992-05-26 Motorola, Inc. Method for selectively etching a feature
US5173451A (en) * 1991-06-04 1992-12-22 Micron Technology, Inc. Soft bond for semiconductor dies
US5302891A (en) * 1991-06-04 1994-04-12 Micron Technology, Inc. Discrete die burn-in for non-packaged die
US5177438A (en) * 1991-08-02 1993-01-05 Motorola, Inc. Low resistance probe for semiconductor
US5177439A (en) * 1991-08-30 1993-01-05 U.S. Philips Corporation Probe card for testing unencapsulated semiconductor devices
US5326428A (en) * 1993-09-03 1994-07-05 Micron Semiconductor, Inc. Method for testing semiconductor circuitry for operability and method of forming apparatus for testing semiconductor circuitry for operability
US5419807A (en) * 1993-09-03 1995-05-30 Micron Technology, Inc. Method of providing electrical interconnect between two layers within a silicon substrate, semiconductor apparatus, and method of forming apparatus for testing semiconductor circuitry for operability

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AU4232396A (en) 1996-05-31
KR100285224B1 (ko) 2001-04-02
EP0792518B1 (en) 2003-04-23
ATE238606T1 (de) 2003-05-15
US5483741A (en) 1996-01-16
JP3195359B2 (ja) 2001-08-06
DE69530509D1 (de) 2003-05-28
WO1996014660A1 (en) 1996-05-17
DE69530509T2 (de) 2004-03-04
EP0792518A1 (en) 1997-09-03
JPH10506196A (ja) 1998-06-16

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