KR970072313A - 반도체 금속박막의 배선방법 - Google Patents

반도체 금속박막의 배선방법 Download PDF

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Publication number
KR970072313A
KR970072313A KR1019960010174A KR19960010174A KR970072313A KR 970072313 A KR970072313 A KR 970072313A KR 1019960010174 A KR1019960010174 A KR 1019960010174A KR 19960010174 A KR19960010174 A KR 19960010174A KR 970072313 A KR970072313 A KR 970072313A
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South Korea
Prior art keywords
thin film
vapor deposition
chemical vapor
tungsten nitride
film
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KR1019960010174A
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English (en)
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KR100215540B1 (ko
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민석기
김용태
권철순
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김은영
한국과학기술연구원
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Priority to KR1019960010174A priority Critical patent/KR100215540B1/ko
Publication of KR970072313A publication Critical patent/KR970072313A/ko
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Publication of KR100215540B1 publication Critical patent/KR100215540B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 금속박막의 배선방법에 관한 것으로, 저압 화학 기상 증착법 또는 플라즈마 화학 기상중착법에 의해 질화 텅스텐 박막을 확산방지막으로 하여 구리로 중착시키도록 한 것이다.
이러한 금속배선방법은 먼저 기판(3)상에 플라즈마 화학증착법으로 질화 텅스텐 확산 방지막(7)을 도포하고, 금속층(1) (6)인 Cu를 중착시키며, 접촉상으로서의 비아콘택 영역(5)과 금속층(1)을 연결시킬 때는 역시 플리즈마 화학중착법으로 중착된 질화 텅스텐 박막을 확산방지막으로 사용하여 금속배선하도록 한 것으로, 확산방지막인 질화 텅스텐 박막은 실리콘 기판(3)과 금속층(1)이 접촉되는 콘택 영역(2), 금속층(1) (6)과 절연막 (4)사이, 금속층(1) (6)이 접촉되는 비아콘택 영역(5)에 적용되는 것이다. 이와 같이 Cu 확산방지를 위한 확산방지막으로 텅스텐 질화박막이 우수한 특성을 지님을 알 수 있다.

Description

반도체 금속박막의 배선방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 의한 반도체 금속박막의 배선방법에 의해 형성된 텅스텐 질화박막을 적용한 배선 단면도.

Claims (3)

  1. 기판의 금속층을 배선하기 전에 화학 기상 증착법으로 질화 텅스텐 박막을 사전에 도포한 후 구리를 중착시키도록 한 것을 특징으로 하는 반도체 금속박막의 배선방법.
  2. 제1항에 있어서, 상기 화학 기상 증착법은 저압 화학 기상 중착법인 것을 특징으로 하는 반도체 금속박막의 배선방법.
  3. 제1항에 있어서, 상기 화확 기상 증착법은 플라즈마 화학 기상 증착법인 것을 특징으로 하는 반도체 금속박막의 배선방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개되는 것임.
KR1019960010174A 1996-04-04 1996-04-04 반도체 금속박막의 배선방법 KR100215540B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019960010174A KR100215540B1 (ko) 1996-04-04 1996-04-04 반도체 금속박막의 배선방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019960010174A KR100215540B1 (ko) 1996-04-04 1996-04-04 반도체 금속박막의 배선방법

Publications (2)

Publication Number Publication Date
KR970072313A true KR970072313A (ko) 1997-11-07
KR100215540B1 KR100215540B1 (ko) 1999-08-16

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980060532A (ko) * 1996-12-31 1998-10-07 김영환 반도체 소자의 금속 배선 형성 방법
KR100301057B1 (ko) * 1999-07-07 2001-11-01 윤종용 구리 배선층을 갖는 반도체 소자 및 그 제조방법

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR19980060532A (ko) * 1996-12-31 1998-10-07 김영환 반도체 소자의 금속 배선 형성 방법
KR100301057B1 (ko) * 1999-07-07 2001-11-01 윤종용 구리 배선층을 갖는 반도체 소자 및 그 제조방법

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Publication number Publication date
KR100215540B1 (ko) 1999-08-16

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