KR970063504A - 반도체 장치 제조 방법 및 제조 장치 - Google Patents
반도체 장치 제조 방법 및 제조 장치 Download PDFInfo
- Publication number
- KR970063504A KR970063504A KR1019970003533A KR19970003533A KR970063504A KR 970063504 A KR970063504 A KR 970063504A KR 1019970003533 A KR1019970003533 A KR 1019970003533A KR 19970003533 A KR19970003533 A KR 19970003533A KR 970063504 A KR970063504 A KR 970063504A
- Authority
- KR
- South Korea
- Prior art keywords
- semiconductor device
- electrode
- wiring
- forming
- polishing
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 238000005498 polishing Methods 0.000 claims abstract description 10
- 239000000126 substance Substances 0.000 claims abstract 5
- 239000003792 electrolyte Substances 0.000 claims abstract 2
- 239000000758 substrate Substances 0.000 claims abstract 2
- 239000002245 particle Substances 0.000 claims 5
- 238000000034 method Methods 0.000 claims 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims 1
- 229910052799 carbon Inorganic materials 0.000 claims 1
- 229910003460 diamond Inorganic materials 0.000 claims 1
- 239000010432 diamond Substances 0.000 claims 1
- 239000008151 electrolyte solution Substances 0.000 claims 1
- 238000007517 polishing process Methods 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
- B23H—WORKING OF METAL BY THE ACTION OF A HIGH CONCENTRATION OF ELECTRIC CURRENT ON A WORKPIECE USING AN ELECTRODE WHICH TAKES THE PLACE OF A TOOL; SUCH WORKING COMBINED WITH OTHER FORMS OF WORKING OF METAL
- B23H5/00—Combined machining
- B23H5/06—Electrochemical machining combined with mechanical working, e.g. grinding or honing
- B23H5/08—Electrolytic grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
- H01L21/32125—Planarisation by chemical mechanical polishing [CMP] by simultaneously passing an electrical current, i.e. electrochemical mechanical polishing, e.g. ECMP
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/7684—Smoothing; Planarisation
Landscapes
- Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Electrochemistry (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Mechanical Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Thin Film Transistor (AREA)
- Weting (AREA)
Abstract
기판 상에 제1배선 또는 전극을 형성하고; 제1배선 또는 전극을 덮는 절연막을 형성하고; 이 절연막을 통하여 제1배선 또는 전극에 콘택홀을 형성하고; 이 콘택홀 내부에 제1배선 또는 전극을 접촉시키는 배선을 형성하고; 및 전해액에서 상기 콘택트 배선을 양극으로 사용하는 화학 기계 연마 수단으로 상기 콘택 배선의 돌출부를 제거함과 동시에 절연막을 평탄화시키는 단계를 포함하는, 다층 배선 구조를 가지는 반도체 장치를 제조하는 방법이 개시되어 있다. 반도체 장치를 제조하는 동안 반도체 장치의 표면을 기계적으로 연마하는 수단; 및 반도체 장치의 전극에 전류를 인가하는 수단을 포함하는, 반도체 장치를 제조하는 장치가 또한 개시되어 있다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1(a)도 내지 제1(d)도는 본 발명의 구체예에 따른, 다층 배선을 가지는 반도체 장치를 제조하는 방법을 도식적으로 나타낸다.
제2도는 본 발명의 구체예에 따른, 반도체 장치를 연마하는 장치를 도식적으로 나타낸다.
Claims (7)
- 기판 상에 제1배선 또는 전극을 형성하는 단계; 상기 제1배선 또는 전극을 덮는 절연막을 형성하는 단계; 상기 절연막을 통하여 상기 제1배선 또는 전극에 콘택홀을 형성하는 단계; 상기 콘택홀 내부에 상기 제1배선 또는 전극을 접촉하기 위한 배선을 형성하는 단계; 및 전해액 내에서 상기 콘택 배선을 양극으로 사용하는 화학 기계적 연마 수단으로 상기 콘택 배선의 돌출부를 제거함과 동시에 상기 절연막을 평탄화하는 단계를 포함하는, 다층 배선을 가지는 반도체 장치 제조 방법.
- 제1항에 있어서, 상기 전해액의 전기 저항은 10-3내지 1010(cm)의 범위에 있는 것을 특징으로 하는 방법.
- 제1항에 있어서, 상기 화학 기계적 연마용으로 수 4,000 내지 10,000 범위에 있는 과립도를 가지는 전기적 비도전 입자를 사용하는 것을 특징으로 하는 방법.
- 제3항에 있어서 상기 전기적 비도전 입자는 다이아몬드 입자, 알루미나 입자, 탄소 입자 및 실리카 입자 중에서 선택한 것을 특징으로 하는 방법.
- 반도체 장치의 제조 중에 반도체 장치의 표면을 연마하는 방법에 있어서, 반도체 장치의 전극을 양극으로서 사용하여 전해 연마를 실시함과 동시에 화학 기계 연마를 실시하는 것을 포함하는 것을 특징으로 하는 방법.
- 반도체 장치의 제조 중에 반도체 장치의 표면을 기계적으로 연마하는 수단; 및 상기 반도체 장치의 전극에 전류를 인가하는 수단을 포함하는 반도체 장치 제조 장치.
- 반도체 장치 제조 중에 반도체 장치의 표면을 연마하는 장치에 있어서, 화학 기계 연마를 수행하는 수단; 및 상기 반도체 장치의 전극에 전류를 인가하는 수단을 포함하는 것을 특징으로 하는 장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP04214996A JP4204649B2 (ja) | 1996-02-05 | 1996-02-05 | 半導体装置の作製方法 |
JP96-42149 | 1996-02-05 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR970063504A true KR970063504A (ko) | 1997-09-12 |
KR100484607B1 KR100484607B1 (ko) | 2005-08-24 |
Family
ID=12627894
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019970003533A KR100484607B1 (ko) | 1996-02-05 | 1997-02-05 | 반도체장치제조방법 |
Country Status (3)
Country | Link |
---|---|
US (2) | US6242343B1 (ko) |
JP (1) | JP4204649B2 (ko) |
KR (1) | KR100484607B1 (ko) |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4204649B2 (ja) * | 1996-02-05 | 2009-01-07 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
KR100456394B1 (ko) * | 1997-07-08 | 2005-04-06 | 삼성전자주식회사 | 반도체제조장치및이를채용한반도체소자의배선형성방법 |
US7202497B2 (en) * | 1997-11-27 | 2007-04-10 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
JP4014710B2 (ja) | 1997-11-28 | 2007-11-28 | 株式会社半導体エネルギー研究所 | 液晶表示装置 |
US6646639B1 (en) | 1998-07-22 | 2003-11-11 | Nvidia Corporation | Modified method and apparatus for improved occlusion culling in graphics systems |
KR100537207B1 (ko) * | 1999-06-30 | 2005-12-16 | 주식회사 하이닉스반도체 | 불활성금속의 화학적 기계적 연마방법 |
JP4513145B2 (ja) * | 1999-09-07 | 2010-07-28 | ソニー株式会社 | 半導体装置の製造方法および研磨方法 |
US6299741B1 (en) * | 1999-11-29 | 2001-10-09 | Applied Materials, Inc. | Advanced electrolytic polish (AEP) assisted metal wafer planarization method and apparatus |
US6844880B1 (en) | 1999-12-06 | 2005-01-18 | Nvidia Corporation | System, method and computer program product for an improved programmable vertex processing model with instruction set |
US6294470B1 (en) * | 1999-12-22 | 2001-09-25 | International Business Machines Corporation | Slurry-less chemical-mechanical polishing |
US6797623B2 (en) * | 2000-03-09 | 2004-09-28 | Sony Corporation | Methods of producing and polishing semiconductor device and polishing apparatus |
JP4644954B2 (ja) * | 2000-03-09 | 2011-03-09 | ソニー株式会社 | 研磨装置 |
US6972223B2 (en) * | 2001-03-15 | 2005-12-06 | Micron Technology, Inc. | Use of atomic oxygen process for improved barrier layer |
JP4841751B2 (ja) * | 2001-06-01 | 2011-12-21 | 株式会社半導体エネルギー研究所 | 有機半導体装置及びその作製方法 |
US7456838B1 (en) | 2001-06-08 | 2008-11-25 | Nvidia Corporation | System and method for converting a vertex program to a binary format capable of being executed by a hardware graphics pipeline |
US7006101B1 (en) | 2001-06-08 | 2006-02-28 | Nvidia Corporation | Graphics API with branching capabilities |
US6885146B2 (en) | 2002-03-14 | 2005-04-26 | Semiconductor Energy Laboratory Co., Ltd. | Display device comprising substrates, contrast medium and barrier layers between contrast medium and each of substrates |
JP2003311539A (ja) * | 2002-04-30 | 2003-11-05 | Sony Corp | 研磨方法および研磨装置、並びに半導体装置の製造方法 |
US20030209523A1 (en) * | 2002-05-09 | 2003-11-13 | Applied Materials, Inc. | Planarization by chemical polishing for ULSI applications |
US6821811B2 (en) * | 2002-08-02 | 2004-11-23 | Semiconductor Energy Laboratory Co., Ltd. | Organic thin film transistor and method of manufacturing the same, and semiconductor device having the organic thin film transistor |
US6739953B1 (en) * | 2003-04-09 | 2004-05-25 | Lsi Logic Corporation | Mechanical stress free processing method |
US6927177B2 (en) * | 2003-10-24 | 2005-08-09 | Lsi Logic Corporation | Chemical mechanical electropolishing system |
US20050087450A1 (en) * | 2003-10-24 | 2005-04-28 | Reder Steven E. | Electropolishing pad |
US20050128385A1 (en) * | 2003-12-12 | 2005-06-16 | Hong-Da Liu | Pixel structure for a liquid crystal on silicon display |
US20060046932A1 (en) * | 2004-08-31 | 2006-03-02 | Eastman Kodak Company | Thermally developable materials with backside conductive layer |
JP2006093191A (ja) * | 2004-09-21 | 2006-04-06 | Konica Minolta Holdings Inc | 有機薄膜トランジスタ、有機薄膜トランジスタシート及びこれらの製造方法 |
JP4667096B2 (ja) * | 2005-03-25 | 2011-04-06 | 株式会社半導体エネルギー研究所 | 有機半導体装置及びその作製方法 |
US9431545B2 (en) | 2011-09-23 | 2016-08-30 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
JP5912394B2 (ja) | 2011-10-13 | 2016-04-27 | 株式会社半導体エネルギー研究所 | 半導体装置 |
US8637864B2 (en) | 2011-10-13 | 2014-01-28 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method of manufacturing the same |
JP6053490B2 (ja) | 2011-12-23 | 2016-12-27 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0781132B2 (ja) * | 1990-08-29 | 1995-08-30 | 株式会社フジミインコーポレーテッド | 研磨剤組成物 |
US5562529A (en) * | 1992-10-08 | 1996-10-08 | Fujitsu Limited | Apparatus and method for uniformly polishing a wafer |
US5616934A (en) * | 1993-05-12 | 1997-04-01 | Micron Technology, Inc. | Fully planarized thin film transistor (TFT) and process to fabricate same |
US5391258A (en) * | 1993-05-26 | 1995-02-21 | Rodel, Inc. | Compositions and methods for polishing |
JPH07130848A (ja) | 1993-11-08 | 1995-05-19 | Kawasaki Steel Corp | 半導体装置の製造方法 |
JP3836166B2 (ja) | 1993-11-22 | 2006-10-18 | 株式会社半導体エネルギー研究所 | 2層構造のトランジスタおよびその作製方法 |
US5567300A (en) * | 1994-09-02 | 1996-10-22 | Ibm Corporation | Electrochemical metal removal technique for planarization of surfaces |
JP2864464B2 (ja) | 1994-12-22 | 1999-03-03 | 日本ビクター株式会社 | 反射型アクティブ・マトリクス・ディスプレイ・パネル及びその製造方法 |
JP3108861B2 (ja) | 1995-06-30 | 2000-11-13 | キヤノン株式会社 | アクティブマトリクス基板、該基板を用いた表示装置、及びこれらの製造方法 |
US5658806A (en) * | 1995-10-26 | 1997-08-19 | National Science Council | Method for fabricating thin-film transistor with bottom-gate or dual-gate configuration |
US5575706A (en) * | 1996-01-11 | 1996-11-19 | Taiwan Semiconductor Manufacturing Company Ltd. | Chemical/mechanical planarization (CMP) apparatus and polish method |
JP4204649B2 (ja) * | 1996-02-05 | 2009-01-07 | 株式会社半導体エネルギー研究所 | 半導体装置の作製方法 |
US5807165A (en) * | 1997-03-26 | 1998-09-15 | International Business Machines Corporation | Method of electrochemical mechanical planarization |
-
1996
- 1996-02-05 JP JP04214996A patent/JP4204649B2/ja not_active Expired - Fee Related
-
1997
- 1997-02-05 US US08/794,879 patent/US6242343B1/en not_active Expired - Lifetime
- 1997-02-05 KR KR1019970003533A patent/KR100484607B1/ko not_active IP Right Cessation
-
2001
- 2001-05-24 US US09/866,322 patent/US6551934B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US6551934B2 (en) | 2003-04-22 |
US6242343B1 (en) | 2001-06-05 |
JPH09213803A (ja) | 1997-08-15 |
JP4204649B2 (ja) | 2009-01-07 |
US20010029098A1 (en) | 2001-10-11 |
KR100484607B1 (ko) | 2005-08-24 |
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