KR970058406A - 회로 기판 및 그의 제조 방법 - Google Patents

회로 기판 및 그의 제조 방법 Download PDF

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Publication number
KR970058406A
KR970058406A KR1019960046024A KR19960046024A KR970058406A KR 970058406 A KR970058406 A KR 970058406A KR 1019960046024 A KR1019960046024 A KR 1019960046024A KR 19960046024 A KR19960046024 A KR 19960046024A KR 970058406 A KR970058406 A KR 970058406A
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South Korea
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electrically conductive
dielectric
layer
material layer
dielectric material
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KR1019960046024A
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KR100240915B1 (ko
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아닐쿠마르 치누프라사드 브하트
아쉬윈쿠마르 치누프라사드 브하트
로버트 제프리 대이
토마스 패트릭 두피
제프리 알란 나이트
리차드 윌리암 말렉
보야 리스타 마르코비츠
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포만 제프리 엘
인터내셔널 비지네스 머신즈 코포레이션
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Publication of KR970058406A publication Critical patent/KR970058406A/ko
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Publication of KR100240915B1 publication Critical patent/KR100240915B1/ko

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0263—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
    • H05K1/0265—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board characterized by the lay-out of or details of the printed conductors, e.g. reinforced conductors, redundant conductors, conductors having different cross-sections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/428—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in substrates having a metal pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0263—High current adaptations, e.g. printed high current conductors or using auxiliary non-printed means; Fine and coarse circuit patterns on one circuit board
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/03—Conductive materials
    • H05K2201/0332—Structure of the conductor
    • H05K2201/0335—Layered conductors or foils
    • H05K2201/0347—Overplating, e.g. for reinforcing conductors or bumps; Plating over filled vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09727—Varying width along a single conductor; Conductors or pads having different widths
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0353—Making conductive layer thin, e.g. by etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/072—Electroless plating, e.g. finish plating or initial plating
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/14—Related to the order of processing steps
    • H05K2203/1407—Applying catalyst before applying plating resist
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H05K3/064—Photoresists
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S428/00—Stock material or miscellaneous articles
    • Y10S428/901—Printed circuit
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24273—Structurally defined web or sheet [e.g., overall dimension, etc.] including aperture
    • Y10T428/24322—Composite web or sheet
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/24—Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24802—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.]
    • Y10T428/24917—Discontinuous or differential coating, impregnation or bond [e.g., artwork, printing, retouched photograph, etc.] including metal layer

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)

Abstract

기판이 2개의 다른 금소고하 프로세스, 예를 들면 가법 및 감법 금속화 프로세스로 처리되는 회로 기판을 제조하는 프로세스가 정의된다. 따라서 이 프로세스는 비용이 적게 들고 신속한 방식으로 2개의 상이한 해상도를 갖는 전도 형상부, 예를 들면 고 밀도 회로 라인과 칩 열흡수 패드를 포함하는 기판을 효과적으로 제작할 수 있다. 결과적인 물품이 또한 정의된다.

Description

회로 기판 및 그의 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제8도는 본 발명의 1 실시예에 따라 회로 기판을 제조하는 여로 단계를 도시한 도면도.

Claims (21)

  1. 회로 기판을 제조하는 방법에 있어서, ① 그 위에 전기적 전도 재료로 된 제1층을 구비하는 유전체 부재를 제공하는 단계와 ② 제1금속화 프로세스를 이용하여 상기 제1전기적 전도 재료 층으로부터 상기 유전체 부재상에 제1전기적 전도 부재를 형성하는 단계와 ③ 상기 유전체 부재상에 그 안에 적어도 1개의 구멍을 구비하는 절연체 재료로 된 제1층을 제공하는 단계와 ④ 상기 제1금속화 프로세스와는 다른 제2금속화 프로세스를 이용하여 상기 제1유전체 재료 층의 상기 구멍내에 제2전기적 전도 부재를 형성하는 단계를 포함하는 회로 기판 제조 방법.
  2. 제1항에 있어서, 상기 제2전기적 전도 부재는 상기 제1전기적 전도 부재보다 더 큰 해상도로 제공되는 회로 기판 제조 방법.
  3. 제1항에 있어서, 상기 제1전기적 전도 재료는 적층 프로세스를 이용하여 상기 유전체 부재상에 위치된 회로 기판 제조 방법.
  4. 제1항에 있어서, 상기 제1금속화 프로세스는 감법 금속화 프로세스이고, 상기 제2금속화 프로세스는 가법 금속화 프로세스인 회로 기판 제조 방법.
  5. 제4항에 있어서, 상기 감법 금속화 프로세스는 상기 제1전기적 전도 재료 층상에 제2유전체 재료 층을 위치시키는 단계, 상기 제1유전체 재료 층의 선택된 영역을 제거하여 상기 제1전기적 전도 부재를 형성하지 않는 상기 제1전기적 전도 재료 층의 영역을 노출하는 단계, 상기 제1전기적 전도 재료 층의 상기 노출된 영역을 제거하는 단계를 포함하는 회로 기판 제조 방법.
  6. 제5항에 있어서, 상기 제2유전체 재료 층은 박판형태(sheetlike)로 상기 제1전기적 전도재료 층상에 위치된 회로 기판 제조 방법.
  7. 제5항에 있어서, 상기 제1전기적 전도 재료 층의 상기 노출된 영역은 에칭 프로세스를 이용하여 제거되는 회로 기판 제조 방법.
  8. 제5항에 있어서, 상기 제2유전체 재료 층은 포토레지스트 재료로 이루어지되, 상기 ㅣ제2유전체 재료 층의 상기 선택된 영역을 제거하는 단계는 상기 포토레지스트의 선택된 영역이 노출되는 노출 프로세스의 상기 노출된 선택 영역이 제거되는 현상 프로세스를 이용하여 달성되는 회로 기판 제조 방법.
  9. 제5항에 있어서, 상기 제2유전체 재료 층을 위치시키는 단계전에 상기 유전체 부재에 상기 제2유전체 재료 층에 의해 덮히는 적어도 한 개의 스로우 홀을 제공하는 단계를 더 포함하는 회로 기판 제조 방법.
  10. 제4항에 있어서, 상기 가법 금속화 프로세스는 상기 제1유전체 재료 층의 상기 구멍내에 제2전기적 전도체 재료 층을 침착한 후 상기 제1유전체 재료 층을 제거하는 단계를 포함하는 회로 기판 제조 방법.
  11. 제10항에 있어서, 상기 제2전기적 전도 재료 층을 침착하는 상기 단계는 무전해 도금 프로세스를 이용하여 달성되는 회로 기판 제조 방법.
  12. 제11항에 있어서, 상기 무전해 도금 프로세스는 상기 유전체 재료가 다수의 상이한 용액내에 담금질되는 다수의 담금 단계와 다음의 상기 유전체 부재가 실질적으로 건조되는 건조 단계를 포함하는 회로 기판 제조 방법.
  13. 제10항에 있어서, 상기 제1유전체 재료 층은 포토레지스트 재료로 이루어지되, 상기 ㅣ제1층의 제거는 벗기기 프로세스를 이용하여 달성되는 회로 기판 제조 방법.
  14. 제1항에 있어서, 상기 제2전기적 전도 부재를 평탄화하는 단계를 더 포함하는 회로 기판 제조 방법.
  15. 제14항에 있어서, 상기 평탄화 단계는 기계적 프로세스를 이용하여 달성되는 회로 기판 제조 방법.
  16. 제15항에 있어서, 상기 기계적 프로세스는 사포질(sanding)인 회로 기판 제조 방법.
  17. 제1항에 있어서, 상기 제1전기적 전도 부재를 형성하기 전에 상기 유전체 부재내에 적어도 1개의 스로우홀을 제공하는 단계를 더 포함하는 회로 기판 제조 방법.
  18. 제17항에 있어서, 상기 적어도 1개의 스로우 홀은 드릴링 프로세스를 이용하여 제공되는 회로 기판 제조 방법.
  19. 회로 기판에 있어서, ① 유전체 부재와 ② 제1해상도를 갖는 상기 유전체 부재상의 제1전기적 전도 부재와 ③ 그 안에 구멍을 갖는 상기 유전체 부재상의 유전체 재료 층 ④ 상기 제1해상도보다 큰 제2해상도를 갖는, 실질적으로 상기 유전체 재료 층의 상기 구멍내에 위치된 제2전기적 전도 부재를 포함하는 회로 기판.
  20. 제19항에 있어서, 상기 유전체 광섬유유리-보강된 에폭시 수지로 이루어진 회로 기판.
  21. 제19항에 있어서, 상기 제1 및 제2전도 부재는 구리로 이루어진 회로 기판.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960046024A 1995-12-01 1996-10-15 회로 기판 및 그의 제조 방법 KR100240915B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US08/566,363 US5707893A (en) 1995-12-01 1995-12-01 Method of making a circuitized substrate using two different metallization processes
US8/566,363 1995-12-01
US08/566,363 1995-12-01

Publications (2)

Publication Number Publication Date
KR970058406A true KR970058406A (ko) 1997-07-31
KR100240915B1 KR100240915B1 (ko) 2000-01-15

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Application Number Title Priority Date Filing Date
KR1019960046024A KR100240915B1 (ko) 1995-12-01 1996-10-15 회로 기판 및 그의 제조 방법

Country Status (5)

Country Link
US (2) US5707893A (ko)
KR (1) KR100240915B1 (ko)
CN (1) CN1088321C (ko)
SG (1) SG44058A1 (ko)
TW (1) TW312080B (ko)

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US6296897B1 (en) * 1998-08-12 2001-10-02 International Business Machines Corporation Process for reducing extraneous metal plating
IT1312433B1 (it) * 1999-05-14 2002-04-17 Cadif Srl Pannello con tessuto elettro-termico,ad alto isolamento elettrico
US6869750B2 (en) * 1999-10-28 2005-03-22 Fujitsu Limited Structure and method for forming a multilayered structure
JP3736607B2 (ja) * 2000-01-21 2006-01-18 セイコーエプソン株式会社 半導体装置及びその製造方法、回路基板並びに電子機器
EP1990831A3 (en) * 2000-02-25 2010-09-29 Ibiden Co., Ltd. Multilayer printed circuit board and multilayer printed circuit board manufacturing method
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US5707893A (en) 1998-01-13
CN1156948A (zh) 1997-08-13
SG44058A1 (en) 1997-11-14
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KR100240915B1 (ko) 2000-01-15
TW312080B (ko) 1997-08-01
US5817405A (en) 1998-10-06

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