KR970053456A - 반도체 소자의 금속배선 형성방법 - Google Patents

반도체 소자의 금속배선 형성방법 Download PDF

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KR970053456A
KR970053456A KR1019950064504A KR19950064504A KR970053456A KR 970053456 A KR970053456 A KR 970053456A KR 1019950064504 A KR1019950064504 A KR 1019950064504A KR 19950064504 A KR19950064504 A KR 19950064504A KR 970053456 A KR970053456 A KR 970053456A
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South Korea
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film
tin film
depositing
tin
semiconductor device
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KR1019950064504A
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KR100223748B1 (ko
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홍기로
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김주용
현대전자산업 주식회사
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Publication of KR970053456A publication Critical patent/KR970053456A/ko
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Publication of KR100223748B1 publication Critical patent/KR100223748B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 발명은 절연막(2)의 개구부 통해 하부의 전도층(1)과 전기적으로 접속되는 TiN막(5)을 중착하는 단계; Ar 플라즈마를 상기 TiN막(5)의 표면 일부를 식각하는 단계; 제1Al막(6)을 상기 TiN막(5)상에 중착하는 단계; 및 상기 제1Al막(6) 중착시의 온도보다 고온에서 제2Al막(6) 상기 TiN막(5) 상에 중착하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법에 관한 것이다.

Description

반도체 소자의 금속배선 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제4도는 본 발명에 따른 금속배선 형성공정 단면도.

Claims (6)

  1. 반도체 소자의 금속배선 형성방법에 있어서, 절연막의 개구부 통해 하부의 전도층과 전기적으로 접속되는 TiN막(5)을 중착하는 단계; 및 Ar 플라즈마로 상기 TiN막의 표면 일부를 식각하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.
  2. 제1항에 있어서, 상기 Ar 플라즈마에 의해 식각되는 상기 TiN막의 두께는 20~30Å 인 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.
  3. 제1항에 있어서, 상기 TiN막은 콜리메이터를 사용한 스퍼터링 방법으로 중착되는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.
  4. 반도체 소자의 금속배선 형성방법에 있어서, 절연막의 개구부 통해 하부의 전도층과 전기적으로 접속되는 TiN을 중착하는 단계; Ar 플라즈마로 상기 TiN막의 표면 일부를 식각하는 단계; 제1Al막을 상기 TiN막 상에 중착하는 단계; 및 상기 제1Al막 중착시의 온도보다 고온에서 제2Al막을 상기 TiN막 상에 중착하는 단계를 포함하여 이루어지는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.
  5. 제4항에 있어서, 상기 Ar 플라즈마에 의해 식각되는 상기 TiN막(5)의 두께는 20~30Å 인 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.
  6. 제4항에 있어서, 상기 TiN막(5)은 콜리메이터를 사용한 스퍼터링 방법으로 중착되는 것을 특징으로 하는 반도체 소자의 금속배선 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950064504A 1995-12-29 1995-12-29 반도체 소자의 금속배선 형성방법 KR100223748B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950064504A KR100223748B1 (ko) 1995-12-29 1995-12-29 반도체 소자의 금속배선 형성방법

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Application Number Priority Date Filing Date Title
KR1019950064504A KR100223748B1 (ko) 1995-12-29 1995-12-29 반도체 소자의 금속배선 형성방법

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KR970053456A true KR970053456A (ko) 1997-07-31
KR100223748B1 KR100223748B1 (ko) 1999-10-15

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06209047A (ja) * 1993-01-11 1994-07-26 Kawasaki Steel Corp 半導体装置の配線形成方法
JP2560626B2 (ja) * 1993-11-10 1996-12-04 日本電気株式会社 半導体装置の製造方法

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