KR970053070A - 반도체 소자의 게이트 전극 형성방법 - Google Patents

반도체 소자의 게이트 전극 형성방법 Download PDF

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KR970053070A
KR970053070A KR1019950069573A KR19950069573A KR970053070A KR 970053070 A KR970053070 A KR 970053070A KR 1019950069573 A KR1019950069573 A KR 1019950069573A KR 19950069573 A KR19950069573 A KR 19950069573A KR 970053070 A KR970053070 A KR 970053070A
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South Korea
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forming
gate electrode
oxide film
polysilicon
film
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KR1019950069573A
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KR100220248B1 (ko
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박상훈
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김주용
현대전자산업 주식회사
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Publication of KR100220248B1 publication Critical patent/KR100220248B1/ko

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H01L29/4925Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement
    • H01L29/4933Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with a silicide layer contacting the silicon layer, e.g. Polycide gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02225Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/0223Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate
    • H01L21/02244Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by oxidation, e.g. oxidation of the substrate of a metallic layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28061Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a metal or metal silicide formed by deposition, e.g. sputter deposition, i.e. without a silicidation reaction
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • H01L21/28167Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H01L21/28176Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation with a treatment, e.g. annealing, after the formation of the definitive gate conductor

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Ceramic Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

본 원은 반도체 소자의 게이트 전극 형성방법을 개시한다. 개시된 본 원은 반도체 기판의 소정 영역에 돌출 부위를 형성하고, 게이트 산화막을 형성한 다음, 전체 구조물 상부에 게이트 전극용 폴리실리콘막을 형성하고, 돌출부위의 상부 및 양측에 존재하도록 식각한다. 그리고, 전이 금속막을 하부의 폴리실리콘을 감싸안도록 형성하여 게이트 전극을 형성하는 단계를 포함한다.

Description

반도체 소자의 게이트 전극 형성방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도 (가) 내지 (라)는 본 발명에 따른 반도체 소자의 게이트 전극 형성방법을 설명하기 위한 공정 순서도.

Claims (5)

  1. 반도체 기판의 게이트 전극 예정 영역 상부에 마스크 패턴을 형성하고, 그의 형태로 기판을 식각하여 돌출 부위를 형성하는 단계; 상기 돌출부위를 구비한 반도체 기판 전면에 게이트 산화막을 형성하는 단계; 상기 게이트 산화막 상부에 폴리실리콘막을 형성하는 단계; 상기 폴리실리콘을 돌출 부위의 상부 및 측부에 존재하도록 식각하는 단계; 및 상기 식각이 이루어진 폴리실리콘을 감싸안도록 선택적 증착법에 의하여 전이 금속막을 형성하여 게이트 전극을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자의 게이트 전극 형성방법.
  2. 제1항에 있어서, 상기 전이 금속막을 형성하는 단계이후, 노출된 기판 표면을 열처리하여 열산화막을 형성하는 단계를 부가적으로 포함하는 것을 특징으로 하는 반도체 소자의 게이트 전극 형성방법.
  3. 제1항에 또는 제2항에 있어서, 상기 열산화막을 형성하는 단계는 수증기가 약 3 내지 8% 함유된 수소분위기 하에서, 900 내지 1000℃정도의 온도로 10 내지 60분 동안 열성장시키는 것을 특징으로 하는 반도체 소자의 게이트 전극 형성방법.
  4. 제3항에 있어서, 열산화막의 두께는 300 내지 800인 것을 특징으로 하는 반도체 소자의 게이트 전극 형성방법.
  5. 제1항에 있어서, 상기 폴리실리콘막의 증착단계 이후, 불순물 이온 주입 단계를 부가적으로 포함하는 것을 특징으로 하는 반도체 소자의 게이트 전극 형성방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950069573A 1995-12-30 1995-12-30 반도체 소자의 게이트 전극 형성방법 KR100220248B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950069573A KR100220248B1 (ko) 1995-12-30 1995-12-30 반도체 소자의 게이트 전극 형성방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950069573A KR100220248B1 (ko) 1995-12-30 1995-12-30 반도체 소자의 게이트 전극 형성방법

Publications (2)

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KR970053070A true KR970053070A (ko) 1997-07-29
KR100220248B1 KR100220248B1 (ko) 1999-09-15

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