KR970003630A - 반도체소자의 금속배선간 절연막의 제조방법 - Google Patents
반도체소자의 금속배선간 절연막의 제조방법 Download PDFInfo
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- KR970003630A KR970003630A KR1019950017677A KR19950017677A KR970003630A KR 970003630 A KR970003630 A KR 970003630A KR 1019950017677 A KR1019950017677 A KR 1019950017677A KR 19950017677 A KR19950017677 A KR 19950017677A KR 970003630 A KR970003630 A KR 970003630A
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- insulating film
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- metal
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- 239000002184 metal Substances 0.000 title claims abstract description 15
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 9
- 238000000034 method Methods 0.000 claims abstract 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims 3
- 229910052814 silicon oxide Inorganic materials 0.000 claims 3
- 230000004888 barrier function Effects 0.000 claims 2
- UPSOBXZLFLJAKK-UHFFFAOYSA-N ozone;tetraethyl silicate Chemical compound [O-][O+]=O.CCO[Si](OCC)(OCC)OCC UPSOBXZLFLJAKK-UHFFFAOYSA-N 0.000 claims 2
- 239000005380 borophosphosilicate glass Substances 0.000 claims 1
- 230000009977 dual effect Effects 0.000 claims 1
- 238000009832 plasma treatment Methods 0.000 claims 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims 1
- 239000000758 substrate Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76862—Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
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- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
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- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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Abstract
본 발명은 반도체소자의 금속배선간 절연막의 제조방법에 관한 것으로서, 금속배선이 되는 도전패턴을 절연막상에 형성한후에 상기 구조의 표면을 플라즈마로 처리한 후, SiH4-N2O 혼합 가스를 사용한 굴절율 1.47 이상의 Si 과함유 산화막을 상기 구조의 전표면에 형성하며, 상기 산화막상에 O3-TEOS막을 형성하여 금속배선간 절연막을 완성하였으므로, O3-TEOS막의성장 속도가 향상되며, 내부에 보이드등의 생성이 방지되는 등 막질이 향상되어, 절연막의 재현성이 향상되어 공정수율및 소자 동작의 신뢰성을 향상시킬 수 있다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2A도 내지 제2D도는 본발명에 따른 반도체소자의 금속배선간 절연막의 제조 공정도.
Claims (9)
- 반도체기판상에 절연막을 형성하는 공정과, 상기 절연막상에 금속배선을 형성하는 공정과, 상기 구조의 금속배선을 플라즈마 처리하는 공정과, 상기 구조의 전표면에 과실리콘 산화막을 형성하는 공정과, 상기 산화막 상에 O3-TEOS막을 형성하는 공정을 구비하는 반도체소자의 금속배선간 절연막의 제조방법.
- 제1항에 있어서, 상기 절연막이 산화막 또는 BPSG 계열 막인 것을 특징으로하는 반도체소자의 금속배선간절연막의 제조방법.
- 제1항에 있어서, 상기 금속배선이 장벽금속층과 W층 및 반사방지막의 적층 구조로 형성되는 것을 특징으로하는 반도체소자의 금속배선간 절연막의 제조방법.
- 제1항에 있어서, 상기 금속배선이 장벽금속층과 Al층으로 형성되는 것을 특징으로하는 반도체소자의 금속배선간 절연막의 제조방법.
- 제1항에 있어서, 상기 플라즈마 처리 공정이 Ar 플라즈마로서, 양 주파수(dual frequency) 방식으로, 고주파수는 200~400W, 저주파수는 50W 이상의 파워로하여, 25℃ 이상의 온도에서, 10초 이상 실시하는 것을 특징으로하는 반도체소자의 금속배선간 절연막의 제조방법.
- 제1항에 있어서, 상기 플라즈마를 N2 가스 플라즈마로 처리하는 것을 특징으로하는 반도체소자의 금속배선간 절연막의 제조방법.
- 제1항에 있어서, 상기 과실리콘 산화막을 PECVD 방법으로 SiH4-N2O 혼합 가스를 사용하여 굴절율이 1.47 이상인 산화막으로 형성하는 것을 특징으로하는 반도체소자의 금속배선간 절연막의 제조방법.
- 제1항에 있어서, 상기 과실리콘 산화막을 1000Å 이상의 두께로 형성하는 것을 특징으로하는 반도체소자의금속배선간 절연막의 제조방법.
- 제1항에 있어서, 상기 O3-TEOS막을 5000Å 이상의 두께로 형성하는 것을 특징으로 하는 반도체소자의 금속배선간 절연막의 제조방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019950017677A KR0159016B1 (ko) | 1995-06-28 | 1995-06-28 | 반도체소자의 금속배선간 절연막의 제조방법 |
TW085106271A TW297924B (ko) | 1995-06-28 | 1996-05-27 | |
US08/660,151 US6060382A (en) | 1995-06-28 | 1996-06-04 | Method for forming insulating film between metal wirings of semiconductor device |
JP8152660A JP2857369B2 (ja) | 1995-06-28 | 1996-06-13 | 半導体素子の金属配線間絶縁膜の製造方法 |
CN96108235A CN1056468C (zh) | 1995-06-28 | 1996-06-28 | 用于在半导体器件的诸金属布线之间形成绝缘薄膜的方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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KR1019950017677A KR0159016B1 (ko) | 1995-06-28 | 1995-06-28 | 반도체소자의 금속배선간 절연막의 제조방법 |
Publications (2)
Publication Number | Publication Date |
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KR970003630A true KR970003630A (ko) | 1997-01-28 |
KR0159016B1 KR0159016B1 (ko) | 1999-02-01 |
Family
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Application Number | Title | Priority Date | Filing Date |
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KR1019950017677A KR0159016B1 (ko) | 1995-06-28 | 1995-06-28 | 반도체소자의 금속배선간 절연막의 제조방법 |
Country Status (5)
Country | Link |
---|---|
US (1) | US6060382A (ko) |
JP (1) | JP2857369B2 (ko) |
KR (1) | KR0159016B1 (ko) |
CN (1) | CN1056468C (ko) |
TW (1) | TW297924B (ko) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100549333B1 (ko) * | 1998-10-02 | 2006-04-06 | 주식회사 하이닉스반도체 | 반도체 소자의 금속배선 형성 방법 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6355983B2 (en) * | 1997-05-20 | 2002-03-12 | Texas Instruments Incorporated | Surface modified interconnects |
US20010055868A1 (en) | 1998-05-22 | 2001-12-27 | Madan Sudhir K. | Apparatus and method for metal layer streched conducting plugs |
TW469619B (en) * | 1998-05-26 | 2001-12-21 | Winbond Electronics Corp | Structure and manufacturing method for metal line |
KR100278657B1 (ko) * | 1998-06-24 | 2001-02-01 | 윤종용 | 반도체장치의금속배선구조및그제조방법 |
KR20030000964A (ko) * | 2001-06-27 | 2003-01-06 | 주식회사 하이닉스반도체 | 반도체 소자의 금속 배선 형성 방법 |
KR100675895B1 (ko) * | 2005-06-29 | 2007-02-02 | 주식회사 하이닉스반도체 | 반도체소자의 금속배선구조 및 그 제조방법 |
KR102402761B1 (ko) * | 2015-10-30 | 2022-05-26 | 삼성전자주식회사 | 반도체 장치 및 이의 제조 방법 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01124221A (ja) * | 1987-11-09 | 1989-05-17 | Nec Corp | 半導体装置の製造方法 |
US5089442A (en) * | 1990-09-20 | 1992-02-18 | At&T Bell Laboratories | Silicon dioxide deposition method using a magnetic field and both sputter deposition and plasma-enhanced cvd |
JPH05308107A (ja) * | 1991-07-01 | 1993-11-19 | Sumitomo Electric Ind Ltd | 半導体装置及びその製作方法 |
JPH06132542A (ja) * | 1992-10-20 | 1994-05-13 | Mitsubishi Electric Corp | 半導体装置 |
JPH0770534B2 (ja) * | 1993-01-11 | 1995-07-31 | 日本電気株式会社 | 半導体装置の製造方法 |
US5403780A (en) * | 1993-06-04 | 1995-04-04 | Jain; Vivek | Method enhancing planarization etchback margin, reliability, and stability of a semiconductor device |
JPH0766287A (ja) * | 1993-08-23 | 1995-03-10 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
JPH07115135A (ja) * | 1993-10-18 | 1995-05-02 | Toshiba Corp | 半導体装置の製造方法 |
JPH07142471A (ja) * | 1993-11-15 | 1995-06-02 | Sony Corp | 酸化膜の成膜方法及び酸化膜成膜装置 |
-
1995
- 1995-06-28 KR KR1019950017677A patent/KR0159016B1/ko not_active IP Right Cessation
-
1996
- 1996-05-27 TW TW085106271A patent/TW297924B/zh not_active IP Right Cessation
- 1996-06-04 US US08/660,151 patent/US6060382A/en not_active Expired - Lifetime
- 1996-06-13 JP JP8152660A patent/JP2857369B2/ja not_active Expired - Fee Related
- 1996-06-28 CN CN96108235A patent/CN1056468C/zh not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100549333B1 (ko) * | 1998-10-02 | 2006-04-06 | 주식회사 하이닉스반도체 | 반도체 소자의 금속배선 형성 방법 |
Also Published As
Publication number | Publication date |
---|---|
JP2857369B2 (ja) | 1999-02-17 |
US6060382A (en) | 2000-05-09 |
JPH0917869A (ja) | 1997-01-17 |
CN1143261A (zh) | 1997-02-19 |
TW297924B (ko) | 1997-02-11 |
CN1056468C (zh) | 2000-09-13 |
KR0159016B1 (ko) | 1999-02-01 |
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