JPH0917869A - 半導体素子の金属配線間絶縁膜の製造方法 - Google Patents
半導体素子の金属配線間絶縁膜の製造方法Info
- Publication number
- JPH0917869A JPH0917869A JP8152660A JP15266096A JPH0917869A JP H0917869 A JPH0917869 A JP H0917869A JP 8152660 A JP8152660 A JP 8152660A JP 15266096 A JP15266096 A JP 15266096A JP H0917869 A JPH0917869 A JP H0917869A
- Authority
- JP
- Japan
- Prior art keywords
- film
- insulating film
- layer
- oxide film
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000002184 metal Substances 0.000 title claims abstract description 58
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 58
- 239000004065 semiconductor Substances 0.000 title claims abstract description 35
- 238000009413 insulation Methods 0.000 title abstract 10
- 238000000034 method Methods 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 239000005380 borophosphosilicate glass Substances 0.000 claims abstract description 4
- 238000004519 manufacturing process Methods 0.000 claims description 26
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 8
- 238000009832 plasma treatment Methods 0.000 claims description 6
- 230000004888 barrier function Effects 0.000 claims description 4
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 4
- 230000009977 dual effect Effects 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 abstract description 10
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 6
- 230000015572 biosynthetic process Effects 0.000 abstract description 3
- 230000006866 deterioration Effects 0.000 abstract description 2
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract 1
- 230000006698 induction Effects 0.000 abstract 1
- 239000010936 titanium Substances 0.000 description 8
- 238000007796 conventional method Methods 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229910021332 silicide Inorganic materials 0.000 description 3
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical group [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000004544 sputter deposition Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- -1 Phospho Chemical class 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76861—Post-treatment or after-treatment not introducing additional chemical elements into the layer
- H01L21/76862—Bombardment with particles, e.g. treatment in noble gas plasmas; UV irradiation
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
- H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
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- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
- H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
- H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
- H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
- H01L21/02274—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
- H01L21/02299—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment
- H01L21/02312—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour
- H01L21/02315—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer pre-treatment treatment by exposure to a gas or vapour treatment by exposure to a plasma
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76822—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
- H01L21/76826—Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by contacting the layer with gases, liquids or plasmas
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31608—Deposition of SiO2
- H01L21/31612—Deposition of SiO2 on a silicon body
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/314—Inorganic layers
- H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
- H01L21/31604—Deposition from a gas or vapour
- H01L21/31625—Deposition of boron or phosphorus doped silicon oxide, e.g. BSG, PSG, BPSG
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- Power Engineering (AREA)
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- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
- Local Oxidation Of Silicon (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
造方法はO3 −TEOS膜を形成して絶縁層内部にボイ
ドが形成されたり膜質が悪化されることを防止するもの
である。 【解決手段】 金属配線となる導電パターンを絶縁膜上
に形成した後にその配線構造の表面をプラズマ処理し、
その後、たとえばSiH4 −N2 O混合ガスを用いた屈
折率1.47以上のSi過含有酸化膜を配線構造の全表
面に形成し、この酸化膜上にO3 −TEOS膜を形成し
て金属配線間の絶縁膜を完成したため、O3 −TEOS
膜の成長速度が向上し、内部でのボイド等の生成が防止
される等の膜質向上が図られ、絶縁膜の再現性が向上し
工程収率及び素子動作の信頼性を向上させることができ
る。
Description
線間絶縁膜の製造方法に関し、特に金属配線間に絶縁膜
が形成される時、基板上にパターンニングした表面をプ
ラズマ処理し、プラズマ誘導(plasma enha
nced)化学気相堆積(chemical vapo
r deposition;以下PECVDと称する)
方法で第1金属間絶縁膜を形成し、その絶縁膜上部にO
3 −TEOS膜のような第2絶縁膜を形成した半導体素
子の金属配線間絶縁膜の製造方法に関する。
やビットライン等の導電配線の幅が減縮しているが、導
電配線の幅がN分の1に減縮すると電気抵抗がN倍に増
加され半導体素子の動作速度を落とす問題点がある。
等に用いられる導電配線では主にドーピングされた多結
晶シリコン層を用い、これは面抵抗が約30〜70Ω/
cm2 程度であり、コンタクト抵抗が一つのコンタクト
当り約30〜70Ω/cm2程度である。
は素子の動作速度を落とす問題があるが、これら抵抗を
減少させるため多結晶シリコン層上に金属−シリサイド
膜が積層されているサリサイド(salicide;s
elf−aligned silicide)構造とし
て選択的金属膜堆積方法で導電配線の上部にのみ金属シ
リサイド膜や選択的金属膜を形成する方法が知られてい
る。
にTi(チタン)シリサイドやW(タングステン)を選
択的に形成する方法によれば、面抵抗は約5Ω/cm2
となり、コンタクト抵抗はコンタクト当り約3Ω/cm
2 以下に著しく減少する。これにより素子の動作時間遅
延を抑制することができ、高集積化が可能となる。
線としても従来はA1(アルミニウム)やその合金を主
に用いたが、A1より高温での安全性が優れ、金属配線
厚さを薄く形成することができ、平坦化が容易なWが用
いられる場合もある。
縁膜の製造工程図を図1A乃至図1Cに示す。ここでは
その一例としてW配線を挙げる。
ーハとなった半導体基板上に素子分離酸化膜とMOSト
ランジスタとキャパシター及びビットラインを形成し、
構造の全表面に絶縁膜(1)を形成する。
i層(2)とTiN層(3)を逐次に形成し、TiN層
(3)上にCVD方法でW層(4)を形成した後、W層
(4)上にW層(4)のパターンニングのための露光工
程時の乱反射を防止するためのTiNからなる反射防止
膜(5)を形成する。
防止膜(5)からTi層(2)まで順次湿式又は、乾式
エッチングして反射防止膜(5)パターンからTi層
(2)パターンまでの導電パターンで構成される金属配
線を形成する(図1参照)。
法で酸化膜(6)を1000オングストローム程度の厚
さに形成し、酸化膜(6)の表面をArやN2 ガスプラ
ズマ中に露出させ表面を損傷させて電荷を発生させる。
この工程は後に形成される平坦化層との界面特性の向上
のための工程である(図2参照)。
O3 −TEOS膜(7)を形成し、これを流動させ半導
体素子の金属配線間絶縁膜の製造工程を完了する(図3
参照)。
金属配線間絶縁膜の製造方法は金属配線の表面に酸化膜
を形成し、酸化膜の表面をプラズマ処理して損傷させた
後、平坦化膜であるO3 −TEOS膜を形成するが、O
3 −TEOS膜が下部層に対する依存性が高く下部層の
種類や状態により成長速度が異なり、膜内に多量のボイ
ドが形成されたり、流動性が悪化したりして、素子の再
現性が落ち、工程収率及び素子動作の信頼性が落下する
問題点がある。
ある場合にはO3 −TEOS膜の成長速度がさらに落
ち、膜質が悪化する問題点がある。
問題点を解決するためのものであり、本発明の目的は金
属配線をパターンニングした後、全表面をプラズマ処理
して損傷させ、CVD酸化膜とO3 −TEOS膜を全表
面に形成して絶縁層の内部にボイドが形成されたり膜質
が悪化することを防止し、再現性が優れ工程収率及び素
子動作の信頼性を向上させることができる半導体素子の
金属配線間絶縁膜の製造方法を提供することにある。
るための本発明による半導体素子の金属配線間絶縁膜製
造方法の特徴は、半導体基板上に絶縁膜を形成する工程
と、絶縁膜上に金属配線を形成する工程と、この金属配
線をプラズマ処理する工程と、絶縁膜および金属配線の
露出した全表面にシリコン酸化膜を形成する工程と、シ
リコン酸化膜上にO3 −TEOS膜を形成する工程とを
備えることにある。
では、半導体基板上に形成された絶縁膜として酸化膜又
は、BPSG系列膜を用いることができる。金属配線の
プラズマ処理としてN2 ガスプラズマ処理を用いること
ができる。また、過シリコン酸化膜は、SiH4 −N2
O混合ガスを用いて形成し、屈折率が1.47以上であ
る酸化膜とすることが望ましい。
半導体素子の金属配線間絶縁膜の製造方法に関し添付図
面を参照して詳細に説明する。
金属配線間絶縁膜の製造工程図で、W配線の例である。
ーハでなる半導体基板上に素子分離のための素子分離酸
化膜を形成して活性領域を定義し、ゲート電極とソース
/ドレイン電極等で構成されるMOSトランジスタとキ
ャパシター及びビットライン等を形成して素子構造を完
成し、この素子構造の全表面に酸化膜やB.P.S.G
(Boro Phospho Silicate Gl
ass;以下BPSGと称する)等の材質でなる絶縁膜
(1)を形成する。
ークや不純物拡散を防止するための障壁金属層であるT
i層(2)とTiN層(3)をスパッタリング等の方法
で形成し、TiN層(3)上にCVD方法でW層(4)
を形成する。
めの露光工程時の光の乱反射を防止するためTiNでな
る反射防止膜(5)をスパッタリング方法でW層(4)
上に形成した後、通常の写真エッチング方法で反射防止
膜(5)からTi層(2)まで順次湿式又は乾式エッチ
ングして反射防止膜(5)パターンと、W層(4)パタ
ーン、TiN層(3)パターン及びTi層(2)パター
ンで構成される金属配線を形成する(図4参照)。
W層(4)パターン、TiN層(3)パターン及びTi
層(2)パターンと絶縁膜(1)の露出している表面を
Arプラズマで処理する。本発明者の実験結果によれ
ば、プラズマ処理の条件は上下2種類の周波数を印加す
る二重周波数(dual frequency)方式
で、高周波数は200〜400W(ワット)、低周波数
は50W以上のパワーとし、25℃以上の温度で、10
秒以上実施すると、後続積層されるO3 −TEOS絶縁
膜の膜質が優秀になる。また、ArでないN2 ガスプラ
ズマで処理しても同様な効果を得ることができる(図5
参照)。
誘導(plasma enhanced)CVD(以
下、PECVDと称する)方法でSiH4 −N2 O混合
ガスを用いて屈折率が1.47以上のSi原子を過含有
する酸化膜(8)を、1000オングストローム以上の
厚さに形成する。ここで、酸化膜の屈折率は通常のCV
D酸化膜の屈折率が1.45程度であることを考慮すれ
ば、屈折率が高いほど後続積層膜の膜質が向上すること
を実験結果により知ることができた(図6参照)。
S膜(7)を5000オングストローム以上の厚さに形
成し、平坦化させて金属配線間絶縁膜形成工程を完了す
る(図7参照)。
3 −TEOS膜の膜質が比較的悪化しにくいA1配線で
も本発明の思想を適用することができるのは勿論であ
る。
体素子の金属配線間絶縁膜の製造方法によると、金属配
線でなる導電パターンを絶縁膜上に形成した後にその配
線構造の表面をプラズマで処理した後、たとえばSiH
4 −N2 O混合ガスを用いた屈折率1.47以上のSi
過含有酸化膜を構造の全表面に形成し、酸化膜上にO3
−TEOS膜を形成して金属配線の間の絶縁膜を完成し
たので、O3 −TEOS膜の成長速度が向上し、内部で
のボイド等の生成が防止できる等の膜質向上が図られ、
絶縁膜の再現性が向上し工程収率及び素子動作の信頼性
を向上させることができる利点がある。
の製造工程図。
の製造工程図。
の製造工程図。
線間絶縁膜の製造工程図。
線間絶縁膜の製造工程図。
線間絶縁膜の製造工程図。
線間絶縁膜の製造工程図。
…反射防止膜、6…酸化膜、7…O3 −TEOS膜、8
…過シリコン酸化膜
Claims (10)
- 【請求項1】 半導体基板上に絶縁膜を形成する工程
と、 前記絶縁膜上に金属配線を形成する工程と、 前記金属配線をプラズマ処理する工程と、 前記絶縁膜および金属配線の露出した全表面に過シリコ
ン酸化膜を形成する工程と、 前記酸化膜上に第2絶縁膜を形成する工程とを備える半
導体素子の金属配線間絶縁膜の製造方法。 - 【請求項2】 前記絶縁膜が、酸化膜またはBPSG系
列膜であることを特徴とする請求項1記載の半導体素子
の金属配線間絶縁膜の製造方法。 - 【請求項3】 前記金属配線が、障壁金属層とW層及び
反射防止膜の積層構造で形成されることを特徴とする請
求項1記載の半導体素子の金属配線間絶縁膜の製造方
法。 - 【請求項4】 前記金属配線が、障壁金属層とAl層で
形成されることを特徴とする請求項1記載の半導体素子
の金属配線間絶縁膜の製造方法。 - 【請求項5】 前記プラズマ処理工程が二重周波数(d
ual frequency)方式で、高周波数は20
0〜400W、低周波数は50W以上のパワーにして、
25℃以上の温度で10秒以上行うArプラズマ処理を
含むことを特徴とする請求項1記載の半導体素子の金属
配線間絶縁膜の製造方法。 - 【請求項6】 前記プラズマが、N2 ガスプラズマであ
ることを特徴とする請求項1記載の半導体素子の金属配
線間絶縁膜の製造方法。 - 【請求項7】 前記過シリコン酸化膜を、PECVD方
法でSiH4 −N2O混合ガスを用いて屈折率が1.4
7以上である酸化膜に形成することを特徴とする請求項
1記載の半導体素子の金属配線間絶縁膜の製造方法。 - 【請求項8】 前記過シリコン酸化膜を、1000オン
グストローム以上の厚さに形成することを特徴とする請
求項1または5記載の半導体素子の金属配線間絶縁膜の
製造方法。 - 【請求項9】 前記第2絶縁膜を、5000オングスト
ローム以上の厚さに形成することを特徴とする請求項1
記載の半導体素子の金属配線間絶縁膜の製造方法。 - 【請求項10】 前記第2絶縁膜は、O3 −TEOS膜
を含むことを特徴とする請求項1記載の半導体素子の金
属配線間絶縁膜の製造方法。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR95-17677 | 1995-06-28 | ||
KR1019950017677A KR0159016B1 (ko) | 1995-06-28 | 1995-06-28 | 반도체소자의 금속배선간 절연막의 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH0917869A true JPH0917869A (ja) | 1997-01-17 |
JP2857369B2 JP2857369B2 (ja) | 1999-02-17 |
Family
ID=19418451
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8152660A Expired - Fee Related JP2857369B2 (ja) | 1995-06-28 | 1996-06-13 | 半導体素子の金属配線間絶縁膜の製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US6060382A (ja) |
JP (1) | JP2857369B2 (ja) |
KR (1) | KR0159016B1 (ja) |
CN (1) | CN1056468C (ja) |
TW (1) | TW297924B (ja) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6355983B2 (en) * | 1997-05-20 | 2002-03-12 | Texas Instruments Incorporated | Surface modified interconnects |
US20010055868A1 (en) | 1998-05-22 | 2001-12-27 | Madan Sudhir K. | Apparatus and method for metal layer streched conducting plugs |
TW469619B (en) * | 1998-05-26 | 2001-12-21 | Winbond Electronics Corp | Structure and manufacturing method for metal line |
KR100278657B1 (ko) | 1998-06-24 | 2001-02-01 | 윤종용 | 반도체장치의금속배선구조및그제조방법 |
KR100549333B1 (ko) * | 1998-10-02 | 2006-04-06 | 주식회사 하이닉스반도체 | 반도체 소자의 금속배선 형성 방법 |
KR20030000964A (ko) * | 2001-06-27 | 2003-01-06 | 주식회사 하이닉스반도체 | 반도체 소자의 금속 배선 형성 방법 |
KR100675895B1 (ko) * | 2005-06-29 | 2007-02-02 | 주식회사 하이닉스반도체 | 반도체소자의 금속배선구조 및 그 제조방법 |
KR102402761B1 (ko) | 2015-10-30 | 2022-05-26 | 삼성전자주식회사 | 반도체 장치 및 이의 제조 방법 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01124221A (ja) * | 1987-11-09 | 1989-05-17 | Nec Corp | 半導体装置の製造方法 |
JPH06132542A (ja) * | 1992-10-20 | 1994-05-13 | Mitsubishi Electric Corp | 半導体装置 |
JPH07115135A (ja) * | 1993-10-18 | 1995-05-02 | Toshiba Corp | 半導体装置の製造方法 |
JPH07142471A (ja) * | 1993-11-15 | 1995-06-02 | Sony Corp | 酸化膜の成膜方法及び酸化膜成膜装置 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5089442A (en) * | 1990-09-20 | 1992-02-18 | At&T Bell Laboratories | Silicon dioxide deposition method using a magnetic field and both sputter deposition and plasma-enhanced cvd |
JPH05308107A (ja) * | 1991-07-01 | 1993-11-19 | Sumitomo Electric Ind Ltd | 半導体装置及びその製作方法 |
JPH0770534B2 (ja) * | 1993-01-11 | 1995-07-31 | 日本電気株式会社 | 半導体装置の製造方法 |
US5403780A (en) * | 1993-06-04 | 1995-04-04 | Jain; Vivek | Method enhancing planarization etchback margin, reliability, and stability of a semiconductor device |
JPH0766287A (ja) * | 1993-08-23 | 1995-03-10 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
-
1995
- 1995-06-28 KR KR1019950017677A patent/KR0159016B1/ko not_active IP Right Cessation
-
1996
- 1996-05-27 TW TW085106271A patent/TW297924B/zh not_active IP Right Cessation
- 1996-06-04 US US08/660,151 patent/US6060382A/en not_active Expired - Lifetime
- 1996-06-13 JP JP8152660A patent/JP2857369B2/ja not_active Expired - Fee Related
- 1996-06-28 CN CN96108235A patent/CN1056468C/zh not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01124221A (ja) * | 1987-11-09 | 1989-05-17 | Nec Corp | 半導体装置の製造方法 |
JPH06132542A (ja) * | 1992-10-20 | 1994-05-13 | Mitsubishi Electric Corp | 半導体装置 |
JPH07115135A (ja) * | 1993-10-18 | 1995-05-02 | Toshiba Corp | 半導体装置の製造方法 |
JPH07142471A (ja) * | 1993-11-15 | 1995-06-02 | Sony Corp | 酸化膜の成膜方法及び酸化膜成膜装置 |
Also Published As
Publication number | Publication date |
---|---|
JP2857369B2 (ja) | 1999-02-17 |
CN1143261A (zh) | 1997-02-19 |
US6060382A (en) | 2000-05-09 |
KR970003630A (ko) | 1997-01-28 |
TW297924B (ja) | 1997-02-11 |
CN1056468C (zh) | 2000-09-13 |
KR0159016B1 (ko) | 1999-02-01 |
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