JPS5650538A - Formation of multilayered wiring structure - Google Patents
Formation of multilayered wiring structureInfo
- Publication number
- JPS5650538A JPS5650538A JP12764679A JP12764679A JPS5650538A JP S5650538 A JPS5650538 A JP S5650538A JP 12764679 A JP12764679 A JP 12764679A JP 12764679 A JP12764679 A JP 12764679A JP S5650538 A JPS5650538 A JP S5650538A
- Authority
- JP
- Japan
- Prior art keywords
- nitride film
- film
- plasma
- metal
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
PURPOSE:To omit the process of forming an opening hole in an interlayer insulating film, in the case interlayer connecting of multilayered wiring is performed, by employing a plasma nitride film (a nitride film formed by a plasma CVD method) as the interlayer insulating layer, thermally reacting the copper and the plasma nitride film, and giving the conductive property. CONSTITUTION:An insulating layer 2 comprising an SiO2 film is formed on the main surface of a silicon substrate 1. Then, the first wiring metal layer 10 is formed by a metal, which is not reacted with a nitride film made by a plasma CVD method, e.g., Al. Thereafter a nitride film 11 which is to become the interlayer insulating film is formed by the plasma CVD method, a metal connecting film 12 comprising Cu is selectively formed on the surface, and the heat treatment is performed. Thus, Cu is diffused into the nitride film, and a conductive layer 13 is formed. Thereafter, the second wiring metal layer 14 is formed, a desired pattern is formed, and the itended multilayered wiring structure can be obtained. As for the conductive layer, a metal, other than Cu, which can be readily diffused into the plasma nitride film, and which can make it conductive, can be used.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12764679A JPS5650538A (en) | 1979-10-02 | 1979-10-02 | Formation of multilayered wiring structure |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12764679A JPS5650538A (en) | 1979-10-02 | 1979-10-02 | Formation of multilayered wiring structure |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5650538A true JPS5650538A (en) | 1981-05-07 |
Family
ID=14965233
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12764679A Pending JPS5650538A (en) | 1979-10-02 | 1979-10-02 | Formation of multilayered wiring structure |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5650538A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1988010008A1 (en) * | 1987-06-12 | 1988-12-15 | Massachusetts Institute Of Technology | Fabrication of interlayer conductive paths in integrated circuits |
-
1979
- 1979-10-02 JP JP12764679A patent/JPS5650538A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1988010008A1 (en) * | 1987-06-12 | 1988-12-15 | Massachusetts Institute Of Technology | Fabrication of interlayer conductive paths in integrated circuits |
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