KR960035916A - 반도체 소자 제조방법 - Google Patents

반도체 소자 제조방법 Download PDF

Info

Publication number
KR960035916A
KR960035916A KR1019950006097A KR19950006097A KR960035916A KR 960035916 A KR960035916 A KR 960035916A KR 1019950006097 A KR1019950006097 A KR 1019950006097A KR 19950006097 A KR19950006097 A KR 19950006097A KR 960035916 A KR960035916 A KR 960035916A
Authority
KR
South Korea
Prior art keywords
forming
substrate
protrusion
gate electrode
semiconductor substrate
Prior art date
Application number
KR1019950006097A
Other languages
English (en)
Other versions
KR0147678B1 (ko
Inventor
황리연
Original Assignee
문정환
엘지반도체 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 문정환, 엘지반도체 주식회사 filed Critical 문정환
Priority to KR1019950006097A priority Critical patent/KR0147678B1/ko
Publication of KR960035916A publication Critical patent/KR960035916A/ko
Application granted granted Critical
Publication of KR0147678B1 publication Critical patent/KR0147678B1/ko

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025Channel region of field-effect devices
    • H01L29/1029Channel region of field-effect devices of field-effect transistors
    • H01L29/1033Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66537Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

본 발명은 반도체 소자 제조방법에 관한 것으로, 숏채널특성과 펀치쓰루특성을 개선시킬 수 있도록 한것이다.
본 발명은 반도체기판을 선택적으로 식각하여 소정영역에 산모양의 돌출부를 형성하는 단계와, 상기 돌출부가 형성된 반도체기판 전면에 게이트산화막을 형성하는 단계, 상기 돌출부를 포함하는 기판 소정영역 상부에 게이트전극에 형성하는 단계, 및 기판과 동일도전형이 불순물을 경사 이온주입하여 게이트전극 하부의 기판내에 채널스톱영역을 형성하는 단계를 포함하는 반도체 소자 제조방법을 제공한다.

Description

반도체 소자 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 2도는 본 발명의 반도체 소자 제조방법을 도시한 공정순서도, 제 3도 및 제 4도는 본 발명의 효과를 설명하기 위한 도면.

Claims (3)

  1. 반도체기판을 선택적으로 식각하여 돌출부를 형성하는 단계와, 상기 돌출부가 형성된 반도체기판위에 게이트절연막을 형성하는 단계, 상기 돌출부에 대응하는 게이트 절연막위에 게이트전극을 형성하는 단계, 및 기관과 동일도전형의 불순물을 경사 이온주입하여 게이트전극 하부의 기판내에 채널스톱영역을 형성하는 단계를 포함하는 것을 특징으로 하는 반도체 소자 제조방법
  2. 제 1항에 있어서, 상기 반도체기판에 돌출부를 형성하는 단계는 반도체기판상에 질화막을 형성하는 공정, 상기 질화막을 선택적으로 식각하여 기판을 노출시키는 공정,상기 노출된 기판부위를 비등방성식각하는 공정, 상기 식각된 기판부위상에 산화막을 형성하는 공정, 상기 질화막을 제거하는 공정, 상기 질화막의 제거에 따라 노출된 기판부위를 비등방석 식각하는 공정, 상기 산화막을 제거하는 공정으로 이루어지는 것을 특징으로 하는 반도체 소자 제조방법.
  3. 제 1항에 있어서, 상기 채널스톱영역을 형성하는 단계후에 기판과 반대도전형의 불순물을 저농도로 이온주입하는 단계, 상기 게이트전극 측면에 측벽스페이서를 형성하는 공정, 기판과 반대도전형의 불순물을 고농도로 이온 주입하는 단계, 열처리를 행하여 저농도 불순물영역 및 고농도 소오스 및 드레인 영역을 형성하는 단계를 더 포함하는 것을 특징으로 하는 반도체 소자 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950006097A 1995-03-22 1995-03-22 반도체 소자 제조방법 KR0147678B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019950006097A KR0147678B1 (ko) 1995-03-22 1995-03-22 반도체 소자 제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019950006097A KR0147678B1 (ko) 1995-03-22 1995-03-22 반도체 소자 제조방법

Publications (2)

Publication Number Publication Date
KR960035916A true KR960035916A (ko) 1996-10-28
KR0147678B1 KR0147678B1 (ko) 1998-11-02

Family

ID=19410355

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950006097A KR0147678B1 (ko) 1995-03-22 1995-03-22 반도체 소자 제조방법

Country Status (1)

Country Link
KR (1) KR0147678B1 (ko)

Also Published As

Publication number Publication date
KR0147678B1 (ko) 1998-11-02

Similar Documents

Publication Publication Date Title
KR960036041A (ko) 고내압 트랜지스터 및 그 제조방법
KR940027104A (ko) 트랜지스터 제조방법
KR870000763A (ko) 반도체 장치 및 그 제조방법
KR960035908A (ko) 모스 전계효과 트랜지스터의 제조방법
KR980006542A (ko) 반도체소자 제조방법
KR960006045A (ko) 반도체장치의 제조방법
KR100257074B1 (ko) 모스팻 및 이의 제조방법
KR960035916A (ko) 반도체 소자 제조방법
KR970024283A (ko) 모스 트랜지스터 및 그 제조방법
KR100421899B1 (ko) 반도체소자제조방법
KR950026026A (ko) 트랜지스터 제조 방법
KR960005895A (ko) 모스트랜지스터 제조방법
KR950012647A (ko) 트랜지스터 제조방법
KR970052981A (ko) 반도체소자의 제조방법
KR950004589A (ko) 모스패트(mosfet)구조 및 제조방법
KR950025921A (ko) 반도체소자 제조방법
KR940016888A (ko) 트랜지스터 형성 방법
KR970018242A (ko) 반도체 소자 제조방법
KR960035918A (ko) 반도체 소자의 얕은 접합 형성방법
KR960019611A (ko) 반도체소자 제조방법
KR980005893A (ko) 반도체 소자의 트랜지스터 제조 방법
KR920013700A (ko) 소이 구조의 트랜지스터 제조방법
KR19990060945A (ko) 반도체 소자의 제조 방법
KR960015813A (ko) 모스펫 형성방법
KR970054497A (ko) 박막 트랜지스터 제조방법

Legal Events

Date Code Title Description
A201 Request for examination
E701 Decision to grant or registration of patent right
GRNT Written decision to grant
FPAY Annual fee payment

Payment date: 20070419

Year of fee payment: 10

LAPS Lapse due to unpaid annual fee