KR960026340A - 플라즈마 에칭 방법 - Google Patents

플라즈마 에칭 방법 Download PDF

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Publication number
KR960026340A
KR960026340A KR1019950054324A KR19950054324A KR960026340A KR 960026340 A KR960026340 A KR 960026340A KR 1019950054324 A KR1019950054324 A KR 1019950054324A KR 19950054324 A KR19950054324 A KR 19950054324A KR 960026340 A KR960026340 A KR 960026340A
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South Korea
Prior art keywords
chamber
substrate
etching
planar coil
plasma
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KR1019950054324A
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English (en)
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KR100413894B1 (ko
Inventor
비린더 에스 그레왈
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발도르프, 옴케
지멘스 악티엔게젤샤프트
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Publication of KR960026340A publication Critical patent/KR960026340A/ko
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Publication of KR100413894B1 publication Critical patent/KR100413894B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Drying Of Semiconductors (AREA)
  • ing And Chemical Polishing (AREA)

Abstract

챔버 벽내에 설치되 유전체 윈도우에 인접하고 챔버의바깥에 중착되는 전기적으로 전도성 평면 코일로 적합한 진공 챔버에 염소를 포함하는 플라즈마 가스로 실리콘에 게이트 스택을 플라즈마 에칭, 전도성 평면 코일은 소스의 임피던스가 코일에 정합되는 제1무선 주파수 원에 결합되고, 및 제2전도성 무선 주파수 원이 제1무선 주자수 원으로부터 0내지 200와트 및 제2무선 주파수 원으로부터 50내지 200으로 에칭중에 전력을 제한하는 것을 포함하는 평면 코일에 평행한 방향의 챔버에 부착된 기판 지지대에 결합되는 방법. 결과 에칭이 이방성이고, 기판의 전하가 에칭되는 것을 피한다. 게이트 스택이 전도성 폴리실리콘을 포함할 때, 바람직한 플라즈마에칭 가스는 높은 선택적인 에칭이 얻어질 때 수소 염화물 및 염소의 혼합물이다.

Description

플라즈마 에칭 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제6도는 본 발명의 공정에 다라서 형성된 에칭된 게이트 스택의 현미경 사진이다.

Claims (7)

  1. 플라즈마로 기판을 에칭하는 방법에 있어서, 진공 챔버내에서 에칭될 기판을 설치하고, 챔버내에 소정의 압력을 유지하는 동안에 챔버내로 예비 에칭 가스를 도입하고, 상기 챔버내의 코일에 거의 평행한 평면 플라즈마를 형성하기 위해 상기 챔버의 벽에 설치된 유전체 윈도우에 인접하고 상기 챔버 외측에 배치된 평면 코일에 무선 주파수 전류를 공진하고, 상기 챔버내에 기판 지지대 및 평면 코일 양단에 무선 주파수 전위를 인가함으로서, 플라즈마 이온 및 방사선이 평면 기판에 수직인 방향으로 가속되며 그 개선점으로 평면코일에 대한 전력이 약0내지 200와트로 제한되는 단계및 지지 기판에 대한 전력이 에칭중에 50내지 200와트로 제한되는 단계를 포함하는 것을 특징으로 하는 플라즈마 기판을 에칭하는 방법.
  2. 제1항에 있어서, 상기 기판은 기판위에 게이트 산화물 층을 갖는 실리콘이며, 전도성 폴리실리콘 층은 게이트 산화물 층에 중착되고 공간 실리콘 산화물층은 게이트 산화물 층위에 중착되는 것을 특징으로 하는 방법.
  3. 제1항에 있어서, 상기 에칭 가스가 염소와 수소 염화물을 포함하는 혼합물인 것을 특징으로 하는 방법.
  4. 제3항에 있어서, 상기 에칭 가스는 질소 및 산소를 함유하는 것을 특징으로 하는 방법.
  5. 제2항에 있어서, 내화성 금속 실리콘 층이 상기 전도성 폴리실리콘 층위에 중착되는 것을 특징으로 하는 방법.
  6. 제5항에 있어서, 상기 내화성 금속 규화물이 티타늄 규화물인 것을 특징으로 하는 방법.
  7. 제5항에 있어서, 상기 내화성 금속 규화물은 텅스텐 규화물인 것을 특징으로 하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019950054324A 1994-12-22 1995-12-22 플라즈마에칭방법 KR100413894B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/362,398 US5591301A (en) 1994-12-22 1994-12-22 Plasma etching method
US08/362,398 1994-12-22

Publications (2)

Publication Number Publication Date
KR960026340A true KR960026340A (ko) 1996-07-22
KR100413894B1 KR100413894B1 (ko) 2004-04-21

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Country Status (7)

Country Link
US (1) US5591301A (ko)
EP (1) EP0718876B1 (ko)
JP (1) JPH08236513A (ko)
KR (1) KR100413894B1 (ko)
AT (1) ATE320082T1 (ko)
DE (1) DE69534832T2 (ko)
TW (1) TW410401B (ko)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6017825A (en) * 1996-03-29 2000-01-25 Lam Research Corporation Etch rate loading improvement
KR100230981B1 (ko) * 1996-05-08 1999-11-15 김광호 반도체장치 제조공정의 플라즈마 식각 방법
US5880033A (en) * 1996-06-17 1999-03-09 Applied Materials, Inc. Method for etching metal silicide with high selectivity to polysilicon
US6008139A (en) * 1996-06-17 1999-12-28 Applied Materials Inc. Method of etching polycide structures
US6562724B1 (en) * 1997-06-09 2003-05-13 Texas Instruments Incorporated Self-aligned stack formation
US6479785B1 (en) 1998-07-09 2002-11-12 Richard J. Fugo Device for plasma incision of mater with a specifically tuned radiofrequencty electromagnetic field generator
NZ504364A (en) * 1997-10-24 2002-11-26 Richard J Method of plasma incision of matter with a specifically tuned radiofrequency electromagnetic field generator
US5958266A (en) * 1997-10-24 1999-09-28 Fugo; Richard J. Method of plasma incision of matter with a specifically tuned radiofrequency electromagnetic field generator
JPH11145113A (ja) * 1997-11-13 1999-05-28 Nec Corp エッチング方法
EP0932190A1 (en) * 1997-12-30 1999-07-28 International Business Machines Corporation Method of plasma etching the tungsten silicide layer in the gate conductor stack formation
US6787730B2 (en) * 1998-07-09 2004-09-07 Damian Coccio Device for plasma incision of matter with a specifically tuned radiofrequency electromagnetic field generator
US6309926B1 (en) 1998-12-04 2001-10-30 Advanced Micro Devices Thin resist with nitride hard mask for gate etch application
TW501199B (en) 1999-03-05 2002-09-01 Applied Materials Inc Method for enhancing etching of TiSix
US6261967B1 (en) 2000-02-09 2001-07-17 Infineon Technologies North America Corp. Easy to remove hard mask layer for semiconductor device fabrication
EP1156519A1 (en) * 2000-05-16 2001-11-21 Semiconductor 300 GmbH & Co. KG Gate etch process for 12 inch wafers
US6461974B1 (en) 2000-10-06 2002-10-08 Lam Research Corporation High temperature tungsten etching process
US6642584B2 (en) 2001-01-30 2003-11-04 International Business Machines Corporation Dual work function semiconductor structure with borderless contact and method of fabricating the same
WO2008021321A2 (en) * 2006-08-17 2008-02-21 Rjf Holdings Iv, Inc Method and apparatus for plasma incision of cardiovascular tissue
KR100927398B1 (ko) * 2007-06-26 2009-11-19 주식회사 하이닉스반도체 반도체 소자의 미세 패턴 형성 방법
US20120244693A1 (en) * 2011-03-22 2012-09-27 Tokyo Electron Limited Method for patterning a full metal gate structure
US8946002B2 (en) 2012-07-24 2015-02-03 Semiconductor Components Industries, Llc Method of forming a semiconductor device having a patterned gate dielectric and structure therefor
KR101582542B1 (ko) * 2014-08-19 2016-01-05 국방과학연구소 대면적 플라즈마를 이용한 전자기파 감쇠 장치

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4030967A (en) * 1976-08-16 1977-06-21 Northern Telecom Limited Gaseous plasma etching of aluminum and aluminum oxide
US4253907A (en) * 1979-03-28 1981-03-03 Western Electric Company, Inc. Anisotropic plasma etching
US4297162A (en) * 1979-10-17 1981-10-27 Texas Instruments Incorporated Plasma etching using improved electrode
US4444618A (en) * 1983-03-03 1984-04-24 General Electric Company Processes and gas mixtures for the reactive ion etching of aluminum and aluminum alloys
US5112435A (en) * 1985-10-11 1992-05-12 Applied Materials, Inc. Materials and methods for etching silicides, polycrystalline silicon and polycides
JPS62162362A (ja) * 1986-01-10 1987-07-18 Mitsubishi Electric Corp Ｍｏｓ型集積回路及びその製造方法
US4789426A (en) * 1987-01-06 1988-12-06 Harris Corp. Process for performing variable selectivity polysilicon etch
JPS63215076A (ja) * 1987-03-04 1988-09-07 Matsushita Electric Ind Co Ltd 半導体集積回路装置
JPS63238288A (ja) * 1987-03-27 1988-10-04 Fujitsu Ltd ドライエツチング方法
US4838992A (en) * 1987-05-27 1989-06-13 Northern Telecom Limited Method of etching aluminum alloys in semi-conductor wafers
US5248636A (en) * 1987-07-16 1993-09-28 Texas Instruments Incorporated Processing method using both a remotely generated plasma and an in-situ plasma with UV irradiation
US4948458A (en) 1989-08-14 1990-08-14 Lam Research Corporation Method and apparatus for producing magnetically-coupled planar plasma
JP2673380B2 (ja) * 1990-02-20 1997-11-05 三菱電機株式会社 プラズマエッチングの方法
KR0176715B1 (ko) * 1990-07-30 1999-04-15 오가 노리오 드라이에칭방법
US5259922A (en) * 1990-08-14 1993-11-09 Matsushita Electric Industrial Co., Ltd. Drying etching method
JPH04196529A (ja) * 1990-11-28 1992-07-16 Toshiba Corp プラズマ処理装置
JP2519364B2 (ja) * 1990-12-03 1996-07-31 アプライド マテリアルズ インコーポレイテッド Ｕｈｆ／ｖｈｆ共振アンテナ供給源を用いたプラズマリアクタ
DE4107006A1 (de) * 1991-03-05 1992-09-10 Siemens Ag Verfahren zum anisotropen trockenaetzen von aluminium bzw. aluminiumlegierungen enthaltenden leiterbahnebenen in integrierten halbleiterschaltungen
US5201990A (en) * 1991-05-23 1993-04-13 Applied Materials, Inc. Process for treating aluminum surfaces in a vacuum apparatus
JPH0582481A (ja) * 1991-09-18 1993-04-02 Nippon Telegr & Teleph Corp <Ntt> ガーネツト膜加工方法
US5323053A (en) * 1992-05-28 1994-06-21 At&T Bell Laboratories Semiconductor devices using epitaxial silicides on (111) surfaces etched in (100) silicon substrates
US5346578A (en) * 1992-11-04 1994-09-13 Novellus Systems, Inc. Induction plasma source
US5401350A (en) * 1993-03-08 1995-03-28 Lsi Logic Corporation Coil configurations for improved uniformity in inductively coupled plasma systems
US5449433A (en) * 1994-02-14 1995-09-12 Micron Semiconductor, Inc. Use of a high density plasma source having an electrostatic shield for anisotropic polysilicon etching over topography

Also Published As

Publication number Publication date
EP0718876B1 (en) 2006-03-08
TW410401B (en) 2000-11-01
EP0718876A3 (en) 1998-05-20
DE69534832D1 (de) 2006-05-04
US5591301A (en) 1997-01-07
DE69534832T2 (de) 2006-09-28
JPH08236513A (ja) 1996-09-13
KR100413894B1 (ko) 2004-04-21
EP0718876A2 (en) 1996-06-26
ATE320082T1 (de) 2006-03-15

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