KR960012810A - 망동기용 디지탈 위상동기루프 제어방법 - Google Patents

망동기용 디지탈 위상동기루프 제어방법 Download PDF

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KR960012810A
KR960012810A KR1019940023408A KR19940023408A KR960012810A KR 960012810 A KR960012810 A KR 960012810A KR 1019940023408 A KR1019940023408 A KR 1019940023408A KR 19940023408 A KR19940023408 A KR 19940023408A KR 960012810 A KR960012810 A KR 960012810A
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phase difference
mode
average value
phase
value
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KR1019940023408A
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KR0177731B1 (ko
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박중희
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정장호
엘지정보통신 주식회사
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Priority to KR1019940023408A priority Critical patent/KR0177731B1/ko
Priority to US08/526,574 priority patent/US5673004A/en
Priority to RU95115985/09A priority patent/RU2154895C2/ru
Priority to CN95117703A priority patent/CN1080050C/zh
Publication of KR960012810A publication Critical patent/KR960012810A/ko
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/101—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop
    • H03L7/102—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop the additional signal being directly applied to the controlled loop oscillator
    • H03L7/103—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using an additional control signal to the controlled loop oscillator derived from a signal generated in the loop the additional signal being directly applied to the controlled loop oscillator the additional signal being a digital signal
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/107—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/14—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted
    • H03L7/143—Details of the phase-locked loop for assuring constant frequency when supply or correction voltages fail or are interrupted by switching the reference signal of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0688—Change of the master or reference, e.g. take-over or failure of the master
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • H04J3/0691—Synchronisation in a TDM node
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S331/00—Oscillators
    • Y10S331/02—Phase locked loop having lock indicating or detecting means

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

본 발명은 망동기용 DP-PLL(Digital Processing - Phase Locked Loop)의 제어 알고리즘에 관한 것으로, 특히 동작 모드 천이시 발생되는 위상 불연속(Phase-hit)을 방지하기 위한 망동기용 디지털 위상 동기 루프 제어방법에 관한 것이다.
종래의 망동기용 DP-PLL장치는 절대위상차는 검출이 가능하나 기준 클럭과 시스템 클럭사이의 위상변화는 검출이 불가능하므로 클럭원 절체 및 동작 모드 천이시 위상 불연속(Phase-hit)이 발생되는 문제점이 있었다.
따라서 본 발명은 프리 런 모드에서 기준 클럭 신호의 이상이 모니터 되지 않으면 정상으로 판단하여 패스트 모드로 천이하여 디지털 위상동기루프를 제어하는 방법에 있어서, 상기 프리 런 모드에서 패스트 모드로 천이한 후 초기과정에서 위상차 데이터를 일정기간 축적하고 평균치를 구하여 이를 패스트 모드에서의 기준 위상차로 설정하는 제1과정과, 상기 위상차 데이터가 기준 위상차에 수렴하도록 전압 제어 발진부의 제어값을 산출하여 제어하는 제2과정과, 상기 패스트 모드가 안정되면 노르말 모드로 천이한 후 초기과정에서 일정기간동안 상기 검출한 위상차 데이터(PD)를 축적하고 평균치를 구하여 이를 노르말 모드에서의 기준위상차로 설정을 하고 이에 수렴하는 전압 제어 발진부의 제어값을 산출하여 제어하는 제3과정을 순차실행시켜 종래기술의 제반 문제점을 해결하였다.

Description

망동기용 디지털 위상동기루프 제어방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제3도는 본 발명이 적용되는 망동기용 디지털 위상동기루프 장치 구성도.
제4도는 제3도의 각부 입, 출력 파형도.
제5도는 본 발명 망동기용 디지털 위상동기루프 장치의 모드 선택신호흐름도.

Claims (2)

  1. 프리 런 모드에서 기준 클럭 신호의 이상이 모니터 되지 않으면 정상으로 판단하여 패스트 모드로 천이하여 디지털 위상동기루프를 제어하는 방법에 있어서, 상기 프리런 모드에서 패스트 모드로 천이한 후 초기과정에서 위상차 데이터를 일정기간 축적하고 평균치를 구하여 이를 패스트 모드에서의 기준 위상차로 설정하는 제1과정과, 상기 위상차 데이터가 기준 위상차에 수렴하도록 전압 제어 발진부의 제어값을 산출하여 제어하는 제 2 과정과, 상기 패스트 모드가 안정되면 노르말 모드로 천이한 후 초기과정에서 일정기간동안 상기 검출한 위상차 데이터(PD)를 축적하고 평균치를 구하여 이를 노르말 모드에서의 기준위상차로 설정을 하고 이에 수렴하는 전압 제어 발진부의 제어값을 산출하여 제어하는 제 3 과정으로 이루어짐을 특징으로 하는 망동기용 디지털 위상동기루프 제어방법.
  2. 제1항에 있어서, 상기 노르말 모드에서 천이한 후 일정기간의 데이터(PD)의 평균치에 노르말 모드에서의 전압 제어 발진부의 제어값으로 부터 역 산출된 현재의 위상차 데이터의 평균치를 감산한 결과값을 기준 위상차로 설정하여 전압 제어 발진부의 제어값을 산출하여 제어하는 제4과정과, 상기 홀드오버 모드에서 기준클럭이 정상적으로 모니터되면 패스트 모드로 천이하고 일정기간의 위상차 데이터의 평균치에 홀드오버 모드에서 전압 제어 발진부의 제어값으로 부터 역산출된 현재의 위상차 데이터의 평균치를 감산한 결과 값을 기준 위상차로 설정하고 전압제어 발진부의 제어값을 산출하여 제어하는 제5과정을 더 포함하여 이루어짐을 특징으로 하는 망동기용 디지털 위상동기루프 제어방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940023408A 1994-09-15 1994-09-15 망동기용 디지탈 위상동기루프 제어방법 KR0177731B1 (ko)

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Application Number Priority Date Filing Date Title
KR1019940023408A KR0177731B1 (ko) 1994-09-15 1994-09-15 망동기용 디지탈 위상동기루프 제어방법
US08/526,574 US5673004A (en) 1994-09-15 1995-09-11 Method and circuit for controlling digital processing phase-locked loop for network synchronization
RU95115985/09A RU2154895C2 (ru) 1994-09-15 1995-09-14 Способ и схема управления системой фазовой автоподстройки частоты с цифровой обработкой для сетевой синхронизации
CN95117703A CN1080050C (zh) 1994-09-15 1995-09-15 用于控制数字处理锁相环路以实现网络同步的方法和电路

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KR1019940023408A KR0177731B1 (ko) 1994-09-15 1994-09-15 망동기용 디지탈 위상동기루프 제어방법

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KR0177731B1 KR0177731B1 (ko) 1999-05-15

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US5136617A (en) * 1990-12-03 1992-08-04 At&T Bell Laboratories Switching technique for attaining synchronization

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US5673004A (en) 1997-09-30
CN1127447A (zh) 1996-07-24
CN1080050C (zh) 2002-02-27
KR0177731B1 (ko) 1999-05-15
RU2154895C2 (ru) 2000-08-20

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