KR960009224A - P-mos 트랜지스터의 핫 캐리어 열화의 시뮬레이션 방법 - Google Patents

P-mos 트랜지스터의 핫 캐리어 열화의 시뮬레이션 방법 Download PDF

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Publication number
KR960009224A
KR960009224A KR1019950025317A KR19950025317A KR960009224A KR 960009224 A KR960009224 A KR 960009224A KR 1019950025317 A KR1019950025317 A KR 1019950025317A KR 19950025317 A KR19950025317 A KR 19950025317A KR 960009224 A KR960009224 A KR 960009224A
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KR
South Korea
Prior art keywords
mos transistors
simulation method
hot carrier
carrier degradation
degradation
Prior art date
Application number
KR1019950025317A
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English (en)
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KR0162540B1 (ko
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Publication of KR960009224A publication Critical patent/KR960009224A/ko
Application granted granted Critical
Publication of KR0162540B1 publication Critical patent/KR0162540B1/ko

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Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26Testing of individual semiconductor devices
    • G01R31/2607Circuits therefor
    • G01R31/2621Circuits therefor for testing field effect transistors, i.e. FET's
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
KR1019950025317A 1994-08-19 1995-08-17 P-mos 트랜지스터의 핫 캐리어 열화의 시뮬레이션 방법 KR0162540B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP94-195071 1994-08-19
JP19507194A JP3380054B2 (ja) 1994-08-19 1994-08-19 P−mosトランジスタのホットキャリア劣化のシミュレーション方法

Publications (2)

Publication Number Publication Date
KR960009224A true KR960009224A (ko) 1996-03-22
KR0162540B1 KR0162540B1 (ko) 1998-12-01

Family

ID=16335078

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950025317A KR0162540B1 (ko) 1994-08-19 1995-08-17 P-mos 트랜지스터의 핫 캐리어 열화의 시뮬레이션 방법

Country Status (3)

Country Link
US (1) US5615377A (ko)
JP (1) JP3380054B2 (ko)
KR (1) KR0162540B1 (ko)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100796511B1 (ko) * 2006-07-31 2008-01-21 동부일렉트로닉스 주식회사 Mosfet에서 드레인 포화 전압을 구하는 방법

Families Citing this family (24)

* Cited by examiner, † Cited by third party
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US6073082A (en) * 1996-04-11 2000-06-06 Mitsubishi Denki Kabushiki Kaisha Method of estimating lifetime of floating SOI-MOSFET
US6049213A (en) * 1998-01-27 2000-04-11 International Business Machines Corporation Method and system for testing the reliability of gate dielectric films
US6278964B1 (en) * 1998-05-29 2001-08-21 Matsushita Electric Industrial Co., Ltd. Hot carrier effect simulation for integrated circuits
JP3125870B2 (ja) * 1998-07-06 2001-01-22 日本電気株式会社 遅延計算方法及び遅延値計算プログラムを記録した記録媒体
US6198301B1 (en) * 1998-07-23 2001-03-06 Lucent Technologies Inc. Method for determining the hot carrier lifetime of a transistor
JP3382544B2 (ja) * 1998-09-14 2003-03-04 沖電気工業株式会社 Mosfetのシミュレーション方法及び装置
US6188234B1 (en) 1999-01-07 2001-02-13 International Business Machines Corporation Method of determining dielectric time-to-breakdown
US6530064B1 (en) * 1999-12-29 2003-03-04 Texas Instruments Incorporated Method and apparatus for predicting an operational lifetime of a transistor
US6425111B1 (en) * 1999-12-30 2002-07-23 The Board Of Trustees Of The Leland Stanford Junior University Saturation region transistor modeling for geometric programming
JP3405713B2 (ja) 2000-06-27 2003-05-12 松下電器産業株式会社 半導体装置の寿命推定方法および信頼性シミュレーション方法
US7292968B2 (en) * 2000-09-29 2007-11-06 Cadence Design Systems, Inc. Hot carrier circuit reliability simulation
US7567891B1 (en) * 2000-09-29 2009-07-28 Cadence Design Systems, Inc. Hot-carrier device degradation modeling and extraction methodologies
US6583641B2 (en) * 2001-04-25 2003-06-24 United Microelectronics Corp. Method of determining integrity of a gate dielectric
US7106088B2 (en) * 2005-01-10 2006-09-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method of predicting high-k semiconductor device lifetime
TW200809748A (en) * 2006-08-09 2008-02-16 Ind Tech Res Inst Method for simulating circuit reliability and system thereof
US8362794B2 (en) * 2009-07-23 2013-01-29 International Business Machines Corporation Method and system for assessing reliability of integrated circuit
US9141735B2 (en) * 2010-06-18 2015-09-22 Taiwan Semiconductor Manufacturing Company, Ltd. Circuit device reliability simulation system
CN103310028B (zh) 2012-03-07 2017-08-15 飞思卡尔半导体公司 考虑器件老化的设计集成电路的方法
CN102707227B (zh) * 2012-05-17 2014-07-23 深港产学研基地 一种场效应晶体管阈值电压提取方法
KR102087441B1 (ko) * 2012-10-17 2020-03-11 매그나칩 반도체 유한회사 웨이퍼 레벨 신뢰도 강화방법
US9213787B1 (en) * 2014-03-31 2015-12-15 Cadence Design Systems, Inc. Simulation based system and method for gate oxide reliability enhancement
KR102070722B1 (ko) 2019-06-11 2020-01-29 영현전력기술 주식회사 배전선로의 전신주 애자 설치 구조
US11537768B2 (en) * 2020-03-16 2022-12-27 Nanya Technology Corporation Method for aging simulation model establishment
CN113049936B (zh) * 2021-03-12 2022-08-19 鲁明亮 一种提取cmos器件中迁移率和源漏极串联电阻的方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4816753A (en) * 1987-05-21 1989-03-28 Advanced Research And Applications Corporation Method for reliability testing of integrated circuits
JPH0448640A (ja) * 1990-06-14 1992-02-18 Oki Electric Ind Co Ltd Mosトランジスタの製造方法
DE69329543T2 (de) * 1992-12-09 2001-05-31 Compaq Computer Corp Herstellung eines Feldeffekttransistors mit integrierter Schottky-Klammerungsdiode
JP2736501B2 (ja) * 1993-09-28 1998-04-02 三菱電機株式会社 Mos型トランジスタのホットキャリア劣化のシミュレーション方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100796511B1 (ko) * 2006-07-31 2008-01-21 동부일렉트로닉스 주식회사 Mosfet에서 드레인 포화 전압을 구하는 방법

Also Published As

Publication number Publication date
JPH0864814A (ja) 1996-03-08
US5615377A (en) 1997-03-25
KR0162540B1 (ko) 1998-12-01
JP3380054B2 (ja) 2003-02-24

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