KR950034610A - 전기적 접속부 제조 방법 및 반도체 디바이스 - Google Patents

전기적 접속부 제조 방법 및 반도체 디바이스 Download PDF

Info

Publication number
KR950034610A
KR950034610A KR1019950010066A KR19950010066A KR950034610A KR 950034610 A KR950034610 A KR 950034610A KR 1019950010066 A KR1019950010066 A KR 1019950010066A KR 19950010066 A KR19950010066 A KR 19950010066A KR 950034610 A KR950034610 A KR 950034610A
Authority
KR
South Korea
Prior art keywords
layer
organic
conductors
inorganic
cap layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
KR1019950010066A
Other languages
English (en)
Korean (ko)
Inventor
에이치. 해브만 로버트
Original Assignee
윌리엄 이.힐러
텍사스 인스트루먼츠 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 윌리엄 이.힐러, 텍사스 인스트루먼츠 인코포레이티드 filed Critical 윌리엄 이.힐러
Publication of KR950034610A publication Critical patent/KR950034610A/ko
Abandoned legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/074Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/074Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/01Manufacture or treatment
    • H10W20/071Manufacture or treatment of dielectric parts thereof
    • H10W20/081Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/082Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts the openings being tapered via holes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48Insulating materials thereof
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00Interconnections in chips, wafers or substrates
    • H10W20/40Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495Capacitive arrangements or effects of, or between wiring layers

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1019950010066A 1994-04-28 1995-04-27 전기적 접속부 제조 방법 및 반도체 디바이스 Abandoned KR950034610A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US23409994A 1994-04-28 1994-04-28
US8/234,099 1994-04-28

Publications (1)

Publication Number Publication Date
KR950034610A true KR950034610A (ko) 1995-12-28

Family

ID=22879928

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019950010066A Abandoned KR950034610A (ko) 1994-04-28 1995-04-27 전기적 접속부 제조 방법 및 반도체 디바이스

Country Status (6)

Country Link
US (1) US6188125B1 (https=)
EP (1) EP0680085B1 (https=)
JP (1) JPH08139194A (https=)
KR (1) KR950034610A (https=)
DE (1) DE69512125T2 (https=)
TW (1) TW271005B (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970067387A (ko) * 1996-03-22 1997-10-13 윌리엄 비. 켐플러 금속간 유전체를 갖는 반도체 장치와 그 제조 방법

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH09129727A (ja) * 1995-10-30 1997-05-16 Nec Corp 半導体装置及びその製造方法
FR2747511B1 (fr) 1996-04-10 1998-09-04 Sgs Thomson Microelectronics Interconnexions multicouches a faible capacite parasite laterale
JPH10223624A (ja) 1997-02-06 1998-08-21 Nec Yamagata Ltd 半導体装置の製造方法
JPH10335458A (ja) 1997-05-30 1998-12-18 Nec Corp 半導体装置及びその製造方法
US6294455B1 (en) 1997-08-20 2001-09-25 Micron Technology, Inc. Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry
JP3199006B2 (ja) * 1997-11-18 2001-08-13 日本電気株式会社 層間絶縁膜の形成方法および絶縁膜形成装置
US6197696B1 (en) * 1998-03-26 2001-03-06 Matsushita Electric Industrial Co., Ltd. Method for forming interconnection structure
FR2777697B1 (fr) * 1998-04-16 2000-06-09 St Microelectronics Sa Circuit integre avec couche d'arret et procede de fabrication associe
US20010029091A1 (en) * 1998-04-17 2001-10-11 U.S. Philips Corporation Method for manufacturing an electronic device comprising an organic- containing material
JP3102409B2 (ja) * 1998-04-30 2000-10-23 日本電気株式会社 配線の形成方法及びプラズマアッシング装置
US6127263A (en) * 1998-07-10 2000-10-03 Applied Materials, Inc. Misalignment tolerant techniques for dual damascene fabrication
US6391771B1 (en) 1998-07-23 2002-05-21 Applied Materials, Inc. Integrated circuit interconnect lines having sidewall layers
TW437040B (en) 1998-08-12 2001-05-28 Applied Materials Inc Interconnect line formed by dual damascene using dielectric layers having dissimilar etching characteristics
US6071809A (en) * 1998-09-25 2000-06-06 Rockwell Semiconductor Systems, Inc. Methods for forming high-performing dual-damascene interconnect structures
US6225207B1 (en) * 1998-10-01 2001-05-01 Applied Materials, Inc. Techniques for triple and quadruple damascene fabrication
US6309801B1 (en) 1998-11-18 2001-10-30 U.S. Philips Corporation Method of manufacturing an electronic device comprising two layers of organic-containing material
US6258732B1 (en) * 1999-02-04 2001-07-10 International Business Machines Corporation Method of forming a patterned organic dielectric layer on a substrate
US6770975B2 (en) 1999-06-09 2004-08-03 Alliedsignal Inc. Integrated circuits with multiple low dielectric-constant inter-metal dielectrics
EP1077475A3 (en) * 1999-08-11 2003-04-02 Applied Materials, Inc. Method of micromachining a multi-part cavity
DE19961103C2 (de) * 1999-12-17 2002-03-14 Infineon Technologies Ag Dielektrische Füllung von elektrischen Verdrahtungsebenen und Verfahren zur Herstellung einer elektrischen Verdrahtung
US6720249B1 (en) * 2000-04-17 2004-04-13 International Business Machines Corporation Protective hardmask for producing interconnect structures
DE10127934A1 (de) * 2001-06-08 2002-12-19 Infineon Technologies Ag Leiterbahnanordnung und Verfahren zum Herstellen einer gekapselten Leiterbahnkopplung
DE10146146B4 (de) * 2001-09-19 2004-02-05 Infineon Technologies Ag Verfahren zur elektrischen Isolation nebeneinander liegender metallischer Leiterbahnen und Halbleiterbauelement mit voneinander isolierten metallischen Leiterbahnen
JP3667303B2 (ja) 2002-06-04 2005-07-06 沖電気工業株式会社 多層配線構造部の製造方法
US6878620B2 (en) * 2002-11-12 2005-04-12 Applied Materials, Inc. Side wall passivation films for damascene cu/low k electronic devices
DE10301243B4 (de) 2003-01-15 2009-04-16 Infineon Technologies Ag Verfahren zum Herstellen einer integrierten Schaltungsanordnung, insbesondere mit Kondensatoranordnung
US7608538B2 (en) * 2007-01-05 2009-10-27 International Business Machines Corporation Formation of vertical devices by electroplating
US9505609B2 (en) * 2015-04-29 2016-11-29 Invensense, Inc. CMOS-MEMS integrated device with selective bond pad protection
DE102019131408B4 (de) 2019-06-28 2025-12-04 Taiwan Semiconductor Manufacturing Company, Ltd. Verbesserte Kontaktierung von Metallleitungen bei Fehlausrichtung von BEOL-Durchkontaktierungen
CN112151497B (zh) 2019-06-28 2023-08-22 台湾积体电路制造股份有限公司 半导体结构以及形成半导体结构的方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4523372A (en) * 1984-05-07 1985-06-18 Motorola, Inc. Process for fabricating semiconductor device
JPS6185844A (ja) * 1984-09-28 1986-05-01 シーメンス、アクチエンゲゼルヤフト 集積回路とその製法
JPH01235254A (ja) 1988-03-15 1989-09-20 Nec Corp 半導体装置及びその製造方法
JP2782801B2 (ja) * 1989-06-23 1998-08-06 日本電気株式会社 半導体装置の配線構造
JPH04174541A (ja) 1990-03-28 1992-06-22 Nec Corp 半導体集積回路及びその製造方法
JPH04233732A (ja) * 1990-08-16 1992-08-21 Motorola Inc 半導体の製造工程で使用するスピン・オン誘電体
US5284801A (en) * 1992-07-22 1994-02-08 Vlsi Technology, Inc. Methods of moisture protection in semiconductor devices utilizing polyimides for inter-metal dielectric
JPH0697299A (ja) * 1992-09-11 1994-04-08 Nec Yamagata Ltd 半導体装置

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970067387A (ko) * 1996-03-22 1997-10-13 윌리엄 비. 켐플러 금속간 유전체를 갖는 반도체 장치와 그 제조 방법

Also Published As

Publication number Publication date
DE69512125T2 (de) 2000-04-20
JPH08139194A (ja) 1996-05-31
EP0680085A1 (en) 1995-11-02
EP0680085B1 (en) 1999-09-15
DE69512125D1 (de) 1999-10-21
US6188125B1 (en) 2001-02-13
TW271005B (https=) 1996-02-21

Similar Documents

Publication Publication Date Title
KR950034610A (ko) 전기적 접속부 제조 방법 및 반도체 디바이스
US5935868A (en) Interconnect structure and method to achieve unlanded vias for low dielectric constant materials
US6331481B1 (en) Damascene etchback for low ε dielectric
US6177329B1 (en) Integrated circuit structures having gas pockets and method for forming integrated circuit structures having gas pockets
US6309801B1 (en) Method of manufacturing an electronic device comprising two layers of organic-containing material
US9640435B2 (en) Patterning approach for improved via landing profile
US6037255A (en) Method for making integrated circuit having polymer interlayer dielectric
US5798559A (en) Integrated circuit structure having an air dielectric and dielectric support pillars
US6696222B2 (en) Dual damascene process using metal hard mask
US7232736B2 (en) Semiconductor devices with capacitors of metal/insulator/metal structure and methods for forming the same
CN1284226C (zh) 有机夹层介电材料中的铜通路的剪切应力的减小
US6309955B1 (en) Method for using a CVD organic barc as a hard mask during via etch
US20050024979A1 (en) Metal-insulator-metal capacitor and interconnecting structure
KR950034792A (ko) 집적된 저밀도 유전체와의 상호 접속 구조
US20030143832A1 (en) Dielectric between metal structures and method therefor
US6576550B1 (en) ‘Via first’ dual damascene process for copper metallization
US5960316A (en) Method to fabricate unlanded vias with a low dielectric constant material as an intraline dielectric
US6054380A (en) Method and apparatus for integrating low dielectric constant materials into a multilevel metallization and interconnect structure
US6632707B1 (en) Method for forming an interconnect structure using a CVD organic BARC to mitigate via poisoning
US20070194448A1 (en) Semiconductor interconnection line and method of forming the same
EP0507881A1 (en) Semiconductor interconnect structure utilizing a polyimide insulator
US6204096B1 (en) Method for reducing critical dimension of dual damascene process using spin-on-glass process
JP4717972B2 (ja) 集積回路の製造方法
EP0917199A2 (en) Improvements in or relating to semiconductor devices
KR100909177B1 (ko) 듀얼 다마신 패턴 형성 방법

Legal Events

Date Code Title Description
PA0109 Patent application

St.27 status event code: A-0-1-A10-A12-nap-PA0109

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

R17-X000 Change to representative recorded

St.27 status event code: A-3-3-R10-R17-oth-X000

A201 Request for examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

NORF Unpaid initial registration fee
PC1904 Unpaid initial registration fee

St.27 status event code: A-2-2-U10-U13-oth-PC1904

St.27 status event code: N-2-6-B10-B12-nap-PC1904

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000

P22-X000 Classification modified

St.27 status event code: A-2-2-P10-P22-nap-X000