KR950013606B1 - Ic의 테스트 핀을 이용한 테스트 모드설정회로 - Google Patents
Ic의 테스트 핀을 이용한 테스트 모드설정회로 Download PDFInfo
- Publication number
- KR950013606B1 KR950013606B1 KR1019880014002A KR880014002A KR950013606B1 KR 950013606 B1 KR950013606 B1 KR 950013606B1 KR 1019880014002 A KR1019880014002 A KR 1019880014002A KR 880014002 A KR880014002 A KR 880014002A KR 950013606 B1 KR950013606 B1 KR 950013606B1
- Authority
- KR
- South Korea
- Prior art keywords
- test
- test mode
- type mosfet
- input
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
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- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Logic Circuits (AREA)
Abstract
Description
Claims (1)
- IC(100) 테스트핀의 입력단자(Tin)를 통해 입력되는 입력전압을 감지하도록 P형 MOSFET(P1, P2)와 N형 MOSFET(N1, N2)를 사용하여 각각 직렬로 연결함과 동시에 그 게이트 단자(G)를 전원단자(Vcc)에 연결하고, P형 MOSFET(P1)의 소오스단자(S)에 테스트핀의 입력단자(Tin)를 연결하며, 상기 P형 MOSFET(P1, P2)와 N형 MOSFET(N1, N2)의 출력에 연결된 접속점(a,b)과 테스트 핀의 입력단자(Tin)를 통해 인버터(I1, I2), NOR게이트(G1, G2) 및 AND게이트(G3, G2)로 구성된 디코더(10)로 디코딩하여 노멀모드(Noutr)와 테스트 모드(Tout1, Tout2, Tout3)가 출력되도록 구성된 것을 특징으로 하는 IC의 테스트핀을 이용한 테스트모드 설정회로.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019880014002A KR950013606B1 (ko) | 1988-10-27 | 1988-10-27 | Ic의 테스트 핀을 이용한 테스트 모드설정회로 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019880014002A KR950013606B1 (ko) | 1988-10-27 | 1988-10-27 | Ic의 테스트 핀을 이용한 테스트 모드설정회로 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR900006791A KR900006791A (ko) | 1990-05-08 |
KR950013606B1 true KR950013606B1 (ko) | 1995-11-13 |
Family
ID=19278789
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019880014002A Expired - Fee Related KR950013606B1 (ko) | 1988-10-27 | 1988-10-27 | Ic의 테스트 핀을 이용한 테스트 모드설정회로 |
Country Status (1)
Country | Link |
---|---|
KR (1) | KR950013606B1 (ko) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100862994B1 (ko) * | 2006-12-07 | 2008-10-13 | 주식회사 하이닉스반도체 | 테스트 모드 구동 회로를 포함한 반도체 메모리 장치 및테스트 모드 구동 방법 |
US7574638B2 (en) | 2005-02-03 | 2009-08-11 | Samsung Electronics Co., Ltd. | Semiconductor device tested using minimum pins and methods of testing the same |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100394575B1 (ko) * | 2001-04-11 | 2003-08-14 | 삼성전자주식회사 | 반도체 메모리의 테스트용 핀을 통한 내부정보 선택적출력방법 및 그에 따른 출력회로 |
KR100496859B1 (ko) * | 2002-08-13 | 2005-06-22 | 삼성전자주식회사 | 동작모드 설정기능을 가진 반도체 집적회로 |
KR100706241B1 (ko) * | 2005-02-04 | 2007-04-11 | 삼성전자주식회사 | 테스트 핀을 사용하지 않고 테스트할 수 있는 시스템-온-칩 및 테스트 방법 |
-
1988
- 1988-10-27 KR KR1019880014002A patent/KR950013606B1/ko not_active Expired - Fee Related
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7574638B2 (en) | 2005-02-03 | 2009-08-11 | Samsung Electronics Co., Ltd. | Semiconductor device tested using minimum pins and methods of testing the same |
KR100862994B1 (ko) * | 2006-12-07 | 2008-10-13 | 주식회사 하이닉스반도체 | 테스트 모드 구동 회로를 포함한 반도체 메모리 장치 및테스트 모드 구동 방법 |
US7831405B2 (en) | 2006-12-07 | 2010-11-09 | Hynix Semiconductor Inc. | Semiconductor package capable of performing various tests and method of testing the same |
Also Published As
Publication number | Publication date |
---|---|
KR900006791A (ko) | 1990-05-08 |
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Legal Events
Date | Code | Title | Description |
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PA0109 | Patent application |
Patent event code: PA01091R01D Comment text: Patent Application Patent event date: 19881027 |
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PG1501 | Laying open of application | ||
A201 | Request for examination | ||
PA0201 | Request for examination |
Patent event code: PA02012R01D Patent event date: 19931012 Comment text: Request for Examination of Application Patent event code: PA02011R01I Patent event date: 19881027 Comment text: Patent Application |
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G160 | Decision to publish patent application | ||
PG1605 | Publication of application before grant of patent |
Comment text: Decision on Publication of Application Patent event code: PG16051S01I Patent event date: 19951017 |
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E701 | Decision to grant or registration of patent right | ||
PE0701 | Decision of registration |
Patent event code: PE07011S01D Comment text: Decision to Grant Registration Patent event date: 19960205 |
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GRNT | Written decision to grant | ||
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Comment text: Registration of Establishment Patent event date: 19960229 Patent event code: PR07011E01D |
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