KR940020535A - 리드 온 칩(loc) 패키지 제조방법 - Google Patents

리드 온 칩(loc) 패키지 제조방법 Download PDF

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Publication number
KR940020535A
KR940020535A KR1019930002390A KR930002390A KR940020535A KR 940020535 A KR940020535 A KR 940020535A KR 1019930002390 A KR1019930002390 A KR 1019930002390A KR 930002390 A KR930002390 A KR 930002390A KR 940020535 A KR940020535 A KR 940020535A
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KR
South Korea
Prior art keywords
wafer
lead
chip
polyimide tape
package
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KR1019930002390A
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English (en)
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KR100253267B1 (ko
Inventor
전흥섭
Original Assignee
문정환
금성일렉트론 주식회사
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Priority to KR1019930002390A priority Critical patent/KR100253267B1/ko
Publication of KR940020535A publication Critical patent/KR940020535A/ko
Application granted granted Critical
Publication of KR100253267B1 publication Critical patent/KR100253267B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73215—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

본 발명은 리드 온 칩(LOC) 패키지 제조방법에 관한 것으로, 종래 방법의 리드 프레임의 단가상승 및 보관상의 어려움을 해소하고, 다이 어태치 공정의 까다로움을 해소하기 위한 것인 바, 이러한 본 발명의 리드온 칩 패키지 제조방법은 단위공정을 완료한 웨이퍼(11)의 상면 전면에 걸쳐 폴리이미드 테이프(12)를 라미네이션 한후 그위에 피알(13)을 스핀코팅하는 단계와, 이와같이 된 웨이퍼(11)의 상부에 리드 위치를 디화인하기 위한 패턴(14a)을 가지는 글래스 마스크(14)를 탑재하여 익스포우져 공정 및 디벨로프 공정으로 웨이퍼(11)의 스크라이브레인 위치 및 칩 본드패드(15)위치의 피알(13)층을 오픈하는 단계와, 상기 피알(13)층의 오픈으로 노출된 폴리이미드 테이프(12)부분을 케미컬 에칭하여 제거함과 아울러 최종적으로 여분의 피알층을 제거하는 단계를 거쳐 웨이퍼상의 각 칩위에 리드부착을 위한 폴리이미드 테이프 패턴을 형성하는 공정을 행한후, 통상적인 소잉공정, 다이 어태치 공정, 와이어 본딩공정, 몰딩공정 및 트림/포밍 공정을 진행함을 특징으로 하고 있다.

Description

리드 온 칩(LOC) 패키지 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제4도는 본 발명에 의한 리드 온 칩(LOC) 패키지의 제조공정 플로우 챠트,
제5도의 (가)(나)(다)(라)는 본 발명 폴리이미드 테이프 패턴 형성 공정을 단계별로 도시한 공정도.

Claims (1)

  1. 반도체칩의 상면에 리드프레임의 리드들이 위치되어 구성되는 리드 온 칩(LOC) 패키지를 제조함에 있어서, 단위공정을 완료한 웨이퍼(11)의 상면 전면에 걸쳐 폴리이미드 테이프(12)를 라미네이션 한후 그위에 피알(13)을 스핀 코팅하는 단계와, 이와같이 된 웨이퍼(11)의 상부에 리드 위치를 디화인하기 위한 패턴(14a)을 가지는 글래스 마스크(14)를 탑재하여 익스포우져 공정 및 디벨로프 공정으로 웨이퍼(11)의 스크라이브레인 위치 및 칩 본드패드(15)위치의 피알(13)층을 오픈하는 단계와, 상기 피알(13)층의 오픈으로 노출된 폴리이미드 테이프(12)부분을 케미컬 에칭하여 제거함과 아울러 최종적으로 여분의 피알층을 제거하는 단계를 거쳐 웨이퍼상의 각 칩위에 리드부착을 위한 폴리이미드 테이프 패턴을 형성하는 공정을 행한후, 통상적인 소잉공정, 다이 어태치 공정, 와이어 본딩공정, 몰딩공정 및 트림/포밍 공정을 진행함을 특징으로 하는 리드 온 칩(LOC) 패키지 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930002390A 1993-02-20 1993-02-20 리드 온 칩(loc)패키지 제조방법 KR100253267B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019930002390A KR100253267B1 (ko) 1993-02-20 1993-02-20 리드 온 칩(loc)패키지 제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019930002390A KR100253267B1 (ko) 1993-02-20 1993-02-20 리드 온 칩(loc)패키지 제조방법

Publications (2)

Publication Number Publication Date
KR940020535A true KR940020535A (ko) 1994-09-16
KR100253267B1 KR100253267B1 (ko) 2000-04-15

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Application Number Title Priority Date Filing Date
KR1019930002390A KR100253267B1 (ko) 1993-02-20 1993-02-20 리드 온 칩(loc)패키지 제조방법

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