KR940020510A - 반도체 기판 및 그 제조방법 - Google Patents
반도체 기판 및 그 제조방법 Download PDFInfo
- Publication number
- KR940020510A KR940020510A KR1019940003032A KR19940003032A KR940020510A KR 940020510 A KR940020510 A KR 940020510A KR 1019940003032 A KR1019940003032 A KR 1019940003032A KR 19940003032 A KR19940003032 A KR 19940003032A KR 940020510 A KR940020510 A KR 940020510A
- Authority
- KR
- South Korea
- Prior art keywords
- heat treatment
- pieces
- hours
- semiconductor substrate
- depth
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 4
- 239000004065 semiconductor Substances 0.000 title claims 6
- 239000000758 substrate Substances 0.000 title claims 5
- 238000010438 heat treatment Methods 0.000 claims abstract 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract 3
- 230000015572 biosynthetic process Effects 0.000 claims abstract 3
- 229910052760 oxygen Inorganic materials 0.000 claims abstract 3
- 239000001301 oxygen Substances 0.000 claims abstract 3
- 230000001590 oxidative effect Effects 0.000 claims abstract 2
- 239000013078 crystal Substances 0.000 claims 3
- 238000000034 method Methods 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 abstract 3
- 239000007789 gas Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 2
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
ST1으로 성장시켜서, ST2로 성형한 CZ 웨이퍼에 대하여 ST3에 있어서, 비산화 분위기로 1150℃ 이상, 30분 이상의 열처리를 한다(예 : 15% H2함유 Ar 가스중·1200℃·1시간), 이로써 디바이스 형성면으로부터의 깊이가 20㎛이상의 내부에서는 104개/㎠ 이상이고 그보다 얕은층에서는 0.1~103개/㎠의 BMD밀도 프로파일을 갖는 웨이퍼가 작성된다.
이 프로파일을 보는데는 다시 그 웨이퍼에 대하여 ST4로 산소 분위기·780℃·3시간의 열처리를 하고 그후, ST5로 산소분위기·1100℃·16 시간의 열처리를 한다. 이것으로써 BMD를 현미경으로 확인할 수 있다.
디바이스 형성면 부근의 사실상의 무결함화 및 내부의 충분한 게터 능력을 실현할 수 있다. 이로써 제품의 수율향상에 이바지할 수 있다.
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 일실시예에 관한 제조방법의 흐름을 나타내는 블록도.
제2도는 제1도에 도시한 제조방법에 의하여 작성되는 웨이퍼의 BMD 밀도 프로파일을 그래프(A) 및 확대 단면도(B)로 나타낸 설명도.
Claims (3)
- 반소 분위기 중에서 780℃에서 3시간의 열처리를 하고 이어서 산소 분위기 중에서 1100℃에서, 16시간의 열처리를 한 뒤에 BMD 관찰을 하였을 때의 디바이스 형성면으로부터 10㎛의 깊이까지의 BMD 밀도는 0.1~1000개/㎠인 것을 특징으로 하는 반도체 기판.
- 제1항에 있어서, 디바이스 형성면에서 20㎛ 이상의 깊이의 층에 있어서의 BMD 밀도는 104개/㎠ 이상인 것을 특징으로 하는 반도체 기판.
- 반도체 기판의 제조방법에 있어서, CZ법에 의하여 반도체 결정을 성장시키는 제1공정과; 상기 반도체 결정으로 이루어진 결정체를 기판 형상으로 성형하는 제2공정과; 그 기판 형상 성형체에 대하여 비산화 분위기 중에서 1150℃ 이상, 30분 이상의 열처리를 행하는 제3공정을 포함하는 것을 특징으로 하는 방법.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP93-033574 | 1993-02-23 | ||
JP3357493 | 1993-02-23 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR940020510A true KR940020510A (ko) | 1994-09-16 |
KR0139730B1 KR0139730B1 (ko) | 1998-06-01 |
Family
ID=12390311
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019940003032A KR0139730B1 (ko) | 1993-02-23 | 1994-02-21 | 반도체 기판 및 그 제조방법 |
Country Status (2)
Country | Link |
---|---|
US (1) | US5502331A (ko) |
KR (1) | KR0139730B1 (ko) |
Families Citing this family (38)
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US6331457B1 (en) * | 1997-01-24 | 2001-12-18 | Semiconductor Energy Laboratory., Ltd. Co. | Method for manufacturing a semiconductor thin film |
US5994761A (en) * | 1997-02-26 | 1999-11-30 | Memc Electronic Materials Spa | Ideal oxygen precipitating silicon wafers and oxygen out-diffusion-less process therefor |
MY137778A (en) * | 1997-04-09 | 2009-03-31 | Memc Electronic Materials | Low defect density, ideal oxygen precipitating silicon |
DE19742653A1 (de) * | 1997-09-26 | 1999-04-01 | Priesemuth W | Verfahren und Vorrichtung zum Herstellen einer Scheibe aus halbleitendem Material |
JP3955674B2 (ja) * | 1998-03-19 | 2007-08-08 | 株式会社東芝 | 半導体ウェーハの製造方法及び半導体装置の製造方法 |
US6828690B1 (en) * | 1998-08-05 | 2004-12-07 | Memc Electronic Materials, Inc. | Non-uniform minority carrier lifetime distributions in high performance silicon power devices |
WO2000012786A1 (fr) * | 1998-08-31 | 2000-03-09 | Shin-Etsu Handotai Co., Ltd. | Procede de production de plaquette de silicium monocristallin et plaquette de silicium monocristallin |
EP1114454A2 (en) | 1998-09-02 | 2001-07-11 | MEMC Electronic Materials, Inc. | Silicon on insulator structure from low defect density single crystal silicon |
CN1155064C (zh) * | 1998-09-02 | 2004-06-23 | Memc电子材料有限公司 | 制备理想析氧硅晶片的工艺 |
KR100816696B1 (ko) | 1998-09-02 | 2008-03-27 | 엠이엠씨 일렉트로닉 머티리얼즈 인코포레이티드 | 개선된 내부 게터링을 갖는 열어닐된 웨이퍼 |
US6336968B1 (en) | 1998-09-02 | 2002-01-08 | Memc Electronic Materials, Inc. | Non-oxygen precipitating czochralski silicon wafers |
DE69908965T2 (de) * | 1998-10-14 | 2004-05-13 | Memc Electronic Materials, Inc. | Wärmegetempertes einkristallines silizium mit niedriger fehlerdichte |
JP2000154070A (ja) * | 1998-11-16 | 2000-06-06 | Suminoe Textile Co Ltd | セラミックス三次元構造体及びその製造方法 |
US6284384B1 (en) | 1998-12-09 | 2001-09-04 | Memc Electronic Materials, Inc. | Epitaxial silicon wafer with intrinsic gettering |
US20030051656A1 (en) | 1999-06-14 | 2003-03-20 | Charles Chiun-Chieh Yang | Method for the preparation of an epitaxial silicon wafer with intrinsic gettering |
US6635587B1 (en) | 1999-09-23 | 2003-10-21 | Memc Electronic Materials, Inc. | Method for producing czochralski silicon free of agglomerated self-interstitial defects |
US6339016B1 (en) | 2000-06-30 | 2002-01-15 | Memc Electronic Materials, Inc. | Method and apparatus for forming an epitaxial silicon wafer with a denuded zone |
US6599815B1 (en) | 2000-06-30 | 2003-07-29 | Memc Electronic Materials, Inc. | Method and apparatus for forming a silicon wafer with a denuded zone |
KR20030021185A (ko) * | 2000-06-30 | 2003-03-12 | 엠이엠씨 일렉트로닉 머티리얼즈 인코포레이티드 | 디누디드 존을 갖는 실리콘 웨이퍼를 형성하는 방법 및 장치 |
JP4605876B2 (ja) * | 2000-09-20 | 2011-01-05 | 信越半導体株式会社 | シリコンウエーハおよびシリコンエピタキシャルウエーハの製造方法 |
JP4106862B2 (ja) * | 2000-10-25 | 2008-06-25 | 信越半導体株式会社 | シリコンウェーハの製造方法 |
US6897084B2 (en) * | 2001-04-11 | 2005-05-24 | Memc Electronic Materials, Inc. | Control of oxygen precipitate formation in high resistivity CZ silicon |
US20020179006A1 (en) * | 2001-04-20 | 2002-12-05 | Memc Electronic Materials, Inc. | Method for the preparation of a semiconductor substrate with a non-uniform distribution of stabilized oxygen precipitates |
JP2004006615A (ja) * | 2002-04-26 | 2004-01-08 | Sumitomo Mitsubishi Silicon Corp | 高抵抗シリコンウエーハ及びその製造方法 |
WO2004008521A1 (ja) * | 2002-07-17 | 2004-01-22 | Sumitomo Mitsubishi Silicon Corporation | 高抵抗シリコンウエーハ及びその製造方法 |
US6955718B2 (en) * | 2003-07-08 | 2005-10-18 | Memc Electronic Materials, Inc. | Process for preparing a stabilized ideal oxygen precipitating silicon wafer |
KR100531552B1 (ko) * | 2003-09-05 | 2005-11-28 | 주식회사 하이닉스반도체 | 실리콘 웨이퍼 및 그 제조방법 |
US20060009011A1 (en) * | 2004-07-06 | 2006-01-12 | Gary Barrett | Method for recycling/reclaiming a monitor wafer |
WO2006030699A1 (ja) * | 2004-09-13 | 2006-03-23 | Shin-Etsu Handotai Co., Ltd. | Soiウェーハの製造方法及びsoiウェーハ |
US7657390B2 (en) * | 2005-11-02 | 2010-02-02 | Applied Materials, Inc. | Reclaiming substrates having defects and contaminants |
US7485928B2 (en) * | 2005-11-09 | 2009-02-03 | Memc Electronic Materials, Inc. | Arsenic and phosphorus doped silicon wafer substrates having intrinsic gettering |
JP5072460B2 (ja) * | 2006-09-20 | 2012-11-14 | ジルトロニック アクチエンゲゼルシャフト | 半導体用シリコンウエハ、およびその製造方法 |
US20080135988A1 (en) * | 2006-12-07 | 2008-06-12 | Maxim Integrated Products, Inc. | Method to reduce semiconductor device leakage |
US20090004426A1 (en) * | 2007-06-29 | 2009-01-01 | Memc Electronic Materials, Inc. | Suppression of Oxygen Precipitation in Heavily Doped Single Crystal Silicon Substrates |
US20090004458A1 (en) * | 2007-06-29 | 2009-01-01 | Memc Electronic Materials, Inc. | Diffusion Control in Heavily Doped Substrates |
US8378384B2 (en) * | 2007-09-28 | 2013-02-19 | Infineon Technologies Ag | Wafer and method for producing a wafer |
CN107849728B (zh) * | 2015-07-27 | 2020-10-16 | 各星有限公司 | 使用双层连续Czochralsk法低氧晶体生长的系统和方法 |
US11695048B2 (en) * | 2020-04-09 | 2023-07-04 | Sumco Corporation | Silicon wafer and manufacturing method of the same |
Family Cites Families (7)
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JPS583375B2 (ja) * | 1979-01-19 | 1983-01-21 | 超エル・エス・アイ技術研究組合 | シリコン単結晶ウエハ−の製造方法 |
US4597804A (en) * | 1981-03-11 | 1986-07-01 | Fujitsu Limited | Methods of forming denuded zone in wafer by intrinsic gettering and forming bipolar transistor therein |
JPS59202640A (ja) * | 1983-05-02 | 1984-11-16 | Toshiba Corp | 半導体ウエハの処理方法 |
US4548654A (en) * | 1983-06-03 | 1985-10-22 | Motorola, Inc. | Surface denuding of silicon wafer |
DE3473971D1 (en) * | 1984-06-20 | 1988-10-13 | Ibm | Method of standardization and stabilization of semiconductor wafers |
US4622082A (en) * | 1984-06-25 | 1986-11-11 | Monsanto Company | Conditioned semiconductor substrates |
US5066359A (en) * | 1990-09-04 | 1991-11-19 | Motorola, Inc. | Method for producing semiconductor devices having bulk defects therein |
-
1994
- 1994-02-21 KR KR1019940003032A patent/KR0139730B1/ko not_active IP Right Cessation
-
1995
- 1995-05-19 US US08/444,892 patent/US5502331A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
US5502331A (en) | 1996-03-26 |
KR0139730B1 (ko) | 1998-06-01 |
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