KR940010301A - 전자부품 패키지용 3차원 접속방법 및 3차원 부품 - Google Patents

전자부품 패키지용 3차원 접속방법 및 3차원 부품 Download PDF

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KR940010301A
KR940010301A KR1019930020700A KR930020700A KR940010301A KR 940010301 A KR940010301 A KR 940010301A KR 1019930020700 A KR1019930020700 A KR 1019930020700A KR 930020700 A KR930020700 A KR 930020700A KR 940010301 A KR940010301 A KR 940010301A
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stack
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package
frame
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크리스챵 바르
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아르레뜨 다낭제
똥송-쎄 에스 에프
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
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    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

본 발명은 집직회로, 메모리등을 내장하는 반도체 침을 각각 인캡슐레이팅하고 있는 패키지를 적층하여 접속하는 방법에 관한 것이다.
접속핀(21)이 장착된 패키지(2)가 방열로로써 양호하게 작용하는 지지 그리드(4)상에 부착되어서 적층되며 수지코팅(5)에 의해 설로 연결된다. 스택을 절단하여 패키지와 그리드의 핀이 스택(3)의 표면(31,32)과 동일 평면상에 있도록 한다.
패키지 자체간의 접속과, 패키지와 스택 접속 패드간의 접속은 스택 표면에서 만들어진다. 접속패드는 필요한 경우에 접속핀이 장착된다.

Description

전자부품 패키지용 3차원 접속방법 및 3차원 부품
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명에 의한 방법의 실시예의 도면,
제2도는 본 발명에 의하여 디바이스내에 삽입하기에 적합한 패키지의 실예도면,
제3a도 내지 3d도는 본 발명에 의하여 디바이스의 제조상에 있는 한 단계의 변경예의 도면,
제4도는 본 발명에 의하여 다비이스의 제조상에 있는 후속단계의 도면,
제5도는 본 발명에 의하여 디바이스의 제조상에 있는 후속단계의 도면,
제6도는 본 발명에 의하여 디바이스 제조상에 있는 후속 단계의 도면.

Claims (13)

  1. 접속핀을 각각 가짐과 동시에 적어도 하나의 전자부품을 내장하는 패키지의 3차원 접속방법에 있어서, 그리드라 불리는 시트에 각각의 패키지를 부착하여 패키지를 지지하는 단계와, 그리드와 함께 패키지를 적층하는 단계와, 적층된 패키지 및 그리드를 전기 절연체로써 결합하는 단계와, 핀을 스택의 표면과 동일한 평면상에 있도록 하기 위하여 핀 수준에서 스택을 절단하는 단계와, 스택면에서 핀 간에 전기적 접속을 형성하는 단계를 구비하는 것을 특징으로 하는 3차원 접속 방법.
  2. 제1항에 있어서, 상기 결합단계는 적층된 패키지와 그리드를 절연체로 도포하는 보조단계를 구비하는 것을 특징으로 하는 특징으로 하는 3차원 접속 방법.
  3. 제1항에 있어서, 상기 절연체는 중합체 수지인 것을 특징으로 하는 3차원 접속 방법.
  4. 제1항에 있어서, 그리드는 적어도 하나의 텅에 의해 프레임에 연결된 중앙부를 구비하고 절단단계는 프레임을 제거하여 중앙부와 스택면이 동일 평면상에 있도록 그러한 방식으로 수행되고, 상기 그리드는 열전도체로 제조되는 것을 특징으로 하는 3차원 접속방법.
  5. 제1항에 있어서, 그리드는 적어도 하나의 텅에 의해 프레임에 연결된 중앙부를 구비하고, 절단단계는 프레임을 제거하여 상기 텅과 스택면이 동일평면상에 있도록 그러한 방식으로 수행되는 것을 특징으로 하는 3차원 접속 방법.
  6. 제4항에 있어서, 상기 프레임은 적층단계중에 패키지를 정렬하기 위한 위치설정 구멍을 구비하는 것을 특징으로 하는 3차원 접속 방법.
  7. 제4항에 있어서, 그리드는 프레임의 두 면을 함께 연결하는 적어도 하나의 귀환 접속을 구비하고, 상기 그리드는 전기 전도체로 제조되는 것을 특징으로 하는 3차원 접속 방법.
  8. 제1항에 있어서, 전기적 접속의 형성 단계는, 모든 스택면에 전도층을 증착하는 것으로 구성된 제1보조 단계와, 도체를 함께 연결하는 전기적 접속을 형성하기 위하여 전도층을 레이저 광선으로 인그레이빙하는 것으로 구성된 제2보조 단계를 구비하는 것을 특징으로 하는 3차원 접속 방법.
  9. 제1항에 있어서, 전기적 접속의 형성단계 중에 스택패드는 스택을 외부회로에 연결하기 위해 만들어지고, 상기 전기적 접속은 적어도 몇개의 핀과 스택 패드를 함께 연결하는 것을 특징으로 하는 3차원 접속 방법.
  10. 제1항에 있어서, 접속핀을 스택에 고정하는 단계를 더 구비하는 것을 특징으로 하는 3차원 접속 방법.
  11. 접속핀을 가짐과 동시에 적어도 하나의 전자 부품을 각각 내장하는 패키지를 포함하는 장치에 있어서, 상기 패키지는 각각 그리드에 연결되어서 다른 패키지의 상단에 차례대로 배열되고, 상기 장치는 적층된 패키지들을 도포하여 결합시키는 절연체를 더 포함하고, 상기 핀은 스택면과 동일 평면상에 있고 또한 핀 사이의 접속은 스택면에 의해 유지되는 것을 특징으로 하는 장치.
  12. 제11항에 있어서, 그리드 재료는 열전도성이 있고, 그리드는 스택면과 동일 평면상에 있으며 따라서 방열로를 형성하는 것을 특징으로 하는 장치.
  13. 제11항에 있어서, 그리드는 전기 전도체로 제조되고, 장치는 2개의 스택면을 함께 연결하는 적어도 하나의 귀환 접속을 더 구비하고, 상기 귀환 접속은 접속부를 경유하여 패키지핀에 연결되는 것을 특징으로 하는 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930020700A 1992-10-13 1993-10-07 전자부품 패키지용 3차원 접속방법 및 3차원 부품 KR940010301A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9212209 1992-10-13
FR9212209A FR2696871B1 (fr) 1992-10-13 1992-10-13 Procédé d'interconnexion 3D de boîtiers de composants électroniques, et composants 3D en résultant.

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KR940010301A true KR940010301A (ko) 1994-05-24

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US (1) US5526230A (ko)
EP (1) EP0593330B1 (ko)
JP (1) JP3483280B2 (ko)
KR (1) KR940010301A (ko)
DE (1) DE69322477T2 (ko)
FR (1) FR2696871B1 (ko)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2719967B1 (fr) * 1994-05-10 1996-06-07 Thomson Csf Interconnexion en trois dimensions de boîtiers de composants électroniques utilisant des circuits imprimés.
FR2773272B1 (fr) * 1997-12-30 2000-03-17 Thomson Csf Antenne reseau et procede de realisation
KR100333384B1 (ko) 1999-06-28 2002-04-18 박종섭 칩 사이즈 스택 패키지 및 그의 제조방법
KR100333385B1 (ko) 1999-06-29 2002-04-18 박종섭 웨이퍼 레벨 스택 패키지 및 그의 제조 방법
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FR2696871B1 (fr) 1994-11-18
EP0593330A1 (fr) 1994-04-20
JP3483280B2 (ja) 2004-01-06
EP0593330B1 (fr) 1998-12-09
FR2696871A1 (fr) 1994-04-15
DE69322477T2 (de) 1999-04-29
US5526230A (en) 1996-06-11
JPH077130A (ja) 1995-01-10
DE69322477D1 (de) 1999-01-21

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