KR940010174A - 적층판의 제조방법 - Google Patents

적층판의 제조방법 Download PDF

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Publication number
KR940010174A
KR940010174A KR1019930020687A KR930020687A KR940010174A KR 940010174 A KR940010174 A KR 940010174A KR 1019930020687 A KR1019930020687 A KR 1019930020687A KR 930020687 A KR930020687 A KR 930020687A KR 940010174 A KR940010174 A KR 940010174A
Authority
KR
South Korea
Prior art keywords
mold part
guide
predetermined pattern
mold
substrate
Prior art date
Application number
KR1019930020687A
Other languages
English (en)
Other versions
KR970006526B1 (ko
Inventor
고우지 아라키
Original Assignee
사토 후미오
가부시키가이샤 도시바
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 사토 후미오, 가부시키가이샤 도시바 filed Critical 사토 후미오
Publication of KR940010174A publication Critical patent/KR940010174A/ko
Application granted granted Critical
Publication of KR970006526B1 publication Critical patent/KR970006526B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/20—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern
    • H05K3/202—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by affixing prefabricated conductor pattern using self-supporting metal foil pattern

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Laminated Bodies (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

본 발명은 세라믹기재상에 패턴을 정밀도가 좋게 배치하고, 동장적층판을 단시간이면서 낮은 비용으로 제조하기 위한 것이다.
본 발명은 도전성부재를 에칭가공 또는 프레스가공함으로써 틀부(23)와, 이 틀부(23)내에 형성되면서 상기 틀부(23)에 지지되는 소정의 패턴(22)을 일체로 형성하고, 그 후 상기 틀부(23)를 가이드로 하여 기재(21)의 일주면에 상기 소정의 패턴(22)을 고온가열에 의해 접합하며, 다시 그 후 상기 틀부(23)를 잘라 버리는 것을 특징으로 한다.

Description

적층판의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 1실시예에 따른 적층판의 제조방법을 나타낸 도면,
제2도는 기판에 패턴을 형성한 후에 불필요한 틀을 제거하는 방법을 나타낸 도면.

Claims (1)

  1. 도전성부재를 에칭가공 또는 프레스가공함으로써 틀부와, 이 틀부내에 형성되면서 상기 틀부에 지지되는 소정의 패턴을 일체로 형성하고, 그 후 상기 틀부를 가이드로 하여 기재의 일주면에 상기 소정의 패턴을 고온가열에 의해 접합하며, 다시 그 후 상기 틀부를 잘라 버리는 것을 특징으로 하는 적층판의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930020687A 1992-10-08 1993-10-07 적층판의 제조방법 KR970006526B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP92-270174 1992-10-08
JP4270174A JPH06120370A (ja) 1992-10-08 1992-10-08 積層板の製造方法

Publications (2)

Publication Number Publication Date
KR940010174A true KR940010174A (ko) 1994-05-24
KR970006526B1 KR970006526B1 (ko) 1997-04-29

Family

ID=17482560

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930020687A KR970006526B1 (ko) 1992-10-08 1993-10-07 적층판의 제조방법

Country Status (3)

Country Link
US (1) US5338392A (ko)
JP (1) JPH06120370A (ko)
KR (1) KR970006526B1 (ko)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7842013B2 (en) * 2004-01-23 2010-11-30 Genico, Inc. Trocar and cannula assembly having conical valve and related methods
US8454563B2 (en) 2009-10-09 2013-06-04 Rogelio A. Insignares Trocar and cannula assembly having improved conical valve, and methods related thereto
EP4294135A1 (de) * 2022-06-14 2023-12-20 CeramTec GmbH Metallische struktur als vorprodukt für elektrische schaltungen und verfahren zur herstellung einer elektrischen schaltung

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3993411A (en) * 1973-06-01 1976-11-23 General Electric Company Bonds between metal and a non-metallic substrate
JPS50109470A (ko) * 1974-02-06 1975-08-28
JPS59220956A (ja) * 1983-05-31 1984-12-12 Matsushita Electric Works Ltd 電子部品の実装構造
JPS629657A (ja) * 1985-07-08 1987-01-17 Daido Steel Co Ltd リ−ドフレ−ム用合金帯母材
US5062916A (en) * 1990-08-01 1991-11-05 W. H. Brady Co. Method for the manufacture of electrical membrane panels having circuits on flexible plastic films
US5240551A (en) * 1990-10-05 1993-08-31 Kabushiki Kaisha Toshiba Method of manufacturing ceramic circuit board

Also Published As

Publication number Publication date
KR970006526B1 (ko) 1997-04-29
JPH06120370A (ja) 1994-04-28
US5338392A (en) 1994-08-16

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