KR940002970A - 상호연결 간격을 공백이 없는 산화막으로 채우는 공정 및 그 방법 - Google Patents

상호연결 간격을 공백이 없는 산화막으로 채우는 공정 및 그 방법 Download PDF

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Publication number
KR940002970A
KR940002970A KR1019930012440A KR930012440A KR940002970A KR 940002970 A KR940002970 A KR 940002970A KR 1019930012440 A KR1019930012440 A KR 1019930012440A KR 930012440 A KR930012440 A KR 930012440A KR 940002970 A KR940002970 A KR 940002970A
Authority
KR
South Korea
Prior art keywords
oxide
layer
interconnect
integrated circuit
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
KR1019930012440A
Other languages
English (en)
Korean (ko)
Inventor
술탄 퍼베이즈
씨. 아반지노 스티븐
Original Assignee
미키오 이시마루
어드밴스드 마이크로 디바이시즈, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 미키오 이시마루, 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 미키오 이시마루
Publication of KR940002970A publication Critical patent/KR940002970A/ko
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/098—Manufacture or treatment of dielectric parts thereof by filling between adjacent conductive parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
KR1019930012440A 1992-07-31 1993-07-02 상호연결 간격을 공백이 없는 산화막으로 채우는 공정 및 그 방법 Withdrawn KR940002970A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/922,897 US5382547A (en) 1992-07-31 1992-07-31 Void free oxide fill for interconnect spaces
US7/922,897 1992-07-31

Publications (1)

Publication Number Publication Date
KR940002970A true KR940002970A (ko) 1994-02-19

Family

ID=25447737

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019930012440A Withdrawn KR940002970A (ko) 1992-07-31 1993-07-02 상호연결 간격을 공백이 없는 산화막으로 채우는 공정 및 그 방법

Country Status (5)

Country Link
US (1) US5382547A (enExample)
EP (1) EP0583866A1 (enExample)
JP (1) JPH0697302A (enExample)
KR (1) KR940002970A (enExample)
TW (1) TW228607B (enExample)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5567660A (en) * 1995-09-13 1996-10-22 Taiwan Semiconductor Manufacturing Company Ltd Spin-on-glass planarization by a new stagnant coating method
US5665657A (en) * 1995-09-18 1997-09-09 Taiwan Semiconductor Manufacturing Company, Ltd Spin-on-glass partial etchback planarization process
US5840623A (en) * 1995-10-04 1998-11-24 Advanced Micro Devices, Inc. Efficient and economical method of planarization of multilevel metallization structures in integrated circuits using CMP
US5665644A (en) * 1995-11-03 1997-09-09 Micron Technology, Inc. Semiconductor processing method of forming electrically conductive interconnect lines and integrated circuitry
US5789314A (en) * 1995-12-05 1998-08-04 Integrated Device Technology, Inc. Method of topside and inter-metal oxide coating
US5827782A (en) * 1996-06-03 1998-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple etch method for optimizing Inter-Metal Dielectric (IMD) spacer layer profile
US5783481A (en) * 1996-06-05 1998-07-21 Advanced Micro Devices, Inc. Semiconductor interlevel dielectric having a polymide for producing air gaps
US6576976B2 (en) 1997-01-03 2003-06-10 Integrated Device Technology, Inc. Semiconductor integrated circuit with an insulation structure having reduced permittivity
US5926716A (en) * 1997-03-31 1999-07-20 Siemens Aktiengesellschaft Method for forming a structure
US5920791A (en) * 1997-11-06 1999-07-06 Vanguard International Semiconductor Corporation Method of manufacturing intermetal dielectrics for sub-half-micron semiconductor devices
KR100481981B1 (ko) * 1997-12-29 2005-06-17 매그나칩 반도체 유한회사 반도체소자의층간절연막형성방법
US6023327A (en) * 1998-08-10 2000-02-08 Advanced Micro Devices, Inc. System and method for detecting defects in an interlayer dielectric of a semiconductor device
US6177802B1 (en) 1998-08-10 2001-01-23 Advanced Micro Devices, Inc. System and method for detecting defects in an interlayer dielectric of a semiconductor device using the hall-effect
US6384466B1 (en) * 1998-08-27 2002-05-07 Micron Technology, Inc. Multi-layer dielectric and method of forming same
JP4236805B2 (ja) 2000-10-18 2009-03-11 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
US7163881B1 (en) 2004-06-08 2007-01-16 Integrated Device Technology, Inc. Method for forming CMOS structure with void-free dielectric film
US7918383B2 (en) * 2004-09-01 2011-04-05 Micron Technology, Inc. Methods for placing substrates in contact with molten solder
JP2006310454A (ja) * 2005-04-27 2006-11-09 Toshiba Corp 半導体装置およびその製造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4481070A (en) * 1984-04-04 1984-11-06 Advanced Micro Devices, Inc. Double planarization process for multilayer metallization of integrated circuit structures
US4986878A (en) * 1988-07-19 1991-01-22 Cypress Semiconductor Corp. Process for improved planarization of the passivation layers for semiconductor devices
JPH0277140A (ja) * 1988-09-13 1990-03-16 Nec Corp 集積回路の製造方法
JPH0279437A (ja) * 1988-09-14 1990-03-20 Mitsubishi Electric Corp 半導体装置の製造方法
US5204288A (en) * 1988-11-10 1993-04-20 Applied Materials, Inc. Method for planarizing an integrated circuit structure using low melting inorganic material
EP0423907B1 (en) * 1988-11-10 1996-04-24 Applied Materials, Inc. Method for planarizing an integrated circuit structure
US5192715A (en) * 1989-07-25 1993-03-09 Advanced Micro Devices, Inc. Process for avoiding spin-on-glass cracking in high aspect ratio cavities
US5119164A (en) * 1989-07-25 1992-06-02 Advanced Micro Devices, Inc. Avoiding spin-on-glass cracking in high aspect ratio cavities
US5101142A (en) * 1990-09-05 1992-03-31 Applied Lumens, Ltd. Solid-state ballast for fluorescent lamp with multiple dimming

Also Published As

Publication number Publication date
TW228607B (enExample) 1994-08-21
EP0583866A1 (en) 1994-02-23
JPH0697302A (ja) 1994-04-08
US5382547A (en) 1995-01-17

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St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

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St.27 status event code: A-3-3-R10-R18-oth-X000

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