TW228607B - - Google Patents

Info

Publication number
TW228607B
TW228607B TW081109685A TW81109685A TW228607B TW 228607 B TW228607 B TW 228607B TW 081109685 A TW081109685 A TW 081109685A TW 81109685 A TW81109685 A TW 81109685A TW 228607 B TW228607 B TW 228607B
Authority
TW
Taiwan
Application number
TW081109685A
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of TW228607B publication Critical patent/TW228607B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
TW081109685A 1992-07-31 1992-12-03 TW228607B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/922,897 US5382547A (en) 1992-07-31 1992-07-31 Void free oxide fill for interconnect spaces

Publications (1)

Publication Number Publication Date
TW228607B true TW228607B (zh) 1994-08-21

Family

ID=25447737

Family Applications (1)

Application Number Title Priority Date Filing Date
TW081109685A TW228607B (zh) 1992-07-31 1992-12-03

Country Status (5)

Country Link
US (1) US5382547A (zh)
EP (1) EP0583866A1 (zh)
JP (1) JPH0697302A (zh)
KR (1) KR940002970A (zh)
TW (1) TW228607B (zh)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5567660A (en) * 1995-09-13 1996-10-22 Taiwan Semiconductor Manufacturing Company Ltd Spin-on-glass planarization by a new stagnant coating method
US5665657A (en) * 1995-09-18 1997-09-09 Taiwan Semiconductor Manufacturing Company, Ltd Spin-on-glass partial etchback planarization process
US5840623A (en) * 1995-10-04 1998-11-24 Advanced Micro Devices, Inc. Efficient and economical method of planarization of multilevel metallization structures in integrated circuits using CMP
US5665644A (en) * 1995-11-03 1997-09-09 Micron Technology, Inc. Semiconductor processing method of forming electrically conductive interconnect lines and integrated circuitry
US5789314A (en) * 1995-12-05 1998-08-04 Integrated Device Technology, Inc. Method of topside and inter-metal oxide coating
US5827782A (en) * 1996-06-03 1998-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple etch method for optimizing Inter-Metal Dielectric (IMD) spacer layer profile
US5783481A (en) * 1996-06-05 1998-07-21 Advanced Micro Devices, Inc. Semiconductor interlevel dielectric having a polymide for producing air gaps
US6576976B2 (en) 1997-01-03 2003-06-10 Integrated Device Technology, Inc. Semiconductor integrated circuit with an insulation structure having reduced permittivity
US5926716A (en) * 1997-03-31 1999-07-20 Siemens Aktiengesellschaft Method for forming a structure
US5920791A (en) * 1997-11-06 1999-07-06 Vanguard International Semiconductor Corporation Method of manufacturing intermetal dielectrics for sub-half-micron semiconductor devices
KR100481981B1 (ko) * 1997-12-29 2005-06-17 매그나칩 반도체 유한회사 반도체소자의층간절연막형성방법
US6177802B1 (en) 1998-08-10 2001-01-23 Advanced Micro Devices, Inc. System and method for detecting defects in an interlayer dielectric of a semiconductor device using the hall-effect
US6023327A (en) * 1998-08-10 2000-02-08 Advanced Micro Devices, Inc. System and method for detecting defects in an interlayer dielectric of a semiconductor device
US6384466B1 (en) * 1998-08-27 2002-05-07 Micron Technology, Inc. Multi-layer dielectric and method of forming same
JP4236805B2 (ja) 2000-10-18 2009-03-11 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
US7163881B1 (en) 2004-06-08 2007-01-16 Integrated Device Technology, Inc. Method for forming CMOS structure with void-free dielectric film
US7918383B2 (en) * 2004-09-01 2011-04-05 Micron Technology, Inc. Methods for placing substrates in contact with molten solder
JP2006310454A (ja) * 2005-04-27 2006-11-09 Toshiba Corp 半導体装置およびその製造方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4481070A (en) * 1984-04-04 1984-11-06 Advanced Micro Devices, Inc. Double planarization process for multilayer metallization of integrated circuit structures
US4986878A (en) * 1988-07-19 1991-01-22 Cypress Semiconductor Corp. Process for improved planarization of the passivation layers for semiconductor devices
JPH0277140A (ja) * 1988-09-13 1990-03-16 Nec Corp 集積回路の製造方法
JPH0279437A (ja) * 1988-09-14 1990-03-20 Mitsubishi Electric Corp 半導体装置の製造方法
EP0423907B1 (en) * 1988-11-10 1996-04-24 Applied Materials, Inc. Method for planarizing an integrated circuit structure
US5204288A (en) * 1988-11-10 1993-04-20 Applied Materials, Inc. Method for planarizing an integrated circuit structure using low melting inorganic material
US5192715A (en) * 1989-07-25 1993-03-09 Advanced Micro Devices, Inc. Process for avoiding spin-on-glass cracking in high aspect ratio cavities
US5119164A (en) * 1989-07-25 1992-06-02 Advanced Micro Devices, Inc. Avoiding spin-on-glass cracking in high aspect ratio cavities
US5101142A (en) * 1990-09-05 1992-03-31 Applied Lumens, Ltd. Solid-state ballast for fluorescent lamp with multiple dimming

Also Published As

Publication number Publication date
EP0583866A1 (en) 1994-02-23
JPH0697302A (ja) 1994-04-08
KR940002970A (ko) 1994-02-19
US5382547A (en) 1995-01-17

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