KR940002031A - 칩 캐리어 - Google Patents

칩 캐리어 Download PDF

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KR940002031A
KR940002031A KR1019930011870A KR930011870A KR940002031A KR 940002031 A KR940002031 A KR 940002031A KR 1019930011870 A KR1019930011870 A KR 1019930011870A KR 930011870 A KR930011870 A KR 930011870A KR 940002031 A KR940002031 A KR 940002031A
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chip carrier
sealant
composition
chip
encapsulant
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KR1019930011870A
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KR960015924B1 (ko
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다이안 프레이 브렌다
아놀드 조셉 찰스
죤 올셰프스키 프란시스
워렌 윌슨 제임스
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죤 디. 크레인
인터내셔널 비지네스 머신즈 코포레이션
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Publication of KR940002031A publication Critical patent/KR940002031A/ko
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Publication of KR960015924B1 publication Critical patent/KR960015924B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3135—Double encapsulation or coating and encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
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    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
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    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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    • H01L2224/732—Location after the connecting process
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  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
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  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Epoxy Resins (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Paints Or Removers (AREA)
  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)
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Abstract

본 발명은 칩 캐리어 기판과, 땜납 덩어리를 거쳐서 이 기판의 표면상에 플립 칩 구조로 고정된 적어도 하나의 반도체 칩을 구비하는 칩 캐리어를 개시한다. 이 땜납 덩어리는 에폭시 함유 조성물을 갖는 제1밀봉재내에 밀봉된다. 또한, 회로 표면상의 회로중 적어도 일부분은 우레탄 함유 조성물을 갖는 제2 밀봉재내에 밀봉되며, 그 조성물은 제2밀봉재가 약 10,000psi 이하의 탄성율을 나타내도록 선택된다. 결과적으로, 제2밀봉재는 칩 캐리어와의 반복가열시험 후 내부의 균열도 나타내지 않고 제1밀봉재와의 접촉면 영역에도 균열을 나타내지 않으며, 회로 배치표면으로부터 제2밀봉재의 박리도 나타내지 않는다.

Description

칩 캐리어
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
도면은 회로 배치 표면(circuitized surface)중 적어도 일부를 덮는 보호용 피막(protective coating)을 구비하는 본 발명에 따른 칩 캐리어(chip carrier)의 바람직한 실시예에 대한 단면도.

Claims (6)

  1. 전기회로가 형성된 표면을 갖는 기판과; 에폭시 함유 조성물을 갖는 제1밀봉재에 의해서 부분적으로 밀봉된 전기전도성 땜납 덩어리를 경유해서 상기 표면상에 고정되는 것으로서, 상기 제1밀봉재의 열팽창계수가 상기 땜납 덩어리의 열팽창계수의 30% 이내로 된 적어도 하나의 반도체 칩과; 상기 기판 표면상에 형성된 상기 전기회로의 적어도 일부분을 덮어서 밀봉하며 상기 제1밀봉재의 적어도 일부분과 접촉하여 부분적으로 둘러싸는 제2밀봉재를 포함하는 칩 캐리어(chip carrier)에 있어서, 상기 제2밀봉재는 우레탄 함유조성물을 가지며, 상기 조성물은 상기 제2밀봉재가 25℃에서 약 10,000psi 이하의 탄성율을 나타낼 수 있도록 선택하는 것을 특징으로 하는 칩 캐리어.
  2. 제1항에 있어서, 상기 제2밀봉재의 조성물은, 상기 칩 캐리어에 매시간당 3사이클의 주기로 약 2,000사이클 동안 0℃로부터 100℃까지의 반복가열을 행한 후 10x 광학 현미경으로 관찰하였을때 내부균열도 나타나지 않고 접촉면의 균열도 없는 것으로 선택한 칩 캐리어.
  3. 제1항에 있어서, 상기 제2밀봉재의 조성물은, 상기 칩 캐리어에 매시간당 1사이클의 주기로 －40℃로부터 ＋65℃로의 가열시험을 10회 반복한 후 10x 광학 현미경으로 검사하였을때 상기 기판으로부터 박리현상도 없고 균열도 나타내지 않도록 선택한 칩 캐리어.
  4. 제1항에 있어서, 상기 제2밀봉재는 적어도 하나의 상기 반도체 칩의 상측 노출 표면중 적어도 일부분을 덮어서 밀봉하는 칩 캐리어.
  5. 제1항에 있어서, 상기 제2밀봉재는 자외선 경화된 밀봉재인 칩 캐리어.
  6. 제1항에 있어서, 상기 적어도 하나의 반도체 칩의 상측 노출표면에 직접 부착된 히트싱크(heat sink)를 추가로 포함하는 칩 캐리어.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019930011870A 1992-07-06 1993-06-28 칩 캐리어 KR960015924B1 (ko)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP92-196072 1992-06-29
US07/909,368 US5249101A (en) 1992-07-06 1992-07-06 Chip carrier with protective coating for circuitized surface
JP909,368 1992-07-06
US909,368 1992-07-06

Publications (2)

Publication Number Publication Date
KR940002031A true KR940002031A (ko) 1994-02-16
KR960015924B1 KR960015924B1 (ko) 1996-11-23

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US (1) US5249101A (ko)
EP (1) EP0578307B1 (ko)
JP (1) JP2501287B2 (ko)
KR (1) KR960015924B1 (ko)
CN (1) CN1028937C (ko)
AT (1) ATE143529T1 (ko)
CA (1) CA2091910C (ko)
DE (1) DE69305012T2 (ko)
ES (1) ES2092216T3 (ko)
MY (1) MY108750A (ko)
SG (1) SG44362A1 (ko)
TW (1) TW230272B (ko)

Families Citing this family (67)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04291948A (ja) * 1991-03-20 1992-10-16 Fujitsu Ltd 半導体装置及びその製造方法及び放熱フィン
JPH0538479U (ja) * 1991-10-25 1993-05-25 曙ブレーキ工業株式会社 ブレーキ制御機構の電磁弁装置
US5288944A (en) * 1992-02-18 1994-02-22 International Business Machines, Inc. Pinned ceramic chip carrier
US5390082A (en) * 1992-07-06 1995-02-14 International Business Machines, Corp. Chip carrier with protective coating for circuitized surface
KR100280762B1 (ko) * 1992-11-03 2001-03-02 비센트 비.인그라시아 노출 후부를 갖는 열적 강화된 반도체 장치 및 그 제조방법
US5403783A (en) * 1992-12-28 1995-04-04 Hitachi, Ltd. Integrated circuit substrate with cooling accelerator substrate
US5379187A (en) * 1993-03-25 1995-01-03 Vlsi Technology, Inc. Design for encapsulation of thermally enhanced integrated circuits
US5539545A (en) * 1993-05-18 1996-07-23 Semiconductor Energy Laboratory Co., Ltd. Method of making LCD in which resin columns are cured and the liquid crystal is reoriented
JPH0722722A (ja) * 1993-07-05 1995-01-24 Mitsubishi Electric Corp 樹脂成形タイプの電子回路装置
US5410806A (en) * 1993-09-15 1995-05-02 Lsi Logic Corporation Method for fabricating conductive epoxy grid array semiconductors packages
US5506756A (en) * 1994-01-25 1996-04-09 Intel Corporation Tape BGA package die-up/die down
US5776796A (en) * 1994-05-19 1998-07-07 Tessera, Inc. Method of encapsulating a semiconductor package
US6359335B1 (en) 1994-05-19 2002-03-19 Tessera, Inc. Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures
US6232152B1 (en) 1994-05-19 2001-05-15 Tessera, Inc. Method of manufacturing a plurality of semiconductor packages and the resulting semiconductor package structures
US5834339A (en) 1996-03-07 1998-11-10 Tessera, Inc. Methods for providing void-free layers for semiconductor assemblies
US5688716A (en) * 1994-07-07 1997-11-18 Tessera, Inc. Fan-out semiconductor chip assembly
US5706174A (en) * 1994-07-07 1998-01-06 Tessera, Inc. Compliant microelectrionic mounting device
MY112145A (en) * 1994-07-11 2001-04-30 Ibm Direct attachment of heat sink attached directly to flip chip using flexible epoxy
JPH0846098A (ja) * 1994-07-22 1996-02-16 Internatl Business Mach Corp <Ibm> 直接的熱伝導路を形成する装置および方法
US6169328B1 (en) 1994-09-20 2001-01-02 Tessera, Inc Semiconductor chip assembly
US5659952A (en) 1994-09-20 1997-08-26 Tessera, Inc. Method of fabricating compliant interface for semiconductor chip
US5915170A (en) * 1994-09-20 1999-06-22 Tessera, Inc. Multiple part compliant interface for packaging of a semiconductor chip and method therefor
US6870272B2 (en) 1994-09-20 2005-03-22 Tessera, Inc. Methods of making microelectronic assemblies including compliant interfaces
US5604978A (en) * 1994-12-05 1997-02-25 International Business Machines Corporation Method for cooling of chips using a plurality of materials
US5757620A (en) * 1994-12-05 1998-05-26 International Business Machines Corporation Apparatus for cooling of chips using blind holes with customized depth
US6046076A (en) * 1994-12-29 2000-04-04 Tessera, Inc. Vacuum dispense method for dispensing an encapsulant and machine therefor
GB9502178D0 (en) * 1995-02-03 1995-03-22 Plessey Semiconductors Ltd MCM-D Assemblies
US5798909A (en) * 1995-02-15 1998-08-25 International Business Machines Corporation Single-tiered organic chip carriers for wire bond-type chips
US6211572B1 (en) * 1995-10-31 2001-04-03 Tessera, Inc. Semiconductor chip package with fan-in leads
US6284563B1 (en) * 1995-10-31 2001-09-04 Tessera, Inc. Method of making compliant microelectronic assemblies
US5744383A (en) * 1995-11-17 1998-04-28 Altera Corporation Integrated circuit package fabrication method
EP0865082A4 (en) * 1995-11-28 1999-10-13 Hitachi Ltd SEMICONDUCTOR DEVICE, PROCESS FOR PRODUCING THE SAME, AND ENCAPSULATED SUBSTRATE
US6007349A (en) * 1996-01-04 1999-12-28 Tessera, Inc. Flexible contact post and post socket and associated methods therefor
US5977629A (en) * 1996-01-24 1999-11-02 Micron Technology, Inc. Condensed memory matrix
JP3527350B2 (ja) * 1996-02-01 2004-05-17 株式会社ルネサステクノロジ 半導体装置
US5851311A (en) * 1996-03-29 1998-12-22 Sophia Systems Co., Ltd. Polymerizable flux composition for encapsulating the solder in situ
US5700723A (en) * 1996-05-15 1997-12-23 Lsi Logic Corporation Method of packaging an integrated circuit
US5895976A (en) * 1996-06-03 1999-04-20 Motorola Corporation Microelectronic assembly including polymeric reinforcement on an integrated circuit die, and method for forming same
US6686015B2 (en) 1996-12-13 2004-02-03 Tessera, Inc. Transferable resilient element for packaging of a semiconductor chip and method therefor
US5891753A (en) 1997-01-24 1999-04-06 Micron Technology, Inc. Method and apparatus for packaging flip chip bare die on printed circuit boards
US5798563A (en) 1997-01-28 1998-08-25 International Business Machines Corporation Polytetrafluoroethylene thin film chip carrier
US6639155B1 (en) 1997-06-11 2003-10-28 International Business Machines Corporation High performance packaging platform and method of making same
US6403882B1 (en) * 1997-06-30 2002-06-11 International Business Machines Corporation Protective cover plate for flip chip assembly backside
US6495083B2 (en) 1997-10-29 2002-12-17 Hestia Technologies, Inc. Method of underfilling an integrated circuit chip
US6038136A (en) * 1997-10-29 2000-03-14 Hestia Technologies, Inc. Chip package with molded underfill
US6324069B1 (en) 1997-10-29 2001-11-27 Hestia Technologies, Inc. Chip package with molded underfill
US5969947A (en) 1997-12-17 1999-10-19 International Business Machines Corporation Integral design features for heatsink attach for electronic packages
JP3017485B2 (ja) * 1998-01-23 2000-03-06 アピックヤマダ株式会社 半導体装置の樹脂封止方法及び樹脂封止装置
US6224711B1 (en) 1998-08-25 2001-05-01 International Business Machines Corporation Assembly process for flip chip package having a low stress chip and resulting structure
US6117797A (en) * 1998-09-03 2000-09-12 Micron Technology, Inc. Attachment method for heat sinks and devices involving removal of misplaced encapsulant
US6008074A (en) 1998-10-01 1999-12-28 Micron Technology, Inc. Method of forming a synchronous-link dynamic random access memory edge-mounted device
US6214640B1 (en) 1999-02-10 2001-04-10 Tessera, Inc. Method of manufacturing a plurality of semiconductor packages
US20020014688A1 (en) * 1999-03-03 2002-02-07 Suresh Ramalingam Controlled collapse chip connection (c4) integrated circuit package which has two dissimilar underfill materials
US6507101B1 (en) * 1999-03-26 2003-01-14 Hewlett-Packard Company Lossy RF shield for integrated circuits
US6077766A (en) * 1999-06-25 2000-06-20 International Business Machines Corporation Variable thickness pads on a substrate surface
MY140714A (en) * 1999-07-08 2010-01-15 Sunstar Engineering Inc Underfilling material for semiconductor package
US6426545B1 (en) * 2000-02-10 2002-07-30 Epic Technologies, Inc. Integrated circuit structures and methods employing a low modulus high elongation photodielectric
US6570259B2 (en) 2001-03-22 2003-05-27 International Business Machines Corporation Apparatus to reduce thermal fatigue stress on flip chip solder connections
US6974765B2 (en) * 2001-09-27 2005-12-13 Intel Corporation Encapsulation of pin solder for maintaining accuracy in pin position
US20040222518A1 (en) * 2003-02-25 2004-11-11 Tessera, Inc. Ball grid array with bumps
US7999379B2 (en) * 2005-02-25 2011-08-16 Tessera, Inc. Microelectronic assemblies having compliancy
DE102005029407B4 (de) * 2005-06-24 2008-06-19 Mühlbauer Ag Verfahren und Vorrichtung zum dauerhaften Verbinden integrierter Schaltungen mit einem Substrat
US7749886B2 (en) 2006-12-20 2010-07-06 Tessera, Inc. Microelectronic assemblies having compliancy and methods therefor
US8710618B2 (en) 2007-03-12 2014-04-29 Honeywell International Inc. Fibrous laminate interface for security coatings
TW201025467A (en) * 2008-12-25 2010-07-01 United Test Ct Inc Ball implantation method and ball implantation system applying the method
JP6386746B2 (ja) * 2014-02-26 2018-09-05 株式会社ジェイデバイス 半導体装置
JP7358857B2 (ja) * 2019-09-04 2023-10-11 富士通株式会社 電子ユニット、電子ユニットの製造方法及び電子機器

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0088050B1 (de) * 1982-02-26 1986-09-03 Ciba-Geigy Ag Photohärtbare gefärbte Massen
US4633573A (en) * 1982-10-12 1987-01-06 Aegis, Inc. Microcircuit package and sealing method
JPS6032807A (ja) * 1983-07-30 1985-02-20 Matsushita Electric Works Ltd 光硬化型樹脂組成物
EP0138754B1 (de) * 1983-08-15 1988-05-25 Ciba-Geigy Ag Photohärtbare Gemische
DE3442131A1 (de) * 1984-11-17 1986-05-22 Messerschmitt-Bölkow-Blohm GmbH, 8012 Ottobrunn Verfahren zum einkapseln von mikroelektronischen halbleiter- und schichtschaltungen
US4806574A (en) * 1985-07-22 1989-02-21 Desoto, Inc. Ultraviolet curable coatings for optical glass fiber based on a polyfunctional core
JP2568421B2 (ja) * 1987-03-24 1997-01-08 株式会社スリーボンド 嫌気硬化性接着シール剤組成物
US5039715A (en) * 1987-04-13 1991-08-13 Dymax Corporation Photocurable acrylate adhesive containing perester/tautomeric acid adhesion promoter
DE3881382T2 (de) * 1988-03-29 1994-01-20 Agency Ind Science Techn Halbleiterchip, verbunden mit einem Substrat.
US4973611A (en) * 1988-04-04 1990-11-27 Uvexs Incorporated Optical fiber buffer coating with Tg
EP0340492A3 (en) * 1988-05-02 1990-07-04 International Business Machines Corporation Conformal sealing and interplanar encapsulation of electronic device structures
US4915167A (en) * 1988-08-05 1990-04-10 Westinghouse Electric Corp. Thermal coupling to enhance heat transfer
JPH0269945A (ja) * 1988-09-05 1990-03-08 Hitachi Ltd 半導体装置及びその製造方法
US5053357A (en) * 1989-12-27 1991-10-01 Motorola, Inc. Method of aligning and mounting an electronic device on a printed circuit board using a flexible substrate having fixed lead arrays thereon
US5089440A (en) * 1990-03-14 1992-02-18 International Business Machines Corporation Solder interconnection structure and process for making
US4999699A (en) * 1990-03-14 1991-03-12 International Business Machines Corporation Solder interconnection structure and process for making
US5121190A (en) * 1990-03-14 1992-06-09 International Business Machines Corp. Solder interconnection structure on organic substrates
JP2843658B2 (ja) * 1990-08-02 1999-01-06 東レ・ダウコーニング・シリコーン株式会社 フリップチップ型半導体装置
US5128746A (en) * 1990-09-27 1992-07-07 Motorola, Inc. Adhesive and encapsulant material with fluxing properties
US5120678A (en) * 1990-11-05 1992-06-09 Motorola Inc. Electrical component package comprising polymer-reinforced solder bump interconnection
US5173764A (en) * 1991-04-08 1992-12-22 Motorola, Inc. Semiconductor device having a particular lid means and encapsulant to reduce die stress

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KR960015924B1 (ko) 1996-11-23
EP0578307A2 (en) 1994-01-12
MY108750A (en) 1996-11-30
CA2091910C (en) 1996-07-30
JPH0697309A (ja) 1994-04-08
CN1081787A (zh) 1994-02-09
SG44362A1 (en) 1997-12-19
ES2092216T3 (es) 1996-11-16
EP0578307B1 (en) 1996-09-25
DE69305012D1 (de) 1996-10-31
JP2501287B2 (ja) 1996-05-29
ATE143529T1 (de) 1996-10-15
US5249101A (en) 1993-09-28
TW230272B (ko) 1994-09-11
EP0578307A3 (en) 1994-08-24
CA2091910A1 (en) 1994-01-07
CN1028937C (zh) 1995-06-14
DE69305012T2 (de) 1997-04-03

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