CN1081787A - 具有电路化表面和保持涂层的晶片载体 - Google Patents
具有电路化表面和保持涂层的晶片载体 Download PDFInfo
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- CN1081787A CN1081787A CN93108062A CN93108062A CN1081787A CN 1081787 A CN1081787 A CN 1081787A CN 93108062 A CN93108062 A CN 93108062A CN 93108062 A CN93108062 A CN 93108062A CN 1081787 A CN1081787 A CN 1081787A
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- 238000000576 coating method Methods 0.000 title description 56
- 239000011248 coating agent Substances 0.000 title description 52
- 238000012423 maintenance Methods 0.000 title description 2
- 239000000565 sealant Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 239000004065 semiconductor Substances 0.000 claims abstract description 10
- 229920000647 polyepoxide Polymers 0.000 claims abstract description 7
- 239000003822 epoxy resin Substances 0.000 claims abstract description 6
- 208000037656 Respiratory Sounds Diseases 0.000 claims description 13
- 239000000203 mixture Substances 0.000 claims description 11
- 230000004087 circulation Effects 0.000 claims description 9
- 238000007789 sealing Methods 0.000 claims description 4
- 239000000470 constituent Substances 0.000 claims description 2
- 238000010438 heat treatment Methods 0.000 claims 2
- 210000002700 urine Anatomy 0.000 claims 1
- 235000012431 wafers Nutrition 0.000 description 29
- 230000005855 radiation Effects 0.000 description 21
- 239000000178 monomer Substances 0.000 description 18
- 239000003795 chemical substances by application Substances 0.000 description 17
- 238000002474 experimental method Methods 0.000 description 14
- 230000005284 excitation Effects 0.000 description 13
- 230000003287 optical effect Effects 0.000 description 13
- QQONPFPTGQHPMA-UHFFFAOYSA-N propylene Natural products CC=C QQONPFPTGQHPMA-UHFFFAOYSA-N 0.000 description 12
- 125000004805 propylene group Chemical group [H]C([H])([H])C([H])([*:1])C([H])([H])[*:2] 0.000 description 12
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 10
- 239000000919 ceramic Substances 0.000 description 9
- 230000007797 corrosion Effects 0.000 description 6
- 238000005260 corrosion Methods 0.000 description 6
- 239000000945 filler Substances 0.000 description 6
- VEXZGXHMUGYJMC-UHFFFAOYSA-M Chloride anion Chemical compound [Cl-] VEXZGXHMUGYJMC-UHFFFAOYSA-M 0.000 description 5
- 150000002500 ions Chemical class 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 239000000853 adhesive Substances 0.000 description 4
- 230000001070 adhesive effect Effects 0.000 description 4
- 238000001723 curing Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000004033 plastic Substances 0.000 description 4
- 239000011253 protective coating Substances 0.000 description 4
- 206010040844 Skin exfoliation Diseases 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000006378 damage Effects 0.000 description 3
- 229920006334 epoxy coating Polymers 0.000 description 3
- 238000013508 migration Methods 0.000 description 3
- 230000005012 migration Effects 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 2
- 238000003848 UV Light-Curing Methods 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 2
- 230000032683 aging Effects 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- -1 isobornyl acrylic acid Chemical compound 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000010453 quartz Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000035882 stress Effects 0.000 description 2
- FGLXTRRGELKYNO-UHFFFAOYSA-N 4-hydroxy-2-methylidenepentanoic acid Chemical compound CC(O)CC(=C)C(O)=O FGLXTRRGELKYNO-UHFFFAOYSA-N 0.000 description 1
- 206010011376 Crepitations Diseases 0.000 description 1
- 208000037063 Thinness Diseases 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 239000011230 binding agent Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000004132 cross linking Methods 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 239000011353 cycloaliphatic epoxy resin Substances 0.000 description 1
- 125000000113 cyclohexyl group Chemical group [H]C1([H])C([H])([H])C([H])([H])C([H])(*)C([H])([H])C1([H])[H] 0.000 description 1
- 230000035618 desquamation Effects 0.000 description 1
- 239000003085 diluting agent Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 210000002615 epidermis Anatomy 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000004992 fission Effects 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 239000004519 grease Substances 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000005382 thermal cycling Methods 0.000 description 1
- 206010048828 underweight Diseases 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
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- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
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- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
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- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- H01L2224/732—Location after the connecting process
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- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
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Abstract
一种具有晶片载体衬底的晶片载体,并且至少一
个半导体晶片以倒装晶片结构的形式,通过焊球安装
在晶片载体衬底的电路化表面上。焊球被含有环氧
树脂的合成物所形成的第一种密封剂所密封。此外,
位于电路化表面的至少一部分电路被含有尿脘的合
成物所组成的第二种密封剂所密封,此合成物选择
后,第二种密封剂就具有了等于或小于100磅/英
寸2的弹性模量。
Description
本发明一般涉及晶片载体,尤其涉及一种具有电路化表面的晶片载体,该电路表面至少部分被一种具有保护性的,经过紫外线(UV)辐射处理过的涂层所覆盖。
半导体封装的一种类型包括在衬底的电路化表面装有一个或多个半导体晶片,衬底可为陶瓷衬底或塑料衬底。这种半导体晶片封装通常被称为晶片载体,它通常安装在印刷电路卡或印刷电路板上。如果使用表面安装的话,那么晶片载体通常包括一个引线框或边缘引脚机械地和电气地接在衬底载有晶片的表面化电路周边形成的电触点上。
在所谓的倒装晶片(flip chip)结构中,通过在晶片载体衬底的电路化表面安装一个或更多个半导体晶片,可以容易地获得比较高的晶片连接密度。在此结构中,晶片面朝下地使用焊球安装在衬底上的可焊接金属衬垫上。然而,由于石英晶片的热膨胀系数(CTE)和陶瓷衬底或塑料衬底的CTE有很大的差别,因此,如果晶片载体受到热波动,那么焊球连接处就会受到较大的应力作用,这种情况会减少或降低球连接的疲劳寿命。这个难题可以通过使用一种CTE小于焊球CTE的30%的密封剂来密封焊球而得到解决。所使用的密封剂的成分包括环氧树脂粘合剂,如环脂肪族环氧树脂粘合剂和填充剂,如高纯度的熔融硅或非晶硅,这已在美国专利No.4,999,699中公开,该专利在此作为参考。正如该专利中所指出的,粘合剂在室温下的粘度不大于约1000厘泊,填充剂的最大颗粒尺寸不大于31微米。而且,粘合剂应大约占粘合剂和填充剂总重量的60%到25%,填充剂应大约占总重量的40%到75%。
晶片载体衬底的电路化表面上的电路和在较小程度上在电路化表面以倒装晶片结构安装的晶片,应加以保护,以免受机械和外界的危害。为了获得这种保护,一种技术是在晶片和该电路化表面的至少一部分电路上安装一个陶瓷盖。当使用这种陶瓷盖以获得机械和外界的保护时,显著增加了晶片载体的成本。而且,这种陶瓷盖的存在排除了在晶片上直接安装一个散热片,以消散晶片所产生的热量的可能性。从而必须在陶瓷盖上安装散热片,同时,必须在每个晶片的上表面和陶瓷盖之间加有导热油脂以便在晶片和散热片之间获得良好的热接触。尽管用这种方法消散热量是有效的,但是如果直接在晶片上安装散热片则更为方便。
前面已经提出了用含有环氧树脂粘合剂和填充剂的涂层覆盖于晶片载体衬底的电路化表面上的电路,以便用相对低的费用来对此电路提供机械和外界的保护方法,把这种填充的环氧树脂层应用于晶片的上表层(不含电路)已被证实是有效的。然而,人们已认识到将它用作保护晶片载体电路化表面的电路的保护性涂层时,该填充的环氧树脂涂层必须具备:
(1)能经得起标准的,加速的热老化实验。实验中,该涂层以每小时三次循环的频率,经受温度为0℃到100的热循环,并至少进行2000次该循环,这样仍不出现内部裂纹或者在涂层与焊球的密封物交界面上的裂纹。因为这些裂纹能使水和其它不期望的化学物质进入并腐蚀电路,所以是不希望出现的。(2)具有疏水性,原因同上。(3)能够经得起第二种标准的热循环实验,通常被称为“装运冲击”(ship shock)实验。在实验中,该涂层受热频率为每小时一次,每次受热循环温度为-40℃到+65℃,该循环至少要进行10次,这样仍不出现裂纹或者涂层从晶片载体衬底剥离的现象;(4)具有低的离子浓度。典型的可通过确保氯化物离子的浓度少于百万分之十来获得,这样就能避免电路的腐蚀和导体的迁移,后者会导致不期望出现的短路;和(5)能相对快的从而方便地固化。
值得注意的是,当上述填充的环氧树脂涂层从晶片载体电路表面的晶片的上表面扩展到具有较大尺寸如26mm×36mm的晶片载体电路化表面的电路上时,这些涂层已证明失去了作用。就是说,当此涂层受到前面所述的加速热老化实验时,涂层就必然会出现内部裂纹或者在涂层与焊球密封物的交界面上出现裂纹。此外,这些涂层通常具有疏水性。而且,当此涂层受到前述的“装载冲击”试验时,它就会出现裂纹或者从晶片载体衬底上剥离。此外,这些涂层必须在烘箱里烘相当长一段时间,如三小时才能固化,这样既费时又不方便。
因此,到目前为止,那些从事晶片载体开发的人们一直在寻求一种保护晶片载体电路化表面上的电路的保护性涂层,但没有成功。这种涂层必须:(1)相对来说较便宜;(2)能经得起标准的热循环实验而不引起裂纹或剥离,能为电路提供有效的机械和外界的保护。(3)具有疏水性;(4)具有低的离子浓度,例如氯化物离子的浓度低于百万分之十;(5)反应性相对快,容易固化;和(6)允许散热片直接安装在晶片上。
本发明涉及一种发现,即上述的环氧树脂涂层用作晶片载体电路化表面上电路的保护性涂层,该涂层具有相对高的弹性模量,即,在室温下(25℃)弹性模量大于约10000磅/吋2(69MPa)。因此,此涂层缺少经受上述的热循环实施所引起的应力的柔性,而导致出现裂纹和剥离。
本发明也涉及一种发现,即通过适当选取数量相对适当的丙烯酸尿脘齐聚物、丙烯酸单体和光激发剂作为涂层的成分,利用紫外线辐射,能相当快在固化,如在5秒钟以内固化,产生相对便宜的,具有疏水性的,在室温下具备弹性模量等于或小于10000磅/吋2的涂层。因此,此涂层能容易地经受热循环实验而不引起裂纹和剥离现象。除此以外,此涂层氯化物离子浓度小于百万分之十,因此,不会出现离子引入而发生的腐蚀和迁移现象。而且,如果不把此涂层抹在电路化表面上的晶片的上表面,那么就能容易地把散热片直接安装在晶片上。
本发明结合附图进行描述。该图是根据本发明的晶片载体的最佳实施例的横截面图,此晶片载体含有一覆盖于其至少一部分电路化表面的保护性涂层。
本发明涉及一种晶片载体,包括晶片载体衬底,例如陶瓷衬底或塑料衬底,在其电路化表面安装有至少一个倒装晶片结构的半导体晶片。在其至少一个半导体晶片和晶片载体衬底之间的焊球连接物用密封剂密封,该密封剂包括比如环氧树脂,其CTE小于焊球CTE的30%。此外,该电路化表面的至少一部分电路被一种具有保护性的,相对便宜的涂层所覆盖,涂层组成成分的选择按照本发明,应该:(1)能容易地经得起上述的热循环实验,而不出现任何的内部裂纹和在涂层和焊球密封剂交界处的界面裂纹,同时,即使在10倍的显微镜下观看也不出现剥离现象;(2)具有疏水性;(3)其氯化物离子的浓度低于百万分之十;(4)利用UV辐射能相对快且方便地固化和(5)允许把散热片直接安装在晶片上。
如附图所描述的最佳实施例,根据本发明的晶片载体10,包括衬底20,例如陶瓷衬底(如矾土衬底)或塑料衬底。在此衬底20具有一电路化表面30,此表面含有电子线路(未示出)和一个例如铜制成电接触衬垫40。至少一个半导体晶片50,如石英晶片,利用焊球60以倒装晶片结构式安装在电路表面30上。焊球的成份为重量占3%的锡和97%的铅。为了使晶片50和衬底20之间的焊球连接60牢固,延长它的疲劳寿命,焊球60用一种CTE小于焊球60CTE的30%的密封剂70来密封。焊球密封剂70的成分包括环氧树脂粘合剂,如环脂肪族聚环氧化合物粘合剂和填充剂,如高纯度的熔融态或非晶体硅,如美国专利4999699中所述。
晶片载体10还包括金属引线框或例如用铜制成的边缘引脚,并机械地和电气地与接触衬垫40连接。优选的例子已在S.R.Engle等人于1992年2月18日递交的美国专利申请No.07,838,613中公开。并在此作为参考。在引线框或边缘引脚80与接触衬垫40的每一个的机械的/电气的连接处具有一个焊接区90,它的成份包括重量分别为10%的锡或和90%的铅。在接触衬垫40和引线框或边缘引脚80之间的每个焊接处至少部分,最好是全部被物质区100所密封。根据专利申请No.07 838613的教导,当焊接区90和物质区100之间的连接受到温度为0℃到100℃,循环次数为每小时三次,至少2000次这样的正弦曲线热循环作用时,焊区90出现的电阻增加小于200毫欧。根据专利申请No.07 838613的教导,采用CTE为焊接区90CTE的±30%以内的填充的环氧树脂作为物质区100,就能达到上述结果。一种有用的环氧树脂是部分填入了硅填剂的环己基二环氧树脂化合物,它是美国加利福尼亚洲德克斯特(Dexter)公司的产品,商品名称Hysol FP0045。
根据本发明,除了电接触衬垫40以外,在密封的焊球60的外部的位于电路化表面30的电路至少一部分最好全部被涂层110覆盖而密封,用来保护受覆盖的电路免受机械和外界的危害。涂层110也接触并至少部分环绕着密封焊球的密封剂70。正如下面将会全面地讨论,通过使用一喷射器,可把用来形成涂层110的合成物分布到电路表面30上,分布后,该物质容易地流到电路表面上并覆盖暴露的电路。而且,此后,利用UV辐射该合成物则相对较快并方便地固化。
根据本发明,用以形成涂层110的合成物包括三种成份:(1)丙烯酸尿脘齐聚物;(2)丙烯酸单体;和(3)光激发剂。在这三种物质中,丙烯酸尿脘齐聚物用以使相应的涂层110具有疏水性。丙烯酸单体用作丙烯酸尿脘齐聚物的稀释剂,并且当此分布的合成物受到紫外线的辐射时,它用于与后者的交联。光激发剂使交联在紫外辐射的影响下,可能实现。
本发明中,可以使用多种的丙烯酸尿脘齐聚物,丙烯酸单体和光激发剂。在这方面,已经发现主要是齐聚物和单体的结合决定了相应涂层110的弹性。人们凭经验发现通过使用这样的齐聚物和单体(以及光激发剂)可以得到由丙烯酸尿脘齐聚物和丙烯酸单体所形成的有用的具有弹性的结合物,用紫外线辐射使它们固化,然后,可使用常规的拉力实验,在温室下测得所产生的涂层110的弹性模量。如果所测量的值小于或等于约10000磅/吋2,那么齐聚物和单体相应的结合物在本发明中就是有用的,至少它能产生具有有用的弹性特性的涂层110。
现已进一步发现齐聚物,单体和光激发剂的合成物决定了所产生涂层110的氯化物离子浓度,因此决定了因离子引入所产生的腐蚀和迁移的程度。而且,通过在晶片载体的电路化表面上形成相应的齐聚物,单体和光激发剂的合成物,凭经验发现即可形成有用的结合物,用紫外辐射使其固化,然后测量所产生的涂层抵抗腐蚀的能力。其方法也就是把覆盖涂层的电路化表面暴露于空气温度为85℃,相对湿度为80%的环境中1000小时,就可以确定。
如果任意一电路线路的直流电阻增加100%或更多,其电路化表面受到了严重的腐蚀,不能接受。把覆盖层涂层的电路化表成暴露于空气温度为85℃,相对湿度为80%的环境中,并受10伏的偏置电压不断作用1000小时,就可以查明迁移现象。如果在任意二个相邻电路线路之间的直流电阻小于10兆欧,其电路化表面就受到了严重的腐蚀,故不能接受。
除了对由于离子引入而引起的腐蚀和迁移的要求以外,对本发明有用的光激发剂必须能够使有用的丙烯酸尿脘齐聚物能够在紫外线辐射的作用下,基本上完全地和有用的丙烯酸单体交联,紫外线辐射的强度和时间将在以下讨论,有用的光激发剂可以依据下面的实验,凭经验而找到。首先把一种光激发剂添加到包含有用的丙烯酸尿脘齐聚物和有用的丙烯酸单体的合成物中,然后把产生的合成物进行紫外线辐射,其强度和时间在以下将具体规定,就能制造出第一涂层样品。第一涂层洋品所具有的断裂应力可通过常规的拉力实验来测得。该断裂应力是用来测量交联程度的,把含有同样的齐聚物,单体和光激发剂的另一种合成物,以同样的强度进行同样的UV辐射,但时间长一点或者以同样的时间,但辐射强度高一点,可以制得第二种这样的涂层样品。如果所测得的第二涂层样品的断裂应力比第一涂层的大,那么就表明第二涂层样品受到了附加的交联。另一方面,如果第二涂层样品的断裂应力没有变化,那么就假定该第一涂层样品获得了完全的或基本完全的交联。如果为获得此种彻底的交联所需的紫外线辐射的强度和辐射时间落入了下面将要给出的范围之内,那么这种相应的光辐射剂对本发明就是有用的。否则,这种光辐射剂对本发明就是没有用处的。
在以上步骤所需的有用的丙烯酸尿脘齐聚物,可使用伊利诺斯洲芝加哥市摩顿(Morton)公司所出售的商品名称为ZL2196和ZL1365的丙烯酸尿脘齐聚物。类似地,人们发现象异冰片基丙烯酸和2-羟基丙基丙烯酸这样的丙烯酸单体与ZL2196或ZL1365丙烯酸尿脘齐聚物相结合在发明中是有用的,同时,以下三种光激发剂和上述任何一种齐聚物和单体相混合,都可用于本发明。它们是:
1)2-甲基-1-(4-(甲硫基)-苯基)-2-吗啉代丙酮;
2)异丙基硫占吨酮;和
3)2-羟基-2-甲基-1-苯基丙烷-1-酮。
如前已提及,这种有用的合成物的三种成份的相对数量也是重要的,例如,丙烯酸尿脘齐聚物应当占该合成物重量的约35%到75%,最好占合成物重量的65%,若其所占份量小于35%,就是不理想的。因为这样此相应的涂层110就具有高于10000磅/吋2的弹性模量,因此当涂层受到如上所述的热循环实验时,它就产生内部裂纹和交界面裂纹并出现剥离现象。另一方面,其份量超过约75%也不希望,因为这样相应的合成物就具有了不希望具有的高的粘度,难以用喷射器把该合成物分散到涂层上,并导致该暴露在电路上的合成物难以流动。
丙烯酸单体应当相应地构成该有用的合成物重量的约63.5%到约22.5%,其份量超过此范围之外是不希望出现的,其原因同上。
光激发剂相应地应当占此有用的合成物的重量的约1.5%到约2.5%,其份量不足约1.5%是不好的。因为它使齐聚物和单体不能充分交联。其份量超过约2.5%也没有必要,因为2.5%足以使它们获得充分的交联。
正如上所提到的,通过一喷射器,可以容易地把以上所限定的有用的合成物分散到衬底20的电路化表面30上。这些合成物能容易地在表面30上流动以覆盖此暴露的电路。同时,在毛细作用的影响下,涂层能容易地流到焊球密封剂70的侧面上,并覆盖和围绕此密封剂。
此有用的化合物分布好后,可以很容易用紫外线辐射使其固化。可用的紫外线(UV)的波长为200到400毫微米。可用的UV强度范围为每平方厘米5.5到6.5焦耳,相应的辐射时间为从约5到30秒。UV辐射强度低于约5.5焦耳/厘米2是不好的,因为它将导致齐聚物和单体不能充分交联。UV强度高于约6.5焦耳/厘米2也没有必要,因为在较低的辐射强度下已能实现充分交联。实际上,相对较高的辐射强度会导致粘接裂变而起反作用。能够以上述特定的强度和时间辐射紫外线和紫外线辐射源,例如UV固化系统,可从Rockville,Maryloand的Fusion UV Curing System买到,该系统装备有D和H灯。
涂层110的厚度最好超过其下的,受保护的电路厚度约0.020英寸。涂层的厚度大一点是有利的,然而,用上述特定的厚度就可以容易地获得它对机械及外界方面的有效保护。
当用上述步骤把此有用的合成物分布并用紫外线固化后,所产生的涂层110就能抵抗住循环温度从0到100℃,频率为每小时3次,至少进行2000次的热循环,同时在10倍的光学显微镜下观察不到内部和交界面裂纹。当然,这种热循环是在一个具有控制系统的烘箱里进行的,该系统并不完全按照上述的热循环技术要求运行。实际上,每个完整的热循环期间为20/±2分钟(而不是准确的20分钟)。此外,温度从10℃上升到90℃和时间为6+3/-2分。温度从90℃下降到10℃时间也是6+3/-2分钟。而且,当烘箱到达峰值温度100+/-10℃时,其相应的停留时间为4+/-2分钟。进一步,烘箱到达最低温度0+/-10时,其相应的停留时间也是4+/-2分钟。因此,对本发明来说,表示在后者的(实际上的)热循环条件可以看成是前者的(理想的)热循环条件。
根据本发明形成的涂层110也能容易地抵抗“运载冲击”实验,在此实验中,涂层受到的循环温度为从-40℃到+65℃。频率为每小时1个循环,至少进行10次这样的循环。这样涂层仍不会从电路化表面30上剥离,同时在10倍光学显微镜下观察,也不出现裂纹。和前面的一样这种“运载冲击”实验是在一个具有控制系统烘箱里进行的,这种系统运行并不完全符合“运载冲击”热循环的条件。实际上,其最小的循环温度是-40+/-5℃,最大的循环温度为+65+/-5℃,除此以外,当总的热循环闪数为至少10次时,该循环频率就为每小时1+/-0.1个循环(而不是准确的每小时1个循环)。而且,在最高温度和最低温度处的停留时间都是25+/-7分钟,在最高温度和最低温度之间的温度处,温度的上升或下降速率为每分钟15℃。同上,对本发明来说,后者(实际上)的热循环条件可视为前者的(理想的)热循环条件。
此有用的合成物除了用于电路化表面30外,通过一喷射器,也可以容易地把它应用于晶片50的上层暴露的表面。这样,经过UV固化后,形成的涂层能保护晶片50和电路表面30免受机械和外界的危害。然而,如果没有在晶片50的上层表面形成涂层,那么就很容易地直接把散热片安装在晶片50的上层表面上,如附图所描绘。
本发明结合最佳实施例,进行了详细地描述,在此领域熟练的人员可以理解到,在不背离本发明的精神和范围的前提下,其中的形式和细节可以做出不同的变化。
Claims (6)
1、一种晶片载体,其特征在于:
一个在其表面具有电子线路的衬底;
至少有一个半导体晶片通过导电的焊球安装在所述表面。焊球至少部分被第一种密封剂所密封,密封剂的成分含有环氧树脂。并且它的热膨胀系数(CTE)小于焊球CTE的30%,
第二种密封剂覆盖并密封着位于所述的衬底表面的至少一部分电子线路,同时,它接触并至少部分环绕着所述第一种密封剂的至少一部分,其特征在于:
所述第二种密封剂的组成成份含有尿脘,并且选择所述合成物以使第二种密封剂的弹性模量在25℃时,等于或小于1000磅/吋2。
2、权利要求1的晶片载体,其特征在于:所述第二种密封剂的组成成分选择以使当所述晶片载体受到温度0至100℃之间的热循环,频率为每小时三次,至少循环2000次的循环加热时,在10倍的光学显微镜下观看,所述第二种密封剂既不出现内部裂纹,也不在所述第一和第二密封剂的交界面上出现裂纹。
3、权利要求1的晶片载体,其特征在于:所述第二种密封剂的成分的选择使得,当该晶片载体受到温度为-40℃到+65℃,循环频率为每小时一次,至少进行十次的循环加热时,该第二密封剂在10倍的光学显微镜下观看,既不从衬底上剥离,也不出现裂纹。
4、权利要求1的晶片载体,其特征在于:所述第二种密封剂也覆盖并密封所述至少一个半导体晶片的至少一部分上层的暴露表面。
5、权利要求1的晶片载体,其特征在于:所述第二种密封剂是经紫外线固化的密封剂。
6、权利要求1的晶片载体,其特征在于一个散热片直接安装在所述至少一个半导体的上层暴露的表面。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/909,368 US5249101A (en) | 1992-07-06 | 1992-07-06 | Chip carrier with protective coating for circuitized surface |
US07/909,368 | 1992-07-06 |
Publications (2)
Publication Number | Publication Date |
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CN1081787A true CN1081787A (zh) | 1994-02-09 |
CN1028937C CN1028937C (zh) | 1995-06-14 |
Family
ID=25427125
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Application Number | Title | Priority Date | Filing Date |
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CN93108062A Expired - Fee Related CN1028937C (zh) | 1992-07-06 | 1993-06-28 | 一种在电路化表面覆盖着护涂层的芯片底座 |
Country Status (12)
Country | Link |
---|---|
US (1) | US5249101A (zh) |
EP (1) | EP0578307B1 (zh) |
JP (1) | JP2501287B2 (zh) |
KR (1) | KR960015924B1 (zh) |
CN (1) | CN1028937C (zh) |
AT (1) | ATE143529T1 (zh) |
CA (1) | CA2091910C (zh) |
DE (1) | DE69305012T2 (zh) |
ES (1) | ES2092216T3 (zh) |
MY (1) | MY108750A (zh) |
SG (1) | SG44362A1 (zh) |
TW (1) | TW230272B (zh) |
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- 1992-07-06 US US07/909,368 patent/US5249101A/en not_active Expired - Lifetime
-
1993
- 1993-03-18 CA CA002091910A patent/CA2091910C/en not_active Expired - Fee Related
- 1993-04-26 TW TW082103193A patent/TW230272B/zh active
- 1993-06-07 JP JP5136147A patent/JP2501287B2/ja not_active Expired - Lifetime
- 1993-06-08 MY MYPI93001105A patent/MY108750A/en unknown
- 1993-06-28 CN CN93108062A patent/CN1028937C/zh not_active Expired - Fee Related
- 1993-06-28 KR KR1019930011870A patent/KR960015924B1/ko not_active IP Right Cessation
- 1993-07-01 AT AT93201907T patent/ATE143529T1/de not_active IP Right Cessation
- 1993-07-01 EP EP93201907A patent/EP0578307B1/en not_active Expired - Lifetime
- 1993-07-01 DE DE69305012T patent/DE69305012T2/de not_active Expired - Fee Related
- 1993-07-01 SG SG1995002312A patent/SG44362A1/en unknown
- 1993-07-01 ES ES93201907T patent/ES2092216T3/es not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
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ATE143529T1 (de) | 1996-10-15 |
DE69305012D1 (de) | 1996-10-31 |
SG44362A1 (en) | 1997-12-19 |
JP2501287B2 (ja) | 1996-05-29 |
KR940002031A (ko) | 1994-02-16 |
ES2092216T3 (es) | 1996-11-16 |
US5249101A (en) | 1993-09-28 |
CN1028937C (zh) | 1995-06-14 |
KR960015924B1 (ko) | 1996-11-23 |
EP0578307B1 (en) | 1996-09-25 |
MY108750A (en) | 1996-11-30 |
JPH0697309A (ja) | 1994-04-08 |
TW230272B (zh) | 1994-09-11 |
CA2091910C (en) | 1996-07-30 |
EP0578307A2 (en) | 1994-01-12 |
EP0578307A3 (en) | 1994-08-24 |
CA2091910A1 (en) | 1994-01-07 |
DE69305012T2 (de) | 1997-04-03 |
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