KR930018750A - 씨모오스 트랜지스터의 제조방법 - Google Patents

씨모오스 트랜지스터의 제조방법 Download PDF

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KR930018750A
KR930018750A KR1019920002484A KR920002484A KR930018750A KR 930018750 A KR930018750 A KR 930018750A KR 1019920002484 A KR1019920002484 A KR 1019920002484A KR 920002484 A KR920002484 A KR 920002484A KR 930018750 A KR930018750 A KR 930018750A
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South Korea
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conductive
region
transistor
device region
substrate
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KR1019920002484A
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KR950006489B1 (ko
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강준섭
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김광호
삼성전자 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823878—Complementary field-effect transistors, e.g. CMOS isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

본 발명은 반도체장치 중 씨모오스 트랜지스터 소자의 제조공정을 간소화하기 위한 것이다. 이를 위해 씨모오스 트랜지스터 소자의 피모오스 트랜지스터의 소오스 및 드레인(58)을 형성할 시 마스크를 사용하지 않고 피형의 이온을 주입시키는 공정을 실시하여 피모오스 트랜지스터의 소오스 및 드레인(58)을 형성하고 그 이후 엔모오스 트랜지스터 영역만을 노출시키는 마스크(58)을 형성하고 그 이후 엔모오스 트랜지스터 영역만을 노출시키는 마스크(61)를 이용하여 엔형의 이온을 주입하는 공정을 실시하여 상기 엔모오스 트랜지스터의 소오스 및 드레인(60)을 형성한다.

Description

씨모오스 트랜지스터의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2a도 내지 제2d도는 본 발명에 의한 씨모오스회로의 제조공정도.

Claims (3)

  1. 제1도전형의 반도체기판과, 상기 기판내에서 소자 분리 영역에 의해 서로 전기적으로 분리되는 제1 및 제2소자영역과, 상기 제1소자 영역에 형성된 상기 제1도전형과 반대도전형인 제2도전형의 웰과, 상기 각 소자영역 상부에 절연막을 중간층으로 하는 제1 및 제2도전층을 구비하는 씨모오스 트랜지스터의 제조방법에 있어서, 상기 기판 상부로 제2도전형의 불순물을 제1놓도로 이온주입하여 상기 제2소자 영역에 상기 제2도전층의 폭만큼 이격되는 제2도전형의 확산영역을 형성하는 제1공정과, 상기 제1소자영역 상부가 노출되도록 마스크 패턴을 형성하는 제2공정과, 상기 기판 상부로 부터 제1도전형의 상기 제1농도보다 실질적으로 높은 제2농도로 이온주입하여 상기 제1소자 영역에 상기 제1도전층의 폭만큼 이격되는 제2도전형의 확산 영역을 형성하는 제3공정을 순차적으로 구비하여 상기 제1소자 영역과 제2소자 영역에 서로 반대 도전형의 채널을 갖는 트랜지스터를 형성함을 특징으로 하는 씨모오스 트랜지스터의 제조방법.
  2. 제1항에 있어서, 상기 제1공정의 이온주입이 브론을 사용하여 (1~3)x1015ions/㎠의 도우즈와25~40Kev의 에너지로 실시됨을 특징으로 하는 씨모오스 트랜지스터의 제조방법.
  3. 제2항에 있어서, 상기 제3공정의 이온주입이 비소를 사용하여 (6~9)x1015ions/㎠의 도우즈와80~100Kev의 에너지로 실시됨을 특징으로 하는 씨모오스 트랜지스터의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920002484A 1992-02-19 1992-02-19 씨모오스 트랜지스터의 제조방법 KR950006489B1 (ko)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1019920002484A KR950006489B1 (ko) 1992-02-19 1992-02-19 씨모오스 트랜지스터의 제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019920002484A KR950006489B1 (ko) 1992-02-19 1992-02-19 씨모오스 트랜지스터의 제조방법

Publications (2)

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KR930018750A true KR930018750A (ko) 1993-09-22
KR950006489B1 KR950006489B1 (ko) 1995-06-15

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