KR930009018A - 반도체장치의 제조방법 - Google Patents

반도체장치의 제조방법 Download PDF

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KR930009018A
KR930009018A KR1019920019130A KR920019130A KR930009018A KR 930009018 A KR930009018 A KR 930009018A KR 1019920019130 A KR1019920019130 A KR 1019920019130A KR 920019130 A KR920019130 A KR 920019130A KR 930009018 A KR930009018 A KR 930009018A
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semiconductor layer
crystal semiconductor
single crystal
semiconductor device
layer
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KR1019920019130A
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KR970003848B1 (ko
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다카시 잇뽀시
가즈유키 스가하라
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시키모리야
미쓰비시덴키 가부시키가이샤
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Priority claimed from FR929205746A external-priority patent/FR2691288B1/fr
Priority claimed from JP4140800A external-priority patent/JPH05166839A/ja
Application filed by 시키모리야, 미쓰비시덴키 가부시키가이샤 filed Critical 시키모리야
Publication of KR930009018A publication Critical patent/KR930009018A/ko
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Publication of KR970003848B1 publication Critical patent/KR970003848B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
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    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
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    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
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    • H01L21/02656—Special treatments
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76272—Vertical isolation by lateral overgrowth techniques, i.e. ELO techniques
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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
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    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Ceramic Engineering (AREA)
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Abstract

SOI구조의 반도체장치의 제조방법에 있어서 열처리나 산화처리나 산화처리에 의해 또는 연마처리에 의해 단결정반도체층에 새롭게 결정결함이 발생하는 것을 방지한다.
결정결함의 발생이 억제되고, 특성의 흐트러짐이 작은 능동소자를 구비한 SOI구조의 반도체장치를 제공한다.
절연층위에 형성된 비단결정반도체층이 소정의 온도분포를 갖도록 용융시킴으로써, 비단결정 반도체층을 단결정화시킨다(501).
얻어진 단결정 반도체층에 열처리를 하기전에 용융시의 고온부에 대응하는 부분을 선택적으로 제거한다(502).
얻어진 도상 단결정 반도체층에 능동소자를 형성한다(504).
능동소자를 형성하기 전에 도상단결정 반도체층의 표면을 연마에 의해 평활하게 해도된다(503).
도상 단결정 반도체층은 결정아립계를 포함하지 않는다.

Description

반도체장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 이 발명에 따른 반도체 장치의 제조방법의 제1실시예의 제1공정을 표시하는 단면도,
제2도는 이 발명에 따른 반도체 장치의 제조방법의 제1실시예의 제2공정을 표시하는 단면도,
제3도는 이 발명에 따른 반도체 장치의 제조방법의 제1실시예의 제3공정을 표시하는 단면도.

Claims (2)

  1. 재결정 실리콘층을 갖는 반도체 장치로서, 절연체층과, 상기 절연체층의 표면상에 형성되고, 결정아립계를 포함하지 않는 단결정 실리콘 도(島)와 상기 단결정 실리콘도 내에 형성된 영역을 포함하는 트랜지스터를 구비한 반도체장치.
  2. 절연체층 위에 형성된 반도체층내에 능동영역을 구비한 반도체 장치의 제조방법으로서, 비단결정반도체층을 가열하고, 소정의 온도분포를 갖도록 용융시켜서 상기 비단결정 반도체층을 단결정 반도체층으로 변화하는 공정과, 상기 용융시의 온도분포에서 고온부에 대응하는 상기 단결정반도체층의 일부분을 선택적으로 제거함으로써, 도상단결정 반도체층을 형성하는 공정과 상기 도상 단결정반도체층을 처리해서 상기 도상단결정 반도체층에 능동소자를 형성하는 공정을 구비하는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019920019130A 1991-10-17 1992-10-17 반도체 장치 및 그 제조방법 KR970003848B1 (ko)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP91-269396 1991-10-17
JP26939691 1991-10-17
FR929205746A FR2691288B1 (fr) 1992-05-04 1992-05-12 Procede de formation de films semi-conducteurs monocristallins.
JP92-140800 1992-06-01
JP4140800A JPH05166839A (ja) 1991-10-17 1992-06-01 半導体装置およびその製造方法

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KR930009018A true KR930009018A (ko) 1993-05-22
KR970003848B1 KR970003848B1 (ko) 1997-03-22

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6348715B1 (en) 1997-12-15 2002-02-19 Lg Semicon Co., Ltd. SOI (silicon on insulator) device
KR100281109B1 (ko) * 1997-12-15 2001-03-02 김영환 에스오아이(soi)소자및그의제조방법
US6261886B1 (en) * 1998-08-04 2001-07-17 Texas Instruments Incorporated Increased gate to body coupling and application to DRAM and dynamic circuits
US20020066899A1 (en) 2000-08-04 2002-06-06 Fitzergald Eugene A. Silicon wafer with embedded optoelectronic material for monolithic OEIC
US6294413B1 (en) * 2000-12-27 2001-09-25 Vanguard International Semiconductor Corp. Method for fabricating a SOI (silicon on insulator) device
US6602758B2 (en) 2001-06-15 2003-08-05 Agere Systems, Inc. Formation of silicon on insulator (SOI) devices as add-on modules for system on a chip processing
US6713819B1 (en) * 2002-04-08 2004-03-30 Advanced Micro Devices, Inc. SOI MOSFET having amorphized source drain and method of fabrication
JP3890270B2 (ja) * 2002-07-19 2007-03-07 Ｎｅｃ液晶テクノロジー株式会社 薄膜トランジスタの製造方法
JP4319078B2 (ja) * 2004-03-26 2009-08-26 シャープ株式会社 半導体装置の製造方法
US9768109B2 (en) * 2015-09-22 2017-09-19 Qualcomm Incorporated Integrated circuits (ICS) on a glass substrate

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0191503A3 (en) * 1980-04-10 1986-09-10 Massachusetts Institute Of Technology Method of producing sheets of crystalline material
JPS59195871A (ja) * 1983-04-20 1984-11-07 Mitsubishi Electric Corp Ｍｏｓ電界効果トランジスタの製造方法
JPS59205712A (ja) * 1983-04-30 1984-11-21 Fujitsu Ltd 半導体装置の製造方法
FR2571544B1 (fr) * 1984-10-05 1987-07-31 Haond Michel Procede de fabrication d'ilots de silicium monocristallin isoles electriquement les uns des autres
FR2572219B1 (fr) * 1984-10-23 1987-05-29 Efcis Procede de fabrication de circuits integres sur substrat isolant
EP0235819B1 (en) * 1986-03-07 1992-06-10 Iizuka, Kozo Process for producing single crystal semiconductor layer
US5028564A (en) * 1989-04-27 1991-07-02 Chang Chen Chi P Edge doping processes for mesa structures in SOS and SOI devices
US5039621A (en) * 1990-06-08 1991-08-13 Texas Instruments Incorporated Semiconductor over insulator mesa and method of forming the same

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US5528054A (en) 1996-06-18

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