KR930001078A - 컴퓨터 시스템 - Google Patents

컴퓨터 시스템 Download PDF

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Publication number
KR930001078A
KR930001078A KR1019920010807A KR920010807A KR930001078A KR 930001078 A KR930001078 A KR 930001078A KR 1019920010807 A KR1019920010807 A KR 1019920010807A KR 920010807 A KR920010807 A KR 920010807A KR 930001078 A KR930001078 A KR 930001078A
Authority
KR
South Korea
Prior art keywords
address
control
computer system
bundle
data exchange
Prior art date
Application number
KR1019920010807A
Other languages
English (en)
Korean (ko)
Inventor
잔드벨드 프레데릭
밴트 마티아스
도미니쿠스 얀센 마셀
Original Assignee
프레데릭 얀 스미트
엔.브이.필립스 글로아이람펜파브리켄
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 프레데릭 얀 스미트, 엔.브이.필립스 글로아이람펜파브리켄 filed Critical 프레데릭 얀 스미트
Publication of KR930001078A publication Critical patent/KR930001078A/ko

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Multi Processors (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
KR1019920010807A 1991-06-24 1992-06-22 컴퓨터 시스템 KR930001078A (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP91201610.2 1991-06-24
EP91201610 1991-06-24

Publications (1)

Publication Number Publication Date
KR930001078A true KR930001078A (ko) 1993-01-16

Family

ID=8207737

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019920010807A KR930001078A (ko) 1991-06-24 1992-06-22 컴퓨터 시스템

Country Status (4)

Country Link
US (1) US5659797A (US06272257-20010807-P00018.png)
EP (1) EP0523764A2 (US06272257-20010807-P00018.png)
JP (1) JPH05265971A (US06272257-20010807-P00018.png)
KR (1) KR930001078A (US06272257-20010807-P00018.png)

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US6338106B1 (en) 1996-12-20 2002-01-08 Pact Gmbh I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures
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US6542998B1 (en) 1997-02-08 2003-04-01 Pact Gmbh Method of self-synchronization of configurable elements of a programmable module
DE19704742A1 (de) 1997-02-11 1998-09-24 Pact Inf Tech Gmbh Internes Bussystem für DFPs, sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstrukturen, zur Bewältigung großer Datenmengen mit hohem Vernetzungsaufwand
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US6061749A (en) 1997-04-30 2000-05-09 Canon Kabushiki Kaisha Transformation of a first dataword received from a FIFO into an input register and subsequent dataword from the FIFO into a normalized output dataword
AUPO647997A0 (en) 1997-04-30 1997-05-22 Canon Information Systems Research Australia Pty Ltd Memory controller architecture
US6195674B1 (en) 1997-04-30 2001-02-27 Canon Kabushiki Kaisha Fast DCT apparatus
US6414687B1 (en) 1997-04-30 2002-07-02 Canon Kabushiki Kaisha Register setting-micro programming system
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US8686549B2 (en) 2001-09-03 2014-04-01 Martin Vorbach Reconfigurable elements
DE19861088A1 (de) 1997-12-22 2000-02-10 Pact Inf Tech Gmbh Verfahren zur Reparatur von integrierten Schaltkreisen
DE19807872A1 (de) 1998-02-25 1999-08-26 Pact Inf Tech Gmbh Verfahren zur Verwaltung von Konfigurationsdaten in Datenflußprozessoren sowie Bausteinen mit zwei- oder mehrdimensionalen programmierbaren Zellstruktur (FPGAs, DPGAs, o. dgl.
US6473780B1 (en) * 1998-04-01 2002-10-29 Intel Corporation Scheduling of direct memory access
US8230411B1 (en) 1999-06-10 2012-07-24 Martin Vorbach Method for interleaving a program over a plurality of cells
US7076630B2 (en) * 2000-02-08 2006-07-11 Mips Tech Inc Method and apparatus for allocating and de-allocating consecutive blocks of memory in background memo management
US7502876B1 (en) * 2000-06-23 2009-03-10 Mips Technologies, Inc. Background memory manager that determines if data structures fits in memory with memory state transactions map
US7165257B2 (en) * 2000-02-08 2007-01-16 Mips Technologies, Inc. Context selection and activation mechanism for activating one of a group of inactive contexts in a processor core for servicing interrupts
US7155516B2 (en) * 2000-02-08 2006-12-26 Mips Technologies, Inc. Method and apparatus for overflowing data packets to a software-controlled memory when they do not fit into a hardware-controlled memory
US7058065B2 (en) * 2000-02-08 2006-06-06 Mips Tech Inc Method and apparatus for preventing undesirable packet download with pending read/write operations in data packet processing
US7042887B2 (en) 2000-02-08 2006-05-09 Mips Technologies, Inc. Method and apparatus for non-speculative pre-fetch operation in data packet processing
US7139901B2 (en) * 2000-02-08 2006-11-21 Mips Technologies, Inc. Extended instruction set for packet processing applications
US7649901B2 (en) * 2000-02-08 2010-01-19 Mips Technologies, Inc. Method and apparatus for optimizing selection of available contexts for packet processing in multi-stream packet processing
US20010052053A1 (en) * 2000-02-08 2001-12-13 Mario Nemirovsky Stream processing unit for a multi-streaming processor
US7032226B1 (en) * 2000-06-30 2006-04-18 Mips Technologies, Inc. Methods and apparatus for managing a buffer of events in the background
US7058064B2 (en) * 2000-02-08 2006-06-06 Mips Technologies, Inc. Queueing system for processors in packet routing operations
US7065096B2 (en) * 2000-06-23 2006-06-20 Mips Technologies, Inc. Method for allocating memory space for limited packet head and/or tail growth
US7082552B2 (en) * 2000-02-08 2006-07-25 Mips Tech Inc Functional validation of a packet management unit
JP2004506261A (ja) 2000-06-13 2004-02-26 ペーアーツェーテー　イクスペーペー　テクノロジーズ　アクチエンゲゼルシャフト パイプラインｃｔプロトコルおよびｃｔ通信
US8058899B2 (en) 2000-10-06 2011-11-15 Martin Vorbach Logic cell array and bus system
US6990555B2 (en) * 2001-01-09 2006-01-24 Pact Xpp Technologies Ag Method of hierarchical caching of configuration data having dataflow processors and modules having two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)
US7444531B2 (en) 2001-03-05 2008-10-28 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US7844796B2 (en) 2001-03-05 2010-11-30 Martin Vorbach Data processing device and method
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US7657877B2 (en) * 2001-06-20 2010-02-02 Pact Xpp Technologies Ag Method for processing data
US7996827B2 (en) 2001-08-16 2011-08-09 Martin Vorbach Method for the translation of programs for reconfigurable architectures
US7434191B2 (en) 2001-09-03 2008-10-07 Pact Xpp Technologies Ag Router
US8686475B2 (en) 2001-09-19 2014-04-01 Pact Xpp Technologies Ag Reconfigurable elements
US8281108B2 (en) 2002-01-19 2012-10-02 Martin Vorbach Reconfigurable general purpose processor having time restricted configurations
EP1514193B1 (de) 2002-02-18 2008-07-23 PACT XPP Technologies AG Bussysteme und rekonfigurationsverfahren
US8914590B2 (en) 2002-08-07 2014-12-16 Pact Xpp Technologies Ag Data processing method and device
US7657861B2 (en) 2002-08-07 2010-02-02 Pact Xpp Technologies Ag Method and device for processing data
AU2003286131A1 (en) 2002-08-07 2004-03-19 Pact Xpp Technologies Ag Method and device for processing data
US7394284B2 (en) 2002-09-06 2008-07-01 Pact Xpp Technologies Ag Reconfigurable sequencer structure
JP4700611B2 (ja) 2003-08-28 2011-06-15 ペーアーツェーテー イクスペーペー テクノロジーズ アクチエンゲゼルシャフト データ処理装置およびデータ処理方法
JP2006251916A (ja) * 2005-03-08 2006-09-21 Fujitsu Ltd Ｄｍａ転送システム及びｄｍａ転送方法
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US11314674B2 (en) * 2020-02-14 2022-04-26 Google Llc Direct memory access architecture with multi-level multi-striding

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US4371932A (en) * 1979-07-30 1983-02-01 International Business Machines Corp. I/O Controller for transferring data between a host processor and multiple I/O units
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US5440749A (en) * 1989-08-03 1995-08-08 Nanotronics Corporation High performance, low cost microprocessor architecture

Also Published As

Publication number Publication date
US5659797A (en) 1997-08-19
EP0523764A3 (US06272257-20010807-P00018.png) 1994-02-16
JPH05265971A (ja) 1993-10-15
EP0523764A2 (en) 1993-01-20

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